iter – interlocks luis fernandez december 2014 central interlock system cis v0

ITER – InterlocksLuis Fernandez December 2014

Central Interlock System CIS v0

CERN

PLC Workshop – ITER IO 4-5 December 2014

Why CIS v0?

2

Objectives

Assessment of the methodology

Validation of technical solutions

Definition of strategy for• Operation from Interlock Desk• Non-Critical interface with CODAC• Timestamp and Archiving

CERN


Slow Interlock Prototype

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Before the CIS v0 there was the Slow Interlock Prototype, our first test platform.

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CIS prototype (test platform)

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CIS 1

Eth. Switch Eth. Switch

PIS 21 PIS 21 PIS 11PIS 12a

CIS 2 CIS 2

PIS 12b

Remote I/O

Supervision Station

CIS 1

Remote I/O

Remote I/O

ICS SLOW

TEST

Remote I/O

Remote I/O

Two network branches connected

All PLC reachable from CIS • CIS 1: Full Redundant• CIS 2: Full Redundant + RIO

4 PIS configurations:• PIS 21: Full redundant + RIO • PIS 11: CPU + 2 x CP + RIO• PIS 12a: CPU + CP + RIO• PIS 12b: CPU + CP

Test I/O for measure Response Time

Each PLC keeps track of the following times:• Execution of safety program• CPU execution • Communication

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TEST Cases

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1. Configuration Parameters:• Safety program execution cycle• Priority• Communication load

2. PLC-PLC communications in Safety Program

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TEST Cases

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3. Behavior of the Fault-tolerant configuration

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TEST Cases

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4. Effect of an increasing number of partners in the architecture

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TEST Cases

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5. Complexity in the safety matrix

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TEST Cases

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5. Complexity in the safety matrix

6. Addition of Remote Inputs / Outputs

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Conclusions from test platform

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[11]

1. Management of complex situationFailures are isolated from the rest of the system; the problems of one partner will not affect the performance of the whole system.

2. No advantage of hardwired connections (from I/O to I/O) compared to network.• No advantage in terms of performance, maintainability, cubicle space, integration and scalability.

3. While the CPU can manage the configuration within one cycle interrupt, the response time of the central functions is almost independent from the number of partners and the communication functions.

4. The restoration of the functionality after a master switch over requires 700ms as a minimum, and with four communication instances per PIS (2 F_SEND/2F_RCV) the system can assure restoration times below 1 second.

5. The performance of a central function is below 350ms and local functions based in digital inputs have a performance below 150 ms.

6. The use of analogue inputs can double the time required for a digital input, below 225 ms

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CIS Architecture

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CIS v.0 Architecture

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ITER magnets

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Interlock Function Context

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ITER Magnet powering system

Magnets are distributed over 21 electrical circuits:• 1 Toroidal Field• 6 Poloidal Field• 5 Central Solenoid• 9 Correction Coil

Main components:• Superconducting Magnets• Power Converter• Protective Make Switch• Fast Discharge Unit• Switching Network Unit• Quench Detection System• Cryogenics/Vacuum

CS3U

CS2U

CS1U

CS1L

CS2L

CS3L

PF1

PF6

PF2

PF3

PF4

PF5

CCU1

CCU2

CCU3TF

PF1 PC

CS3U PC

CS2U PC

CS1U PC

CS1L PC

CS2L PC

CS3L PC

PF6 PC

TF PC

PF2 PC

PF3 PC

VS PC

PF4 PC

PF5 PC

9 FDUs

SNU FDU

SNU FDU

SNU FDU

SNU FDU

SNU FDU

SNU FDU

SNU FDU

SNU FDU

FDU

FDU

FDU

FDU

CCU1 PC MS

CCU2 PC

CCU3 PC

CCL1

CCL2

CCL3

CCL1 PC

CCL2 PC

CCL3 PC

CCS1

CCS2

CCS3

CCS1 PC

CCS2 PC

CCS3 PC

MS

MS

MS

MS

MS

MS

MS

MS

PMS

PMS

PMS

PMS

PMS

PMS

PMS

PMS

PMS

PMS

PMS

PMS

PMS

TF

PF1

PF2

PF3

PF4

PF5

PF6

CS3U

CS2U

CS1U

CS1L

CS2L

CS3L

CCU

CCS

CCL

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CIS v0 Architecture

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Protection Modules:• Coil Protection Module• Hardwired Loops

Supervision Architecture:• Supervisor Module• CIS Operation Station• Critical Interlock Logging System• Engineering Workstation

CODAC Interface Module

Simulation Interface: Magnets PBS 11 CPSS PBS 41 Cryo PBS 34 PCS PBS 47

CERN


CPM functions

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Function DETECTIONTF CIRCUIT_QUENCH TF DISCHARGE LOOPTF FDU_SPURIOUS_ACT TF DISCHARGE LOOPCS CIRCUIT_QUENCH CS DISCHARGE LOOPCS1 FDU_SPURIOUS_ACT CS1 DISCHARGE LOOPPF CIRCUIT_QUENCH PF DISCHARGE LOOPCC CIRCUIT_QUENCH CC DISCHARGE LOOPCOORD_FAST_DISCH TF DISCHARGE LOOPCOORD_FAST_DISCH PF/CS DISCHARGE LOOPWRONG_CURRENT_COMB PCSPCS_OK PCSTF SAFE_QDS_FAIL PIS11 - PICTF FDU_OK PIS41 - PICTF PMS_OK PIS41 - PICTF PC_OK PIS41 - PICTF LOSS_CRYO_MAINTAIN PIS34 - PICMECH LOSS_CRYO_MAINTAIN PIS34 - PICCS LOSS_CRYO_MAINTAIN PIS34 - PICPF LOSS_CRYO_MAINTAIN PIS34 - PICPF/CS FDU_OK PIS41 - PICPF/CS PMS_OK PIS41 - PICPF/CS PC_OK PIS41 - PICPF1 PC_ISOLATION_REQ BYP LOOP / PIS41PF6 PC_ISOLATION_REQ BYP LOOP / PIS41CS PC_ISOLATION_REQ BYP LOOP / PIS41TF LOSS_CRYO_START PIS34 - PICCS LOSS_CRYO_START PIS34 - PICPF LOSS_CRYO_START PIS34 - PICMECH LOSS_CRYO_START PIS34 - PICCIS_OK CISPF/CS SAFE_QDS_FAIL PIS11 - PIC

CC FAST DISCHARGE

PF/CS/CC FAST DISCHARGE

PF/CS FAST DISCHARGE

PF1 BYPASS ISOLATION

REMOVE POWER PERMIT

REMOVE POWER PERMIT

REMOVE POWER PERMIT

TF ACCELERATED DISCH

TF ACCELERATED DISCH PF/CS CTRLD DISCH

PF/CS CTRLD DISCH

CKT CTRLD DISCH

PF6 BYPASS ISOLATIONCS BYPASS ISOLATION

REMOVE POWER PERMIT

Action on plasma

INHIBIT NEXT PLASMA PULSE



INHIBIT NEXT PLASMA PULSE DMS*


Action on Magnets

TF FAST DISCHARGE

CS FAST DISCHARGECS1 FAST DISCHARGEPF FAST DISCHARGE

PF/CS CTRLD DISCH

REMOVE POWER PERMIT

CERN


Supervision Module

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WinCC OA Server:

Retrieve data from:• CPM• PIS (Simulator PLC)

Provide data:• CIS Desk• CILS• CODAC Interface

Manual Commands:• Permit• Inhibits• Reset• Overrides

Time Synchronization

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CIS Desk

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WinCC OA Client

Routinely operations• Monitoring• Alarms• Function Reset• Permits / Inhibits

Critical actions• Overrides:

• Masking of Events• Disabling functions• Forcing Actions

• Monitoring of ICS

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CIS Desk

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Operation Display

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CIS Desk

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Powering Display

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CIS Desk

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Override Display

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CODAC Interface

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Non Critical Interface

Supervisor Module

CODAC Interface Module

CODAC Gateway

Information per CKT:• Power Permit• Override Status

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Layout

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CIS v.0 Design (Hardware)

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Cubicle design for 2 Cubicles and 1 19” rack carried out:• Cubicle 1 – Contains the CPM module, Remote I/O’s and Interface PLC for

sending data to CODAC Gateway

CPM Module Remote I/Os Interface PLC

CERN



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Cubicle design for 2 Cubicles and 1 19” rack carried out:• Cubicle 2 – Contains the Simulator module, Remote I/O’s and DLIB boxes and

CIN-P1 and CIN-P2 switches.CIN-P1

CIN-P2

Simulator PLC

Remote I/OsDLI

B’s

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Cubicle design for 2 Cubicles and 1 19” rack carried out:• 19” rack - Houses the Engineering workstation, Supervisor module, CIS desk

and the CODAC gateway along with the CIN-A switchCODAC Gateway

CIS Desk + CILS

Supervisor module

CIN-A

Engineering WS/Simulator HMI

CERN


CIS v.0 Design (Software)

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Software used for CIS V.0:• Engineering workstation comprises the following software for development of

the functional logic code and Simulator HMI :Siemens STEP 7 V 5.5, CFC V7.0 – For defining the hardware configuration, parameterization and Communication logicSiemens Safety Matrix – For defining the Interlock logic for the MagnetSiemens WinCC Flexible – For defining the HMI for Simulator

CERN


CIS v.0 Design (Software)

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Software used for CIS V.0:• Supervisor module and the CIS desk comprises the following software for

development of the Interlock HMI:Siemens WinCC OA – For defining HMI screens, Time stamping and data archiving in CIS V.0

CERN


CIS V.0 Next steps

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Carry out the endurance tests for the Interface boxes and capture the results

Information from the Interface boxes to be read via Profinet and data to be interpreted for diagnostic purpose

Achieve the time stamping for the events in the CIS desk

Carry out performance tests on the CIS V.0 similar to tests carried out in the Slow Interlock Prototype

Use the CIS V.0 as a platform to demonstrate all the proposed processes for integrating, upgrading and maintaining the ICS.

Use the CIS V.0 as a platform to help in developing and improving the CIS V.1

The CIS V0 shall be shipped to Korea in December 2014 to facilitate study for CIS V.1

CERN


Thanks

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iter – interlocks luis fernandez december 2014 central interlock system cis v0

Documents

plc reachable

iter interlocksbehavior

safety program behavior

cis cis

different case scenarios

cpu cp test io

increasing number of

cpu cp riopis