ittc high-performance networkingjpgs/courses/hsnets/lecture-switching-display.pdf ·...

© James P.G. SterbenzITTCHigh-Performance Networking

The University of Kansas EECS 881Switches and Routers

© 2004–2008 James P.G. Sterbenz1 October 2008

James P.G. Sterbenz

Department of Electrical Engineering & Computer ScienceInformation Technology & Telecommunications Research Center

The University of Kansas

[email protected]

http://www.ittc.ku.edu/~jpgs/courses/hsnets

rev. 1.3

1 October 2008 KU EECS 881 – High-Speed Networking – Switching HSN-SR-2

© James P.G. SterbenzITTC

Switches and RoutersOutline

SR.1 OverviewSR.2 Fast packet switchesSR.3 Switch fabric architectureSR.4 Fast datagram switchesSR.5 Programmable, active, & higher layer processing



Switches and RoutersOutline

SR.1. Switch overviewSR.2. Fast packet switchesSR.3. Switch fabrics

SR.4. Fast datagram switchesSR.5. Programmable, active,

and higher layer processing

network

application

session

transport

network

link

end system

networklink

node

network

link

nodenetwork

link

node

application

session

transport

network

link

end system



Network Node Principle S-II

Network nodes must support high-bandwidth low-latency, end-to-end flows, as well as their aggregation. High-speed network nodes should provide a scalable number or high-bandwidth, low delay interconnections.

Ideal NetworkNetwork Node Principle

networkCPU

M app

end system

CPU

M app

end systemD = 0

R = ∞



Switches and RoutersSR.1 Overview

SR.1 OverviewSR.1.1 Switch functionsSR.1.2 Traditional store-and-forward routersSR.1.3 LAN bridges and switchesSR.1.4 Ideal switch architecture

SR.2 Fast packet switchesSR.3 Switch fabric architectureSR.4 Fast datagram switchesSR.5 Programmable, active, & higher layer processing



Switches and RoutersSR.1.1 Switch Functions





Network LayerService and Interfaces

• Network layer 3 is above link layer 2– addressing : network layer identifier for end systems (hosts)– forwarding : transfers packets hop-by-hop

• using link layer services• network layer responsible for determining which next hop

– routing : determination of path to forward packets– signalling : messages to control network layer behaviour– traffic management : management of traffic and congestion

• Network layer service to transport layer (L4)– deliver TPDUs to destination transport entity



Network LayerForwarding vs. Routing

• Forwarding transfers packets at each hop– each switch (router) makes decision on which link to send– forwarding table (generally) used to make decision– forwarding is per packet decision

[analogy: determining which exits to take on a drive ]

• Routing determines the path to take– routing algorithm independent of forwarding– forwarding table entries populated by routing– routing is (generally) not done per packet

[analogy: planning trip from source to destination ]

Forwarding and routing are very different



Network LayerService and Interfaces

• Network layer packet may encapsulates link layer frame

transport layer

link layer

network layer

transport layer

link layer

network layer

TPDU TPDU

TPDUH TPDUH



Network Layer ServiceService Models: Best Effort

• Best effort– network attempts to deliver most packets most of the time– network may attempt to be fair among users– this is the Internet service model– contrast with best-effort applications

• Differentiated service• Guaranteed service



Network Layer ServiceService Models: Differentiated Service

• Best effort• Differentiated service

– some users or traffic types receive preferential treatment– may provide statistical targets for service performance– this model has been proposed as DiffServ for the Internet

• Guaranteed service



Network Layer ServiceService Models: Guaranteed Service

• Best effort• Differentiated Service• Guaranteed service

– some (perhaps statistical) guarantees on service• delivery (reliability)• performance (delay, bandwidth, jitter, etc)

– this model is provided by the PSTN and ATM networks– this model has been proposed by IntServ for the Internet



SwitchesFunctions: Overview

• Routing / signalling– per flow or longer

• Transfer control– per packet control

• Data manipulation– per byte or packet

routing and signalling

transfer control

routing algorithm

topology link state

traffic management

signalling

input processing switch fabric

output processing

management

data manipulation

link layer decapsulation

link layer framing

packet buffers

forwarding table

link scheduling

congestioncontrol

filter classify

fabric control



SwitchesFunctions: Routing and Signalling

• Routing / signalling– per flow or longer

• Management• Signalling• Topology database• Routing algorithm• Traffic

management


transfer control

routing algorithm

topology link state

traffic management

signalling


output processing

management

data manipulation


link layer framing

packet buffers

forwarding table

link scheduling

congestioncontrol

filter classify

fabric control



SwitchesFunctions: Transfer Control

• Transfer control– per packet control

• Input control– classification tables– forwarding tables

• Congestion control• Fabric control

– e.g. set crosspoints

• Output control– link scheduling


transfer control

routing algorithm

topology link state

traffic management

signalling


output processing

management

data manipulation


link layer framing

packet buffers

forwarding table

link scheduling

congestioncontrol

filter classify

fabric control



SwitchesFunctions: Data Manipulation

• Data manipulation– per byte or packet– performance critical

• Input processing– link layer– packet classification– output lookup

• Switch fabric• Packet buffers• Output processing

– packet scheduling– link layer


transfer control

routing algorithm

topology link state

traffic management

signalling


output processing

management

data manipulation


link layer framing

packet buffers

forwarding table

link scheduling

congestioncontrol

filter classify

fabric control



Switches and RoutersSR.1.2 Store-and-Forward Routers





Store-and-Forward RoutersSecond Generation

• Second generation (1980s)– network interfaces (NI)

• share bus

– general purpose CPU

CPU M

network

w

NI

buffers

NI

link link

1




• Second generation (1980s)– delays

• store-and-forward• contention for CPU• non-trivial header processing

CPU M

network

w

NI

buffers

NI

link link

2






– buffering• in general purpose memory• contention for memory

CPU M

network

w

NI

buffers

NI

link link

3






– buffering• in general purpose memory• contention for memory

– shared bus interconnect• packets traverse bus twice• severely limits # of ports• DMA transfers help

CPU M

network

w

NI

buffers

NI

link link

4



Store-and-Forward RoutersThird Generation

• Third generation (1990s)– NI (network interface)

• NP: embedded controller– e.g. i960

• packet processing• packet buffers

CPU M

w

NI

buffers

NP

NI

buffers

NP

network

L2 L2

L3L3

1



Store-and-Forward RoutersThird Generation

• Third generation (1990s)– NI (network interface)

• NP: embedded controller– e.g. i960

• packet processing• packet buffers

– third party bus transfer• bus is switch fabric• single transfer per packet

– still significant bottleneck

CPU M

w

NI

buffers

NP

NI

buffers

NP

network

L2 L2

L3L3

2



Switches and RoutersSR.1.3 LAN Bridges and Switches

SR.1 Switch overviewSR.1.1 Switch functionsSR.1.2 Traditional store-and-forward routersSR.1.3 LAN bridges and switchesSR.1.4 Ideal switch architecture




Switches and RoutersLAN Switching

• Recall LAN interconnection technology progression:– single segment– learning bridge– hub– switch



LAN SwitchingExact Match Lookup

• Most LANs use large flat address space– IEEE 802 48-bit MAC address

Challenges in switching?



LAN SwitchingExact Match Lookup

• Most LANs use large flat address space– IEEE 802 48-bit MAC address

• No structured aggregation of addresses– 248 ≈ 2.8×1015 entry address space– requires exact match lookup

• Limits size of flat-address networks



LAN SwitchingExact Match Lookup Techniques

• Binary search– O (log n) time steps– requires sorted entries

• Hashing– O (1) time steps best case– O (n) time steps worst case due to hash collisions

• Perfect hashing– upper bound on worst case lookup time– hash function modified as address entries added to table



Switches and RoutersSR.1.4 Ideal Switch Architecture

SR.1 Switch overviewSR.1.1 Switch functionsSR.1.2 Traditional store-and-forward routersSR.1.3 LAN bridges and switchesSR.1.4 Ideal switch architecture




Ideal Switch ArchitectureBandwidth, Latency, Ports

• Infinite bandwidth• Zero latency• Unlimited

number of ports

Store-and-Forward & Queueing Delay Minimisation S-II.3

Store-and-forward delays should be avoided, and per packet queueing should be minimised. In the ideal case, nodes should pipeline and cut through packet with zero per packet delays.

n = ∞

R = ∞ D = 0



Switches and RoutersSR.2 Fast Packet Switches

SR.1 Switches and routersSR.2 Fast packet switches

SR.2.1 Input and label processingSR.2.2 Packet structureSR.2.3 Functional partitioning

SR.4 Switch fabric architectureSR.5 Fast datagram switchesSR.6 Programmable, active, & higher layer processing



Fast Packet SwitchMotivation

• Connection state– simple per packet

processing

• Switch fabric– eliminate blocking– no store-and-forward

Fast Packet Switch Critical Path Principle S-1bc

Simplify and optimise per byte and per packet data manipulation and transfer control functions for implementation in a hardware critical path. State maintained per connection streamlines per packet processing.

input processing output processing


switch fabric

link scheduling

link

link

link

link

label swap

CID table

switch fabric control



Fast Packet SwitchArchitecture

• Routing & signalling– populates forwarding

• connection id table

• Input processing– decodes headers– connection id lookup

• determines output

• Switch fabric– control sets paths to interconnects inputs to outputs

• Output processing– buffer for contention and schedule for transmission



switch fabric

link scheduling

link

link

link

link

label swap

CID table




Fast Packet SwitchArchitecture

• Input processing– connection id table with label swapping– switch fabric– other input functions Lecture IO

• Switch fabric• Output processing Lecture IO• Routing and signalling EECS780 lecture NR



Switches and RoutersSR.2.1 Input and Label Processing






Fast Packet SwitchLabel Swapping

• Connection id is index into table

cin pout cout cstate

=

payload payload cin

1




• Connection id is index into table• Table entry gives egress link and next hop id


=

payload cout payload cin

2




• Connection id is index into table• Table entry gives egress link and next hop id

– port may be prepended for self-routing fabricsexamples: ATM, MPLS


=

pout payload cout payload cin

3



Fast Packet SwitchConnection State Establishment

• SETUP message arrives at switch

1

SETUP (as, ad, r)




• SETUP message arrives at switch– connection routing

• resolve dest. address ad to output port pout from topo. database

2

pout

SETUP (as, ad, r)






– check for available resources r in switch and egress link• if available temporarily reserve

3

pout

SETUP (as, ad, r)







– choose unused connection id cout

• temporarily put output port pout in connection forwarding table

4

c:p









– pass SETUP to next hop• save SETUP association (as, ad, id) to match with CONNECT

5

c:p

SETUP









– pass SETUP to next hop• save SETUP association (as, ad, id) to match with CONNECT

– release all state if:• corresponding RELEASE message received• corresponding CONNECT not received within timeout interval 6

c:p

SETUP




• SETUP message arrives at switch– connection routing– check for and temporarily reserve resources– choose and insert unused connection id– pass SETUP to next hop

• CONNECT message returned to switch

7

c:p

CONNECT





• CONNECT message returned to switch– commit switch and egress link resources

8

c:p

CONNECT





• CONNECT message returned to switch– commit switch and egress link resources– pass CONNECT message back through ingress link

9

c:pCONNECT



Fast Packet SwitchLabel Swapping Example

p0

3 1

5 1

p3

p2

p1

3 3

1 4

1 6

0

pout cout

7 1

1




p0

3 1

5 1

p3

p2

p1

3 3

1 4

1 6

0

pout cout

7 1

2




p0

3 1

3

5 1

p3

p2

p1

3 3

1 4

1 6

0

pout cout

7 1

3




p0

7 2

2

3 1

3

5 1

p3

p2

p1

3 3

1

21

4 0

1 6

3

25

0

0

pout cout

7 1

0 2

4




p2

p0

7 2

2

3 1

3

5 1

p3

p2

p1

3 3

1

21

4 0

1 6

3

25

0

0

pout cout

7 1

0 2

5




p2

p0

7 2

2

3 1

37

5 1

p3

p2

p1

3 3

1

21

4 0

1 6

3

25

0

0

pout cout

7 1

0 2

6




p2

p0

3

7 2

2

3 1

5 3

37

5 1

p3

p2

p1

3 3

1

233

1

4 0

0

1 6

3

2

25

0

0 0

pout cout

7 21

0 2

3

7




p3 p2

p0

3

7 2

2

3 1

5 3

37

5 1

p3

p2

p1

3 3

1

233

1

4 0

0

1 6

3

2

25

0

0 0

pout cout

7 21

0 2

3

8




p3 p2

p0

3

7 2

2

3 1

5 3

37

5

5 1

p3

p2

p1

3 3

1

233

1

4 0

0

1 6

3

2

25

0

0 0

pout cout

7 21

0 2

3

9



Fast Packet SwitchConnectionless vs. Connection Tradeoff

• Connection-oriented fast packet switching– requires round trip connection setup latency– achieved higher data rate due to simple label swap

• IP lookup was a bottleneck in 1980s

Connectionless vs. Connection Tradeoff S-5A

The latency of connection setup must be traded against the increase in packet processing rate and resultant bandwidth increase achievable due to the less complex label swapping.



Switches and RoutersSR.2.2 Packet Structure






Packet StructureSize and Variability

• PDU size and structure are critical to performance

Packet Size and Variability Tradeoff S-8A

Packet size is a balance of a number of parameters that affect performance. Trade the statistical multiplexing and fine-grained control benefits of small packets against the efficiency of large packets. Trade the benefits to switch design of fixed cell sizeagainst the overhead of SAR and efficiency of variable packet size. Multiple discrete packet sizes increase flexibility at the cost of additional switch complexity. Hop-by-hop SAR localizes packet size optimizations at the cost of additional per hop delay and complexity.



Packet Size and StructureVariability

• Fixed vs. variable size packetstradeoffs?



Packet Size and StructureVariability

• Fixed size (cells)+ easier to design switches– difficult to predetermine the best size

• Variable size– more difficult to design switches+ no need for agreement on size+ less need for fragmentation/segmentation

• Discrete sizes: advantages of both fixed and variable• integral multiples, e.g. 64B, 128B, 192B…• power-of-2 scaling with data rate

e.g. 128B @ OC-3, 256B @ OC-12, 512B @ OC-48



Packet Size and StructureSize

• Small vs. large packetstradeoffs?



Packet Size and StructureSize

• Small packets+ efficient statistical multiplexing– high header/payload overhead– short interarrival time challenge per packet processing

• note: this is one major reason ATM failed

• Large packets+ significantly easier per packet processing– less efficient statistical multiplexing– larger queueing delays+ efficient transport of large data blocks– inefficient transport of signalling and control messages

e.g. TCP ACKs



Packet Size and StructureGranularity

• Important to match granularity to packet processingwhy?



Packet Size and StructureGranularity

• Important to match granularity to packet processing+ byte / octet (8 bits)

• control fields should align to 8-bit boundaries

+ word (typically 32 bits)• most end-system processing at word granularity• payload should align to 32-bit boundaries

+ end system data unit• system buffers and memory structures• power-of-2 size will likely be integral fraction

+ commodity memory components• power-of-2 size

– note: ATM cell was none of these



Packet Size and StructurePacket Format

• Header– fields that determine

packet processing

• Payload– TPDU transport protocol data unit

• Trailer– fields that are dependent on

packet processing• e.g. checksum to allow cut-through

TPDU

check

header

trailer

payload

payload lengthcheck

typeconnection id

version

QoSauthentication



Packet Size and StructurePacket Format: Header

• Headerfields that determinepacket processing– protocol version– packet type: control, data, etc.– connection id or protocol demux– QoS and authentication if needed– header check

• processing even if data corrupted

• Payload• Trailer

TPDU

check

header

trailer

payload

payload lengthcheck

typeconnection id

version

QoSauthentication



Packet Size and StructurePacket Format: Payload

• Header• Payload

– TPDU transport protocol data unit

• Trailer

TPDU

check

header

trailer

payload

payload lengthcheck

typeconnection id

version

QoSauthentication



Packet Size and StructurePacket Format: Trailer

• Header• Payload• Trailer

fields that are dependent onpacket processing– checksum to allow cut-through

• compute and compare TPDU

check

header

trailer

payload

payload lengthcheck

typeconnection id

version

QoSauthentication



Packet Size and StructureControl Fields

• Control field structure and encoding is critical– simple encoding (bit vectors vs. code points)– byte/octet granularity and alignment– field length

• fixed when possible• variable length prepended with length (skip vs. hunt)

Packet Control Field Structure S-8B

Optimise packet header and trailer fields for efficient processing. Fields should be simply encoded, byte aligned, and fixed length where possible. Variable-length fields should be prepended with their length.



Packet StructureExample5.4 ATM Cells

• ATM cell format– fast packet switching– fine-grained statistical multiplexing

• Size determined by ITU committee compromise– 48B = avg(32, 64)

• 64 from US = min of proposals for data (and voice)• 32 from European PTTs to avoid voice echo cancellers

• Problems:– header tiny to keep overhead low; no room for seq #– nothing a power of 2– 48B + 5B = 53B; not even a multiple of 8



Packet StructureExample5.4 ATM AAL-5 Cells

PTI 0X1

VPI

VCI CLP

HEC

CRC-32 length CPI

CPCS-UU

SAR-SDU ≤ 40B

last cell – SDU type 1 other cells – SDU type 0

PTI 0X0

VPI

VCI CLP

HEC

SAR-SDU = 48B

header5B

payload

trailer

48B

40B

8B

• AAL 3/4 for data– 4B AAL header

• useless seq#

– 44B payload• not div 8

• AAL 5– no header– trailer last frag– forced on ITU



Packet StructureExample5.4 ATM Hierarchical Switching

• ATM split connection id– permits 2-level switching hierarchy

• VPI (virtual path identifier): high order bits– switched by core and edge switches– core switches have smaller VP tables– switch large bundles of VCs in each VP with single lookup

• VCI (virtual channel identifier): low order bits– switched by local and edge switches– local and edge switches handle small subset of overall nodes




• VC LAN switch– switches small number of VCs

VC

VC





• VPVC edge switch– bundles large numbers of VCs into VPs and switches

VPVC

VCVC

VC





• VPVC edge switch– bundles large numbers of VCs into VPs and switches

• VP core switch– switches VPs; far fewer than VPVCs

VP

VPVC

VCVC

VCVP



Packet Size and StructureSegmentation and Reassembly

• End-to-end+ more efficient

in the network– requires global

agreement on packet size• original assumption for ATM

• cell size standardised• SAR difficult in 1980’s

SAR SAR

SAR SAR



Packet Size and StructureSegmentation and Reassembly

• End-to-end+ more efficient

in the network– requires global

agreement on packet size

• Hop-by-hop– significant overhead

per switch+ each switch can use cell size

optimised to its architecture• used by modern

cell-based IP routers

SAR SAR

SAR

SAR

SAR SAR

SAR

SAR



Packet StructureExample5.5 MPLS Shim

network layer packet

stacked labels single label

S=1

label

COS TTL

link layer header

link layer header

label4B

shim

labelstack

link layer trailer link layer trailer

network layer packet

S=1

label

COS TTL

S=0

label

COS TTL

S=0

label

COS TTL

• MPLS multiprotocol label switching– fast packet switching for IP

• Add label shim– switches swap label– stacked labels

• allows net hierarchy(ala VP/VC)



Traffic ManagementConnection-Oriented Fast Packet Switching

• Traffic management– required to protect high-performance flow characteristics– functions in critical path must be implemented at line speed

• simple hardware required for third generation (1990s)

Switch Traffic Management S-II.2

In a resource-constrained environment, switches must support admission control with resource reservations to provide guaranteed service traffic classes and policing to prevent othertraffic form interfering.



Traffic ManagementOverengineering vs. Optimality

• Traffic management can be very complex• Overengineering can dramatically simplify

Overengineering vs. Optimality S-2B

Optimal traffic management policies use processing and memory, which also adds latency to connection establishment; trade these against the bandwidth wasted by overengineering and overprovisioning the network.



Switches and RoutersSR.2.3 Functional Partitioning

SR.1 OverviewSR.2 Fast packet switches





Switch Functional PartitioningDesign and Technology Alternatives

• Hardware vs. Software– control CPU vs. embedded controller vs. network processor

• Custom VLSI vs. ASIC vs. FPGA• Technology

– DRAM vs. SRAM vs. TCAM– CMOS vs. GaAs

• Electronic vs. optical

Functional Partitioning and Assignment Principle S-1C

Carefully determine what switch functionality is to be implemented in scarce or expensive technology



Switch Functional PartitioningElectronic vs. Optical

• Optical switches– avoid O/E/O conversion (optical/electronic/optical)

• Data path– optical switch elements in photonic domain

• Control pathproblem?






• Control path: photonic processing infeasible– not possible to process header optical domain– conventional buffering not possible in optical domain

solution?






• Control path: photonic processing infeasible– O/E conversion on header only

• header processed by conventional digital electronics

– optical delay lines (long tiny fiber loops)• delay photonic payload long enough for:

– header processing– relatively slow optical switch element control




• Photonic processing infeasible

• Split header O/E/O– electronic

control– optical packet

delay

input processing


optical switch fabric

electronic switch fabric control

input processor

o/e

forward table

e/o

input processor

o/e

forward table

e/o



Switches and RoutersSR.3 Switch Fabric Architecture

SR.1 Switches and routersSR.2 Fast packet switchesSR.3 Switch fabric architecture

SR.3.1 Queueing analysis backgroundSR.3.2 BufferingSR.3.3 Single-stage elementsSR.3.4 Multistage switchesSR.3.5 Multicast support

SR.4 Fast datagram switchesSR.5 Programmable, active, & higher layer processing



Fast Packet SwitchSwitch Fabric Architecture

• Connection state– simple per packet

processing

• Switch fabric– eliminate blocking– no store-and-forward



switch fabric

link scheduling

link

link

link

link

label swap

CID table




Switches and RoutersSR.3.1 Queueing Analysis Background

SR.1 OverviewSR.2 Fast packet switchesSR.3 Switch fabric architecture





Queueing Analysis BackgroundBasic Model

• Packets arrive in a queue at rate λ [1/s]• Packets are served at a rate μ [1/s]

– service time of s [s]

• System utilisation is ρ [erlangs] ([1] = [s/s])– expressed as number in (0…1) or %

λ arrival rateρ utilisation

queue server μ



Queueing Analysis BackgroundLittle’s Theorem

• N = λT• Variables

N – average number of customers (packets) in systemλ – arrival rate [1/s]T – average time spent in system [s]

• Holds for all distributions• Intuition

– as service time increases, so do number in system– as arrival rate increases, so do number in system



Queueing Analysis BackgroundDistributions

• Arrival and service rates determine performance– average rates matter, but…

• Distribution of rates are critical– uniform: all interarrival or service times equal

• simple but unrealistic for most systems

– exponential or Poisson (independent: memoryless)• Pr[k arrivals in interval T] =

– bursty: arrivals clumped into groups– self-similar: distribution similar at different granularities

• evidence of self-similar traffic in Internet• challenges benefits of statistical multiplexing

( )!

kTT

ek

λλ −



Queueing Analysis BackgroundNotation

• A/S/N– A and S: distribution of arrivals and service times

G – general independentM – exponential (Poisson)

• memoryless: each event independent of the previous

D – deterministic or uniform– N: number of servers

• Examples– M/M/1: exponential arrival, exponential service, single server



M/M/1 Queueing AnalysisBasic Results

• Utilization ρ = λ / μ– arrival rate / service rate

• Average time in queue– note what happens as

ρ → 1

• Average time in system

/1

W ρ μρ

=−

1/1

T μρ

=−

ρ 1.0

W



M/M/1 Queueing AnalysisDiscussion

• M/M/1 equations very simple– so they are frequently used in closed-form analysis– reflects independent arrivals

• Web transactions (HTTP gets)• voice call SETUPs

– does not accurately represent traffic in network• bursty traffic (e.g. P2P file sharing, TCP segment bursts)• correlated traffic

• G/G/1 equations very complex!– requires integration of a function– difficult to analyse networks of generalised queues



Analysis TechniquesAnalytical

• Analytical queueing analysis– mathematical analysis of system– useful for small simple system– exact behaviour of complex system difficult or impossible

• not possible to precisely analyse large network of real traffic

– critical problem:• simplifying assumptions must be made for complex systems• usefulness of results depends on these assumptions!

• Simulation• Emulation• Measurement



Analysis TechniquesSimulation

• Queueing analysis• Simulation (e.g. ns-3)

– build software simulation model of system• generally more complex models possible than analytical

– critical problem:• real system must be abstracted to software model• abstractions usually contain simplifying assumptions• usefulness of results depends on abstraction and model!

• Emulation• Measurement



Analysis TechniquesEmulation

• Queueing analysis• Simulation• Emulation

– hardware component designed to behave like real system• e.g. link emulator

– allows control of behaviour not possible in real system– critical problem

• emulator usually simplification of real system• usefulness of results depends on simplification!

– emulator frequently a component of simulation or testbed

• Measurement



Analysis TechniquesMeasurement

• Queueing analysis• Simulation• Emulation• Measurement

– measurement of actual system• may be a testbed – usually a small replica of real network

– critical problem:• testbed may not reflect scale of real network• access to measurement data difficult

– due to scale of real network– due to administrative concerns, including privacy



Analysis TechniquesVerification

• Combination of techniques– each technique has strengths and weaknesses– should be combined as necessary

• Verification of models– compare results of two techniques to verify model– example:

• compare queueing and simulation model of simple system• gives confidence of simulation model for more complex system



Analysis TechniquesDesign Cycle

• Use each technique as appropriate in design cycle• Design cycle

– mathematical analysis and/or simulation• iterate on design parameters until desired behaviour• gives insight on how to build prototype system

– construct prototype and measure in testbed• analysis in small scale• iterate design; modify simulation model if necessary

– build real system on large scale• measure to confirm design and modify future deployments



Switches and RoutersSR.3.2 Buffering






Switch Fabric ArchitectureOverview

• Switch fabric– core of switch– connects arbitrary

inputs to outputs

• Goals– eliminate blocking– no store-and-forward



switch fabric

link scheduling

link

link

link

link

label swap

CID table




Switch Fabric ArchitectureBlocking

• Blocking characteristics (among different outputs)– strictly nonblocking: under all conditions– wide-sense nonblocking: if particular algorithm is used– rearrangeably nonblocking: if existing paths are rearranged– virtually nonblocking: with extremely low probability

Nonblocking Switch Fabric Principle S-II.4f

A nonblocking switch fabric is the core or a high performance switch. Avoid blocking by space-division parallelism, internal speedup, and internal pipelined buffering with cut-through. Strict and wide-sense nonblocking avoids the complexity and delay of path rearrangement.



Switch Fabric ArchitectureContention and Buffering

• Contention (burst collisions) in a non-blocking fabric– occurs when traffic destined for same output– requires buffering even for well-behaved traffic

collisions

in1

in2

out delayed




• Unbuffered fabric

• Internal buffers




• Input queueingproblem?




• Input queueing– suffers from

head-of-line blocking

0






1






2






3






4






5






6






• Output queueingproblem?






• Output queueing– requires either:

• internal speedup• internal expansion



Switch Fabric ArchitectureHead-of-Line Blocking

Head-of-Line Blocking Avoidance Principle S-II.4q

Avoid head-of-line blocking. Output queueing requires internal speedup, expansion, or buffering. Virtual output queueing requires additional queues or queueing complexity. The two techniques must be traded against one another, and can be used in combination.



Switch Fabric ArchitectureVirtual Output Queueing

• Virtual output queueing– parallel buffers– non-FIFO buffers



Switches and RoutersSR.3.3 Single-Stage Elements

SR.1 OverviewSR.2 Fast packet switchesSR.3 Switch fabric architecture





Switch Fabric ArchitectureSingle Stage: Bus as a Switch

• Simple design shared medium bus– point of contention: only one input active at a time

• 2nd/3rd generation routers

– suitable for small switches

• Multicast– inherent broadcast

i0 i1 i2 i3 i4 i5 i6 i7

o0 o1 o2 o3 o4 o5 o6 o7

w



Switch Fabric ArchitectureSingle Stage: Shared Memory Switch

• Simple design– packets written by input– packets read by output

• Shared memory– point of contention– speedup necessary

• but access times not scaling with Moore’s

• Multicast– multiple writes or– multicast output demux

i0

i1

i2

i3

i4

i5

i6

i7

o0 o1 o2 o3 o4 o5 o6 o7

output demultiplex

i nput

mul t i pl ex

shared memory



Switch Fabric ArchitectureSingle Stage: Basic 2×2 Switch Element

• States– point-to-point

• straight• cross

– multicast

control headerdecode

header decode

delay

cut-through delay

cut-through

i0

i1 o1

o0

packet buffer

packet buffer

output multiplexor

0

straight cross






– multicast


header decode

delay

cut-through delay

cut-through

i0

i1 o1

o0

packet buffer

packet buffer

output multiplexor

straight cross

1






– multicast


header decode

delay

cut-through delay

cut-through

i0

i1 o1

o0

packet buffer

packet buffer

output multiplexor

straight cross

2






– multicast


header decode

delay

cut-through delay

cut-through

i0

i1 o1

o0

packet buffer

packet buffer

output multiplexor

3

straight cross






– multicast


header decode

delay

cut-through delay

cut-through

i0

i1 o1

o0

packet buffer

packet buffer

output multiplexor

straight cross

1






– multicast


header decode

delay

cut-through delay

cut-through

i0

i1 o1

o0

packet buffer

packet buffer

output multiplexor

straight cross

2






– multicast


header decode

delay

cut-through delay

cut-through

i0

i1 o1

o0

packet buffer

packet buffer

output multiplexor

straight cross

3






– multicast• Types

– internally buffered or unbuffered

– self routing orexternally controlled


header decode

delay

cut-through delay

cut-through

i0

i1 o1

o0

packet buffer

packet buffer

output multiplexor

straight cross



Switch Fabric ArchitectureSingle Stage: Crossbar Switch

• Crosspoint switch element– electronic

– optical MEMS• rotating mirror

column

ii

oj

electronic optical MEMS

ii

oj

column

cross turn



Switch Fabric ArchitectureSingle Stage: Crossbar Switch

• Crossbar fabric– square array of

crosspoint elements– O (n 2) growth

complexity– reasonable for

moderate n

i0

i1

i2

i3

i4

i5

i6

i7

o0 o1 o2 o3 o4 o5 o6 o7



Crossbar SwitchPath Selection

• Crossbar fabric– simple path routing

• element (o,i) turns

i0

i1

i2

i3

i4

i5

i6

i7

o0 o1 o2 o3 o4 o5 o6 o7 0





• element (o,i) turns• i3 → o4

i0

i1

i2

i3

i4

i5

i6

i7

o0 o1 o2 o3 o4 o5 o6 o7 1






i0

i1

i2

i3

i4

i5

i6

i7

o0 o1 o2 o3 o4 o5 o6 o7 2






i0

i1

i2

i3

i4

i5

i6

i7

o0 o1 o2 o3 o4 o5 o6 o7 3



Crossbar SwitchStrictly Nonblocking



– strictly nonblocking• ij→on noblock ik→om∀j,k,n,m: i ≠ j, n ≠ m

• i1 → o1

i0

i1

i2

i3

i4

i5

i6

i7

o0 o1 o2 o3 o4 o5 o6 o7 1







• i1 → o1

i0

i1

i2

i3

i4

i5

i6

i7

o0 o1 o2 o3 o4 o5 o6 o7 2







• i1 → o1

i0

i1

i2

i3

i4

i5

i6

i7

o0 o1 o2 o3 o4 o5 o6 o7 3



Switches and RoutersSR.3.4 Multistage Switches






Switch FabricsMultistage Switches

• Large switches built from single stage elements– 2×2 elements or n ×n crossbars– O (n log n) growth complexity

Switch Scalability S-III.4

The construction of switches with a large port count requires scalable switch fabrics. Exploit regular structures for implementation in VLSI or optics as the basis for recursively constructed fabrics with logarithmic growth complexity.



Multistage Switch FabricsDelta Fabric Construction and Scalability

• Delta fabric– recursive

construction– double fabric

vertically– add shuffle

stage at input

0

i0

i2

i4

i6

i8

i10

i12

i14

i1

i3

i5

i7

i9

i11

i13

i15

o0

o2

o4

o6

o8

o10

o12

o14

o1

o3

o5

o7

o9

o11

o13

o15

s3 s2 s1 s0




• Delta fabric– O (n log n )

n /2 rows log2 n stagesn = 22/2 log2 2 = 1

i0 i1

o0 o1

s0

1






i0

i2

i1

i3

o0

o2

o1

o3

s1 s0

2






i0

i2

i4

i6

i1

i3

i5

i7

o0

o2

o4

o6

o1

o3

o5

o7

s2 s1 s0

3





n /2 rows log2 n stagesn = 1616/2 log216=32

i0

i2

i4

i6

i8

i10

i12

i14

i1

i3

i5

i7

i9

i11

i13

i15

o0

o2

o4

o6

o8

o10

o12

o14

o1

o3

o5

o7

o9

o11

o13

o15

s3 s2 s1 s0

4



Multistage Switch FabricsDelta Fabric Construction Self-Routing

• Delta fabric– self-routing– ith bit of pout

used to make routing decision in ith stage

i0

i2

i4

i6

i8

i10

i12

i14

i1

i3

i5

i7

i9

i11

i13

i15

o0

o2

o4

o6

o8

o10

o12

o14

o1

o3

o5

o7

o9

o11

o13

o15

s3 s2 s1 s0

0



i0

i2

i4

i6

i8

i10

i12

i14

i1

i3

i5

i7

i9

i11

i13

i15

o0

o2

o4

o6

o8

o10

o12

o14

o1

o3

o5

o7

o9

o11

o13

o15

s3 s2 s1 s0




– i2 → o10 1010

1



i0

i2

i4

i6

i8

i10

i12

i14

i1

i3

i5

i7

i9

i11

i13

i15

o0

o2

o4

o6

o8

o10

o12

o14

o1

o3

o5

o7

o9

o11

o13

o15

s3 s2 s1 s0




– i2 → o10

1010

1010

2



i0

i2

i4

i6

i8

i10

i12

i14

i1

i3

i5

i7

i9

i11

i13

i15

o0

o2

o4

o6

o8

o10

o12

o14

o1

o3

o5

o7

o9

o11

o13

o15

s3 s2 s1 s0




– i2 → o10 1010

31010



i0

i2

i4

i6

i8

i10

i12

i14

i1

i3

i5

i7

i9

i11

i13

i15

o0

o2

o4

o6

o8

o10

o12

o14

o1

o3

o5

o7

o9

o11

o13

o15

s3 s2 s1 s0




– i2 → o10 1010

41010 1010



i0

i2

i4

i6

i8

i10

i12

i14

i1

i3

i5

i7

i9

i11

i13

i15

o0

o2

o4

o6

o8

o10

o12

o14

o1

o3

o5

o7

o9

o11

o13

o15

s3 s2 s1 s0




– i2 → o10 1010

51010 1010



i0

i2

i4

i6

i8

i10

i12

i14

i1

i3

i5

i7

i9

i11

i13

i15

o0

o2

o4

o6

o8

o10

o12

o14

o1

o3

o5

o7

o9

o11

o13

o15

s3 s2 s1 s0




– i2 → o10 1010

61010 1010 1010



i0

i2

i4

i6

i8

i10

i12

i14

i1

i3

i5

i7

i9

i11

i13

i15

o0

o2

o4

o6

o8

o10

o12

o14

o1

o3

o5

o7

o9

o11

o13

o15

s3 s2 s1 s0




– i2 → o10 1010

71010 1010 1010



i0

i2

i4

i6

i8

i10

i12

i14

i1

i3

i5

i7

i9

i11

i13

i15

o0

o2

o4

o6

o8

o10

o12

o14

o1

o3

o5

o7

o9

o11

o13

o15

s3 s2 s1 s0




– i2 → o10 1010

81010 1010 1010 1010



i0

i2

i4

i6

i8

i10

i12

i14

i1

i3

i5

i7

i9

i11

i13

i15

o0

o2

o4

o6

o8

o10

o12

o14

o1

o3

o5

o7

o9

o11

o13

o15

s3 s2 s1 s0




– i2 → o10 1010

91010 1010 1010 1010



i0

i2

i4

i6

i8

i10

i12

i14

i1

i3

i5

i7

i9

i11

i13

i15

o0

o2

o4

o6

o8

o10

o12

o14

o1

o3

o5

o7

o9

o11

o13

o15

s3 s2 s1 s0




– i2 → o10

1010 1010 1010 1010

1010

10



i0

i2

i4

i6

i8

i10

i12

i14

i1

i3

i5

i7

i9

i11

i13

i15

o0

o2

o4

o6

o8

o10

o12

o14

o1

o3

o5

o7

o9

o11

o13

o15

s3 s2 s1 s0




– i2 → o10

– i13 → o10

1010

1010

11



i0

i2

i4

i6

i8

i10

i12

i14

i1

i3

i5

i7

i9

i11

i13

i15

o0

o2

o4

o6

o8

o10

o12

o14

o1

o3

o5

o7

o9

o11

o13

o15

s3 s2 s1 s0




– i2 → o10

– i13 → o10

1010

1010

12



i0

i2

i4

i6

i8

i10

i12

i14

i1

i3

i5

i7

i9

i11

i13

i15

o0

o2

o4

o6

o8

o10

o12

o14

o1

o3

o5

o7

o9

o11

o13

o15

s3 s2 s1 s0




– i2 → o10

– i13 → o10

1010

1010

131010



i0

i2

i4

i6

i8

i10

i12

i14

i1

i3

i5

i7

i9

i11

i13

i15

o0

o2

o4

o6

o8

o10

o12

o14

o1

o3

o5

o7

o9

o11

o13

o15

s3 s2 s1 s0




– i2 → o10

– i13 → o10

1010

1010

141010



i0

i2

i4

i6

i8

i10

i12

i14

i1

i3

i5

i7

i9

i11

i13

i15

o0

o2

o4

o6

o8

o10

o12

o14

o1

o3

o5

o7

o9

o11

o13

o15

s3 s2 s1 s0




– i2 → o10

– i13 → o10

1010

1010

151010 1010



i0

i2

i4

i6

i8

i10

i12

i14

i1

i3

i5

i7

i9

i11

i13

i15

o0

o2

o4

o6

o8

o10

o12

o14

o1

o3

o5

o7

o9

o11

o13

o15

s3 s2 s1 s0




– i2 → o10

– i13 → o10

1010

1010

161010 1010



i0

i2

i4

i6

i8

i10

i12

i14

i1

i3

i5

i7

i9

i11

i13

i15

o0

o2

o4

o6

o8

o10

o12

o14

o1

o3

o5

o7

o9

o11

o13

o15

s3 s2 s1 s0




– i2 → o10

– i13 → o10

1010

1010

171010 1010 1010



i0

i2

i4

i6

i8

i10

i12

i14

i1

i3

i5

i7

i9

i11

i13

i15

o0

o2

o4

o6

o8

o10

o12

o14

o1

o3

o5

o7

o9

o11

o13

o15

s3 s2 s1 s0




– i2 → o10

– i13 → o10

1010

1010

181010 1010 1010



i0

i2

i4

i6

i8

i10

i12

i14

i1

i3

i5

i7

i9

i11

i13

i15

o0

o2

o4

o6

o8

o10

o12

o14

o1

o3

o5

o7

o9

o11

o13

o15

s3 s2 s1 s0




– i2 → o10

– i13 → o10

1010 1010 1010 1010

1010

19



Multistage Switch FabricsClos Fabric Overview

• Clos fabric– n×n fabric is interconnection of 3 crossbars stages– input stage of n/d elements:

d×r crossbars each with d :r expansion– middle stage of r elements: n/d×n/d square crossbars– output stage of n/d elements:

r×d crossbars each with r :d concentration– perfect shuffle interconnection between stages:

i th output of j th crossbar → j th input of i th crossbar



Multistage Switch FabricsClos Fabric Architecture and Construction

0

d

n

rd×rd<r

0

n/d –1

r×dr>d

d

n

0

n/d –1

r–1

10

n/d×n/d

r × n/d




1




2




3




4




5




6




7




8




9




10




11




12




13




14




15



Multistage Switch FabricsClos Fabric Routing and Blocking

• Clos fabric path routing– for input from i th crossbar in first stage →

j th crossbar in last stage– choose any middle stage crossbar with (i, j) point available

• Blocking characteristics– blocking depends on expansion in middle stages r– strictly nonblocking for unicast iff r ≥ 2d –1– engineered to balance cost against blocking probability



Multistage Switch FabricsClos Fabric Routing

0




1




2




3




4



Multistage Switch FabricsClos Fabric Application

• Clos fabric– used in modern switch fabrics– e.g. Ciena optical switches, Juniper routers

• Engineering tradeoff optimisations– crossbar elements to VLSI switch complexity– partitioning: 1st and last stages can be on line-group cards

• permits switching among different rate interfaces



Multistage Switch FabricsExample5.C Ciena CoreDirector Optical Switch

• Ciena CoreDirector optical switch– carrier-grade switch (WAN/MAN service provider market)– note: used in the KU/KSU/UMKC/UNL GpENI project

• Backplane– 640 Gb/s aggregate capacity– center stage of Clos fabric

• Interface slots– 1st and 3rd stages of Clos fabric– SONET OC-3 – OC-192, OTN OUT-2, 1 – 10 GbEthernet



Switches and RoutersSR.3.5 Multicast Support






Switch Fabric ArchitectureNative Multicast

• Multicast support in network conserves bandwidthWhy?



Switch Fabric ArchitectureNative Multicast

• Multicast support in network conserves bandwidth• Multicast support in switches

– prevents multiple transmissions of a single multicast packet– reduces delay in subsequent packets

Switches Should Provide Native Multicast S-2C

Switches should provide native multicast support to conserve bandwidth and avoid latency of repeated transmission.



Crossbar Switch MulticastCrosspoint Element Duplication

• Crosspoint switch element– electronic

• multicast possible

column

ii

oj

electronic

cross turn duplicate



Crossbar Switch MulticastNative Multicast



– strictly nonblocking• i1 → o1

– multicast• i1 → {o1, o6 }

i0

i1

i2

i3

i4

i5

i6

i7

o0 o1 o2 o3 o4 o5 o6 o7 1








i0

i1

i2

i3

i4

i5

i6

i7

o0 o1 o2 o3 o4 o5 o6 o7 2








i0

i1

i2

i3

i4

i5

i6

i7

o0 o1 o2 o3 o4 o5 o6 o7 3








i0

i1

i2

i3

i4

i5

i6

i7

o0 o1 o2 o3 o4 o5 o6 o7 4




• Crossbar switch points enable native multicast– switch points duplicate packet flow

• electronic and some optical (but not MEMs mirrors)

problem?



Crossbar Switch MulticastNative Multicast Blocking


• electronic and some optical (but not MEMs mirrors)

– but fabric no longer nonblocking– sets of multicast output groups interfere with one another



Crossbar Switch MulticastNative Multicast Blocking


• electronic and some optical (but not MEMS mirrors)

– but fabric no longer nonblocking– sets of multicast output groups interfere with one another

• Input shouldn’t wait for free output set– very poor utilisation



Crossbar Switch MulticastOutput Arbitration

• Crossbar switchpoints enablenative multicast

• Output arbitrationneeded to resolveincompatible output sets– fanout splitting:

not all copies needxmit simultaneously

– at cost of implementation complexity

o1 o2 o3 o4 o5

1_3_5

_2345

1234_

_23_5

_2_4_

1 2 1 12

3

3 3 3

24

4

4

5 2

5

i1

i2

i3

i4

i5



Multistage Switch Multicast2×2 Switch Element Duplication




– buffered or unbuffered



header decode

delay

cut-through delay

cut-through

i0

i1 o1

o0

packet buffer

packet buffer

output multiplexor

straight cross duplicate

0










header decode

delay

cut-through delay

cut-through

i0

i1 o1

o0

packet buffer

packet buffer

output multiplexor


1










header decode

delay

cut-through delay

cut-through

i0

i1 o1

o0

packet buffer

packet buffer

output multiplexor


2










header decode

delay

cut-through delay

cut-through

i0

i1 o1

o0

packet buffer

packet buffer

output multiplexor


3



Multistage Switch MulticastNative Multicast Stages

• Multistage multicast– switch elements

duplicate late• 2×2: replicate

state• n×n internal

– alternative:recirculation

– multiple fabrics• copy stages• cid translation• routing stages

i0

i2

i4

i6

i8

i10

i12

i14

i1

i3

i5

i7

i9

i11

i13

i15

o0

o2

o4

o6

o8

o10

o12

o14

o1

o3

o5

o7

o9

o11

o13

o151110

copy stages routing stages

1010

00000100

translate



Switches and RoutersSW.4 Fast Datagram Switches

SR.1 OverviewSR.2 Fast packet switchesSR.3 Switch fabric architectureSR.4 Fast datagram switches

SR.4.1 Overall architecture and performance

SR.5 Programmable, active, & higher layer processing



Fast Datagram SwitchesMotivation

• Connection-oriented fast packet switching– emerged in ATM standards, but ATM failed

• IP became waist of global network infrastructure– increased processing capability enabled fast IP lookups– apply fast packet switching to IP datagram forwarding

Fast Datagram Switch Principle S-1Bd

There is compelling reason to perform high-speed connectionless datagram switching. Apply connection-oriented fast packet switching techniques to fast datagram switching, and exploit technology advances to implement the necessary additional input and output processing in the critical path.



Fast Datagram SwitchesArchitecture

• Fast packetswitch core

• Input processing– IP lookup– packet

classification

• Outputprocessing– packet

scheduling• fair queueing

input processing

management routing and signalling

switch fabric

classify

output processing

output scheduling

link

headerupdate

prefixesinput

processor

link

prefixesinput

processor

link

output scheduling

link

switch fabric

control



Fast Datagram SwitchesArchitecture: Shared Forwarding

input processing • Fast packet switch core• Input processing

– packet classificationmust be performed at input

• Shared forwarding engines– flexible allocation, but– uses switch fabric

ports and bandwidth

• Output processing– packet scheduling

• fair queueing


switch fabric

output processing

output scheduling

link

prefixes

header processing

prefixes

header processing

input processor

link

headers

input processor

link

headers

output scheduling

link

forwarding engines

switch fabric

control



Datagram Routing and SwitchingExample5.6 IP Packets

• 32 bit IP addresses– host or router interface

• Destination address– used by forwarding– longest-match

lecture IO

04 total lengthIHL TOSfragment id

TTL protocol header checksumsource address

destination addressoptions

(= hl – 20B)

payload(= length – hl – 20B)

flag frag offset



Fast Datagram SwitchesThroughput

• Packet processing rate critical– packet processing must sustain at least average rate– critical path must sustain peak line rate for min size packets

Packet Processing Rate S-II.4p

The packet processing rate (packets per second) is a key throughput measure of a switch. Packet processing software and shared parallel hardware resources must be able to sustain the average packet processing rate. Functions in the serial critical path must be designed for the worst case packet processing rate of the path to avoid queueing and blocking of subsequent packets.



Switches and RoutersSR.5 Programmable & Higher Layer Processing


SR.5.1 Alternative technologies and network processorsSR.5.2 Active network nodes



Switches and RoutersSR.5.1 Alternative Technologies





Switch ImplementationHardware Alternatives

• Alternative implementation technologies– hardware (fast but inflexible)

• custom VLSI vs. semicustom vs. standard• technology

– DRAM vs. SRAM vs. CAM– CMOS vs. GaAs

• electronic vs. optical

Functional Partitioning and Assignment PrincipleCarefully determine what switch functionality is to be implemented in scarce or expensive technology. S-1C



Switch ImplementationProgrammable Alternatives

• Alternative implementation technologies– fixed hardware (fast but inflexible)– programmable hardware (e.g. FPGAs)– software: flexible

• switch control CPU• general purpose embedded controller • network processor :

specialised embedded controller for packet processing



Switch ImplementationProgrammable Input/Output Processing

• Network processors– compromise among cost, flexibility, performance

• Advantages of input/output programmability– reduce switch design and debug time– allow field upgrades– allow service providers to deploy new protocols/services– enable per port active networking



Switch ImplementationProgrammable Input/Output Processing

• NPs replace– input processing

• lookup• classification

– output processing• scheduling

– additional• encryption• policing

– large buffers• off NP chip

input NPs and memory

management routing and signalling

switch fabric

classify

output NPs and memory

output scheduling

link

headerupdate

prefixesinput

processor

link

prefixesinput

processor

link

output scheduling

link




Higher Layer and Active ProcessingMotivation and Strategies

• Example motivation for processing in network nodes– firewalls– Web caches– active transcoders– multimedia stream mixing and merging

• Alternative strategies– application layer proxies– active network nodes– layer 4 and layer 7 switches– integration of function into layer 3 forwarding code



Higher Layer and Active ProcessingPerformance

• Active processing reasonable tradeoff– performance vs. flexibility

• Active processing must – not impede the normal fast forwarding path– occur with enough throughput so active queues don’t build

Active Network Processing S-II.4a

Active network processing should not impede the non-active fastpath; packet filters in the critical path must operate at line rate to pass non-active packets. The ability to perform per packet active processing requires sufficient processing power tosustain the require active packet throughput



Active ProcessingGranularity and Node Architecture

• Processing granularity– global control plane

• e.g. routing algorithm

– per flow control plane• e.g. modify RSVP

control

– per packet control plane• e.g. congestion control

– per packet data plane• e.g. transcoding

forwarding

pf

portAAs

portμOS

output processing input processing


switch fabric

forwarding

pf

portAAs

portμOS

active node processing

NodeOS

MEE

portAAs

portμOS

portAAs

portμOS

switch control



Switches and RoutersSR.5.2 Active Network Nodes





Active ProcessingNetwork Processors

• Network processors– enable per port

dynamic programmability

NP

forwarding

pf

portAAs

portμOS

output processing input processing


switch fabric

NP

NP

forwarding

pf

portAAs

portμOS

active node processing

NodeOS

MEE

NP

portAAs

portμOS

portAAs

portμOS

switch control



High-Performance NetworkingAcknowledgements

The material in these foils comes from the textbook supplementary materials:

• Sterbenz & Touch,High-Speed Networking:A Systematic Approach toHigh-Bandwidth Low-Latency Communicationhttp://hsn-book.sterbenz.org

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