jbee final reporthomepages.wmich.edu/~bazuinb/research/feast_freport.pdf · final report 1 june,...

2001, Bradley J. Bazuin

Michigan Space Grant Consortium Seed Grant

Final Report

1 June, 2001

Flexible Electrical and Software Programmable Transceivers (FEAST)

for Wireless Communications

Dr. Bradley J. Bazuin Assistant Professor

Western Michigan University, Department of Electrical and Computer Engineering


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Table of Contents Section Title Page

Table of Contents ........................................................................................ ii Table of Figures..........................................................................................iii Table of Tables............................................................................................ v

1. Introduction ............................................................................................... 6 1.1. Identification and Significance of the Problem or Opportunity .................. 6 1.2. Opportunity for Technical Development..................................................... 8 1.3. Education and Research Applications ......................................................... 9

2. Project Overview ..................................................................................... 10 2.1. Prototype Development ............................................................................. 11 2.2. Technical Objectives ................................................................................. 12 2.3. Deliverables............................................................................................... 12 2.4. Relationship with Future Research or Research and Development .......... 13 2.5. Report Organization .................................................................................. 13

3. FEAST Development............................................................................... 14 3.1. ISM Band RF Design ................................................................................ 15 3.2. Programmable Digital Downconverter...................................................... 17 3.3. Programmable Digital Upconverter .......................................................... 17 3.4. Digital Signal Processor ............................................................................ 17 3.5. Software Development .............................................................................. 19

3.5.1. Real-Time Software Structure................................................................... 19 3.5.2. Software Demodulation............................................................................. 21

3.6. PC Host, User Interface, Command and Control ...................................... 24

4. Detailed Design ........................................................................................ 25 4.1. RF Design.................................................................................................. 26

4.1.1. ISM Receiver............................................................................................. 27 4.1.2. ISM Transmitter ........................................................................................ 30 4.1.3. Additional RF Considerations ................................................................... 32

4.2. Digital Design............................................................................................ 34 4.2.1. Analog-to-Digital Converter ..................................................................... 34 4.2.2. Digital Downconverter .............................................................................. 35 4.2.3. Digital Upconverter ................................................................................... 37 4.2.4. Digital-to-Analog Converter ..................................................................... 39 4.2.5. Digital Interface......................................................................................... 39 4.2.6. DDC/DUC Development Environment..................................................... 40 4.2.7. Digital Design Components and Cost ....................................................... 41

4.3. TMS320C6701 DSP Evaluation Module.................................................. 42


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Table of Contents (cont) Section Title Page

4.4. Firmware Design ....................................................................................... 44 4.4.1. Multi-Channel Buffered Serial Port (McBSP) .......................................... 44 4.4.2. Direct Memory Access (DMA) ................................................................. 46 4.4.3. TI Supporting Documents ......................................................................... 48

4.5. Software Design ........................................................................................ 49 4.5.1. Software Development Flow..................................................................... 50 4.5.2. Real-Time Signal Processing .................................................................... 51 4.5.3. Personal Computer Host............................................................................ 51

5. Test and Verification............................................................................... 54 5.1. RF Receiver and Transmitter .................................................................... 54 5.2. ADC and DDC .......................................................................................... 54 5.3. DSP............................................................................................................ 55 5.4. DUC and DAC .......................................................................................... 56

6. Key Contributors..................................................................................... 57 6.1. Principal Investigator................................................................................. 57 6.2. Staff, Student Involvement........................................................................ 57 6.3. Funding Support ........................................................................................ 57 6.4. Additional Support and Donations............................................................ 58

7. Summary .................................................................................................. 59 7.1. Progress ..................................................................................................... 59 7.2. Conclusion................................................................................................. 61

8. References ................................................................................................ 62

Table of Figures Section Title Page Figure 1. Typical Dedicated Receiver and Transmitter Block Diagram........................... 7 Figure 2. FEAST Receiver and Transmitter Block Diagram............................................ 8 Figure 3. Flexible, Electrical and Software Programmable Transceiver (FEAST)

Block Diagram ................................................................................................ 10 Figure 4. Prototype Components for the FEAST............................................................ 14 Figure 5. The Radio Spectrum........................................................................................ 15 Figure 6. ISM Receiver Block Diagram. ........................................................................ 15 Figure 7. ISM Transmitter Block Diagram..................................................................... 16 Figure 8. Digital Downconverter Module Block Diagram ............................................. 17 Figure 9. Digital Upconverter Module Block Diagram .................................................. 18 Figure 10. TMS320C6701 DSP Evaluation Card Block Diagram ................................... 18


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Table of Figures (cont) Section Title Page Figure 11. Main Software Loop Processing Flow ............................................................ 20 Figure 12. Delta Phase Computation Simulation Results................................................. 24 Figure 13. FEAST Subsystem Block Diagram ................................................................. 25 Figure 14. Receiver Signal and Noise Power Levels........................................................ 27 Figure 15. Receiver Processing Stages ............................................................................. 28 Figure 16. ISM Receiver Processing Stages ..................................................................... 29 Figure 17. ISM Transmitter Processing Stages................................................................. 31 Figure 18. Prototype FEAST RF Receiver and Transmitter Photo .................................. 33 Figure 19. AD6640 Functional Block Diagram................................................................ 35 Figure 20. Digital Downconverter Module Block Diagram ............................................. 35 Figure 21. ADC and DDC Development Modules Connected for Testing ...................... 36 Figure 22. DDC Development Modules Spectral Display................................................ 36 Figure 23. AD6620 DDC Block Diagram ........................................................................ 37 Figure 24. Digital Upconverter Module Block Diagram .................................................. 37 Figure 25. Digital Upconverter Module Photograph ........................................................ 38 Figure 26. AD6622 DUC Block Diagram ........................................................................ 39 Figure 27. AD9754 Functional Block Diagram................................................................ 39 Figure 28. AD6620 Filter Design Wizard Composite Filter ............................................ 41 Figure 29. TI TMS320C6701 Development Module Photo ............................................. 42 Figure 30. TMS320C6701 DSP Evaluation Card Block Diagram ................................... 43 Figure 31. TI320C6701 Host Support Software Block Diagram ..................................... 44 Figure 32. McBSP and Control Registers......................................................................... 45 Figure 33. DMA Controller Interconnection within the ‘C6701 ...................................... 46 Figure 34. FEAST Software Processing Block Diagram.................................................. 49 Figure 35. TI ‘6701 Suggested Software Development Flow .......................................... 50 Figure 36. AD6620 Board Command and Control GUI................................................... 52 Figure 37. AD6622 Board Command and Control GUI .................................................. 53 Figure 38. Spectral Snap Shot Centered at 860 MHz (Cellular Telephone)..................... 55 Figure 39. Spectral Snap Shot Centered at 915 MHz RF Band (ISM) ............................. 56


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Table of Tables Section Title Page Table 1. Signal Types, Desired Filter Bandwidths, and Decimation Ratio and Signal

Rates ................................................................................................................ 22 Table 2. Receiver Cascaded Gain and Noise Figure ..................................................... 28 Table 3. Receiver Parts List and Cost ........................................................................... 30 Table 4. Transmitter Cascaded Gain and Noise Figure................................................. 31 Table 5. Transmitter Parts List and Cost ....................................................................... 32 Table 6. Additional RF Components, Cable Assemblies, and Connectors ................... 32 Table 7. Total RF Costs................................................................................................. 32 Table 8. Total Digital Design Component Costs........................................................... 41 Table 9. McBSP Register Names and Addresses .......................................................... 46 Table 10. DMA Command and Control Register Assignments ...................................... 47 Table 11. TI Development Support Literature ................................................................ 48 Table 12. Software Development Flow Description [20] ............................................... 51


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1. Introduction

Communications systems have experienced rapid advancement due to the demand created for mobile and local wireless communications devices. Whether the communications contains data or voice traffic, the implementation, design techniques, and evolving technology provides a tremendous breadth of opportunities for research and teaching in the university environment and the development of flexible communications technologies for NASA satellite and other space based platforms.

Current space and aerospace communications systems are based on well-defined conventional signal structures and components specifically defined to process known, predefined voice and data signals. Using modern technologies, currently being developed and deployed for cellular telephony and wireless data access, a new class of flexible, electrical and software programmable transceiver (FEAST) can be developed. A FEAST development will enable a wide range of communications signals to be received and transmitted using a common, reprogrammable, open architecture system.

Particular benefits for space and aerospace applications include the programmable use of variable signal formats based on the required data transfer rates, useable bandwidth, path loss and link margins, processing gains, and signal encoding or encryption. Further, using a single, common design, a pool of FEAST systems can provide flexibly assigned spare transceivers for increased communication system redundancy and reliability.

This project will also provide a strong foundation for the training of both undergraduate and graduate students in the fields of communications, signal processing, electrical design (RF, IF, analog, and digital), and real-time computer and software engineering. Various FEAST prototypes will provide a range of classroom demonstrations, hands-on laboratories, and valuable research tools in meeting the educational mission of Western Michigan University and the Electrical and Computer Engineering Department.

1.1. Identification and Significance of the Problem or Opportunity

Current space and aerospace receivers are based on well-defined communication signal structures and components specifically defined to process these signals in the radio frequency (RF), intermediate frequency (IF), and baseband domains. Under normal operating condition, multiple unique receivers each composed of a small set of components can perform all required tasks reliably for years. Regrettably, component and mission problems and failures do occur. Recent problems include the NASA probe of the outer planets that lost a high gain antenna and mission to Mars where the surface vehicle may have landed intact but the orbiting satellite that was to act as a transponder was lost. In the first case, data was rerouted through a low gain antenna and at a significantly reduced data rate, reducing the mission data available. In the second instance, a research teaming using the “dish” at Stanford University was able to receive an identifiable signal


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from the lander, but no intelligible data could be decoded. In both instances, redundant, programmable format transceivers could greatly enhance mission performance and success. Figure 1 shows a conventional transceiver system using dedicated receivers and transmitters.

High GainLNA

Rcv #2 Rcv #n

Tx #1 Tx #2 Tx #m

Low GainLNA

Low GainAmp

High GainAmp

Dedicated Receivers

Dedicated Transmitters

Baseband Processing

Rcv #1

Combine

Combine

ConventionalTransciever

System,Networkor SensorInterface

Figure 1. Typical Dedicated Receiver and Transmitter Block Diagram.

Each receiver and transmitter is capable of one specific communications signal format and task. Antennas are connected to predefined transceiver elements.

By embedding special programming and using FEAST based systems, alternate communications formats that optimize the signal format for possible mission scenarios could be available. While the Mars mission may have had the programming embedded from the initial design, the probe could have easily been downloaded with new programming, even if the communication technique and signal format hadn’t been developed prior to the launch of the vehicle. Figure 2 shows a multiple-antenna, multiband, multiple-format transceiver using the FEAST architectural concept.

The reprogrammability of the FEAST architecture provides many inherent advantages for satellite applications. While normally designed for 3 to 8 years missions, many satellites maintain some form of useful operation for 10 to 15 years or more. During this time frame, the satellite performs its predefined function while the demand for communications continually increases and changes. While easily justified from a financial perspective, if the transponders could be upgraded on-station, increased capacity and reliability could be attained along with a healthy increase in revenues for commercial satellites.


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High GainLNA

RF-ADC#n

Sum DACto RF #1

Sum DACto RF #j

Low GainLNA

Flexible RF Distribution

Low GainAmp

High GainAmp

Flexible RF Combine

FEASTReceiver Pool

FEAST Transmitter Pool

Baseband Processing

RF-ADC#1

System,Networkor SensorInterface

FEAST BasedTranscieverArchitecture

Rcv C

omm

and andC

ontrolT

x Com

mand and C

ontrol

Rcv#1

Rcv#2

Rcv#m

TX#1

TX#2

TX#k

Digital Data Distribution

Digital Data Distribution

Figure 2. FEAST Receiver and Transmitter Block Diagram.

All digital receiver and transmitter pools can be arbitrarily programmed and assigned to any antenna, RF band, or signal format.

As a terrestrial application, the world has become increasingly populated with cellular and wireless basestations to support the growing communication demands. Currently, each carrier uses one of the defined cellular standards (e.g. AMPS, NAMPS, CDMA, GSM). As four carriers may now exist in any US location (two in the cellular band and two in the PCS band), four distinct basestations using four unique sets of transceivers may be require for every coverage region. If a common transceiver could be designed and flexibly allocated to each of the tasks based on demand, a tremendous savings in hardware and cost could be attained.

1.2. Opportunity for Technical Development

Current technological advancements in communications are focused on reducing the size, weight, power, and complexity of existing transceivers and on defining extensions of existing systems and techniques. As a result, the components and technology being made available enable the development and demonstration of a range of both new and hybrid communication transceivers. Hybrid transceivers are defined to process multiple defined signal formats, either sequentially or simultaneously, using one common set of components. While AM/FM/TV-Band radios have existing for many years, high sample


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rate analog-to-digital and digital-to-analog converters, programmable multirate filters, programmable logic devices and software programmable digital signal processors may now enable transponders to programmably receive and transmit simple signals (AM, FM, FSK, SSB) and more complex (AMPS, GSM, CDMA, DSSS, Frequency Hop, etc.) communications using one common transceiver design. New communications systems, formats, and transceivers are also being developed. The new systems, using similar components and architectures, are developing theoretically optimized signal formats that make use of the full available bandwidths, mitigate for projected channel impairments including multipath, provide capacity on demand, and improve performance and security through coding and encryption techniques.

The proposed research project seeks to define and develop architectures, algorithms, techniques, prototypes, and software programming for both hybrid and new communications transceivers and systems.

1.3. Education and Research Applications

As an educational tool, prototype FEAST systems provide an opportunity for both classroom demonstrations and laboratory hand-on experimentation with each of the elements of the architecture. While based on communications and digital signal processing algorithms and techniques, the prototypes also demonstrate modern RF receiver and transmitter design, high-speed real-time digital design, computer architecture, and real-time software engineering.

As a research tool, FEAST prototypes provide a base for a wide range of computer, signal processing, communications, and signal processing work. By employing an open architecture, the FEAST allows the rapid reprogramming and interchange of component parts. This provides for the direct component level test, evaluation and comparison of:

• RF and IF receiver and transmitters; • high speed analog-to-digital (ADC) and digital-to-analog (DAC) converters; • selected dedicated digital communications processing components (e.g. direct

digital up/downconverters, digital filters and equalizers, programmable devices used for hardware communications processing, etc); and

• modern microprocessors and digital signal processors (e.g. Pentium III, G4 Power PC with AltiVec, TI TMS320C6201 and ‘C6701, Phillips Trimedia processor, etc.).

A FEAST prototype can provide a reference platform to develop high-level and application specific programming and software. This features enables a direct comparison and analysis of proposed and existing communication signals while providing a tool for improving and advancing upon the state-of-the-art. A FEAST prototype can be used for development of unique communication signals such as the emerging third and forth generation cellular telephony proposals involving wideband CDMA, advanced GSM, or the application of discrete multi-tone (DMT).


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2. Project Overview

The goals in establishing this research are to define, develop and demonstrate flexible, electrical and software programmable transponders (FEAST) for wireless communications. The basic FEAST architecture is shown in Fig. 3. The receiver path consists of a wide bandwidth RF to IF downconverter, a high-speed analog-to-digital converter (ADC), integrated direct digital downconverter (DDC) and filter, and a high-speed programmable digital signal processor (pDSP). The transmission path inverses the components in the receiver with an integrated digital upconverter (DUC) and filter, a digital-to-analog converter (DAC), and an IF to RF upconverter and amplifier. With this architecture, the FEAST can be programmed for a wide range of communication signal formats and processing requirements, only limited by the RF tuning range, attainable ADC and DAC rates, the pDSP processing capacity, and the ability to develop real-time processing software.

Satellite

Radio tow er

IBM Com patible

RF to IFReceiver

A to DConvert

DigitalDow n-

Converter

DigitalSignal

Processor

Digital U p-Converter

D to AConvert

IF to RFTransm it

Figure 3. Flexible, Electrical and Software Programmable Transceiver

(FEAST) Block Diagram

The initial communications processing and digital signal processing focuses on simple forms of communications [1, 2, 3, 4], building the tools and utilities required to perform more advanced research and installing the components most applicable for providing educational demonstrations and hands-on laboratories. These tasks include:

• Real time data collection and storage for post-processing evaluation; • Snap shot data analysis capabilities performing spectral analysis and signal

correlation; • Digital filtering for both general spectrum, pre- and post-demodulation filters; • Simple demodulation processing of AM, FM-narrowband, FM-wideband, and

FSK; • Unlicensed ISM band transmitter to receiver verification using FSK or FM; and • PC host tools to support continued development.


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2.1. Prototype Development

The initial design and development of a FEAST applies rapid prototyping techniques using available industry modules and test kits for the individual blocks, readily available WMU laboratory computers, modules an d test equipment, and a range staffing based on interested undergraduate and graduate students under the direction and guidance of Dr. Bradley J. Bazuin.

The initial RF receiver electronics uses existing test equipment prior to the development of suitable instrumentation, scientific and medical (ISM) band transceiver. The ADC, DAC, digital and pDSP hardware will be based on widely available component manufacturers test and development kits. With the proliferation of new, advanced components the test and development kits provide a way for engineers to rapidly learn about and incorporate the components into new and existing designs. For this project, the kits will function as training aids to the students and the building blocks for the prototype FEAST system. Examples of kits directly applicable to FEAST development include: Analog Devices AD6640 12-bit 64 Msps analog-to-digital converter (AD6640ST/PCB), Analog Devices AD6620 dual channel digital IF downconverting filter-decimator evaluation kit and development software, GrayChip quad digital receiver and transmitter evaluation boards developed by Coryell & Wiprud (EV-4014 and EV-4114), Xilinx prototype development platforms (BG560-100 Prototype Package For Virtex and Virtex-E Devices), and Texas Instruments TI320C6201 DSP Test and Evaluation Board

Each development kit or board contains either prototyping area or connectors that are sufficient to provide interconnect cabling to rapidly prototype the FEAST processing electronics. In addition, each kit comes with appropriate documentation, development software, and PC compatible interfacing for configuration, command, control, or programming. As an added feature, alternate development kits can be readily substituted into the system architecture as components improve and/or processing requirements change to meet varying research or application demands.

Software development employ PC based development environments using high-level language programming in C where possible and targeted custom assembly language for drivers or critical real-time operation.

To support the hardware and software developments, modeling and simulation of the processing performed will be performed using MATLAB. The algorithmic simulations will provide a performance estimate of the FEAST components while also providing test vectors for the validation of hardware and software components as they are completed.


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2.2. Technical Objectives

The technical objectives of the seed project are: • Define the initial FEAST prototype architecture and identify the critical

components and development kits required; • Procure and/or acquire the development kits, test equipment, and laboratory space

with the support of WMU’s ECE department; • Select promising undergraduate and graduate students as funded research

assistants (Note: Jonathon Barber has submitted an individual grant request in this area);

• Design, build, and test the receiver and transmitter processing elements (ADC, DAC, DDC, DUC, Xilinx support logic, pDSP and PC Host interfaces);

• Design, code, and test real-time pDSP modules and program and PC Host modules and program software; and

• Demonstrate FEAST receiver capabilities using readily available signal sources (e.g. AM and FM radio, aircraft communications bands, CB radio transmissions); and

• Demonstrate FEAST IF output to IF input loop back capability using multiple signal formats.

The technical objectives for follow-on work include: • Design, build, and test ISM band RF to IF and IF to RF receiver and transmitters; • Generate a MATLAB model and simulation of the FEAST hardware

configuration for defining and testing additional communications signal formats; • Incorporate real-time pDSP software for receiving and processing current and

next generation cellular telephone traffic; • Perform comparative computer processor analysis for real-time signal processing

between modern DSP devices and emerging “general purpose” processors (e.g. Pentium III with vector processing and G4 Power PC with AltiVec); and

• Increase the number of FEAST prototypes to begin research into both spatial and space-time beamforming as applied to communications signals.

2.3. Deliverables

Deliverable items on this project shall consist of an interim progress report and a final report.

The interim report will be composed, reviewed and delivered by 31 December 2000. The report will include a detailed description of the FEAST architecture, enumeration of the system components and projected capability, a description of detailed accomplishments to date, a list of student and staff involvement and support for the efforts (both funded and


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unfounded), a description of ongoing proposals and grant requests related to this work, and an assessment of the overall state of the project.

The final report that expands upon and updates the material presented in the interim will be composed and delivered by 1 June, 2001. In addition, the FEAST prototype test results will be defined and presented, a synopsis of student educational opportunities will be provided, and an assessment of the research expertise gained by the principal investigator will be provided. Copies of all research papers and reports developed during this phase of the project will also be included as an addendum to the final report.

2.4. Relationship with Future Research or Research and Development

Potential applications of the architecture, techniques, and components used in this project include:

• SBIR and STTR Proposals for Flexible Communications Systems. • Department of Defense 6.2 and 6.3 development funds to define novel

communications signal formats for high capacity and low probability of intercept. • Commercial grants from wireless and cellular carriers for signal format analysis,

comparison, and development.

2.5. Report Organization

The following sections provide an overview of the FEAST architecture describing each of the critical components and subsystems, describe the detailed design of the FEAST subsystems and present initial test results, acknowledge the support and contributions of contributors to this work, and provide a summary of the work completed.


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3. FEAST Development

The first phase the FEAST seed program has focused on putting together a group of students to support the work, studying available techniques and components, and creating a preliminary system for purchase, fabrication, construction, and coding. The second phase, currently underway, involves acquiring the necessary parts and devices, fabricating and assembling the various system components or subsystems, coding and testing software, integrating the hardware and software elements together, and performing various tests and demonstrations of the completed FEAST prototype.

The FEAST prototype is composed of a number of distinct subsystems and processing stages as shown in Fig. 4. There are two significant custom RF design components, the ISM receiver and transmitter, three separate evaluation modules from Analog Devices, a PC card DSP development module from Texas Instruments, and a host IBM compatible PC for software code development, command, control, and display.

Custom ISMReceiver

SpectrumAnalyzerwith IFOutput

AD6640S/PCBADC Evaluation

Module

AD6620S/PCBDigital

DownconverterEvaluation Module

TI320C6701DSPEvaluation Module

Crystal Oscillator40-65 MHz

IBM PCCompatible

Host

AD6622S/PCBDigital Upconverter

with DACEvaluation Module

Custom ISMTransmitter

Monitor

Keyboard

Figure 4. Prototype Components for the FEAST

Also shown for general receiver testing is the use of a spectrum analyzer as a fixed tuned receiver with a controllable IF bandwidth. In this mode, the spectrum analyzer start and stop frequencies are set to the same, desired RF center frequency and the video bandwidth is set to the desired IF bandwidth. The IF output is then directly feed to the ADC for either direct sampling or subsampling based on the IF center frequency.

The following subsections provides an overview of the FEAST prototype preliminary design and the critical subsystems.


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3.1. ISM Band RF Design

The FEAST prototype is intended to both receive and transmit RF signals. While the receiver can be designed to collect and process almost any radio frequency band, signal transmission is closely reviewed, observed and regulated by the Federal Communication Commission (FCC). To transmit a signal, the frequency band must be well defined and preferable available for scientific or research purposes. The spectrum commonly referred to as the “Radio Spectrum” is shown in Fig. 5. Spectrum has been allocated for these purposes at specific Instrumentation and Scientific Measurement (ISM) frequencies. The FEAST project will use one of the ISM band, from 902 MHz to 928 MHz directly above the cellular telephone bands.

30 kHz

LW MF HF VHF UHF

300 kHz 3 MHz 30 MHz 300 MHz 3 GHz

AMFM

T V 2-6 AVT V 7-13 CELL

ISMCELL

T V

Figure 5. The Radio Spectrum.

The approximate locations of common signals are shown.

The FEAST ISM receiver is designed as a conventional super-heterodyne architecture as shown in Fig. 6. The key aspect of the design for a software radio is to provide as wide a signal bandwidth as is reasonable to the analog-to-digital converter (ADC) for digitization. For this system, the ADC selected is the Analog Devices 12-bit, high sample rate, high spur-free dynamic range, high signal-to-noise ratio (SNR) AD6640. This ADC can provide a sample rate of up to 65 MHz and is available on an evaluation module from Analog Devices. Based on Nyquist sample rate criteria, the AD6640 allows a passband of up to 32.5 MHz to be used. To allow for a lower clock rate and a more reasonable IF filter shape factor, a nominal IF passband of 20 MHz has been selected allowing a sample rate of 62 MHz.

Pre-selector

IF BandpassFilter

LowpassFilter

TuningSynthesizer

LocalOsc.

ADCLNA

Tuniing

DigitalOutput

fc=915 MHz

fc=140 MHzBW =20 MHz Nom

fs=1055 MHz

fs=62 MHz

fs=155.5 MHz

f=29 MHz

Figure 6. ISM Receiver Block Diagram.

To facilitate the passband and sample rate, the IF filter and mixing frequencies must provide the appropriate center frequency and spectral shape. The IF filter establishes the


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bandwidth of the passband. For this receiver, two cascaded surface acoustic wave (SAW) filters will be used. SAWTEK has a range of catalog SAW filters with a center frequency of 140 MHz that meet the filter design goals.

With the availability of 140 MHz SAW filters, the first mixing stage of the receiver can be defined. To downconvert the ISM band centered at 915 MHz to 140 MHz, a local oscillator of either 915-140 MHz or 915+140 MHz can be used (either 775 MHz or 1055 MHz). Numerous oscillators and synthesizers are now available to support either of these frequencies. Based on harmonic and higher order product concerns, a high side local oscillator (LO) at 1055 MHz will be used.

Using an ADC sample rate of 62 MHz of a real signal, it is advantageous to center the passband between 0 and half of the Nyquist rate (between 0 and Fs/2). If we center the analog baseband signal at Fs/4 or 15.5 MHz, the spectral band of interest resides between 5.5 and 25.5 MHz. For ADC aliasing considerations, this perfectly centers the spectrum and minimizes the effect of any out-off-band signals. To provide a non-inverted, centered spectrum at 15.5 MHz, the second mixing stage LO is set at 155.5 MHz (140+15.5 MHz).

The ISM transmitter uses the same considerations and many of the same components as the ISM receiver. The transmitter block diagram is shown in Fig. 7. The transmitter inverts the signal processing sequence of the receiver and uses the same mixers, IF filter and first and second LOs. The transmitter converts the software radio’s digital waveform to analog using a digital-to-analog converter (DAC). The Analog Devices AD9754 provides a 14-bit high rate, low noise output that is first filtered for harmonic content and then converted to the IF and RF frequencies desired. The RF signal after the final mixing stages is amplified by a simple preamplifier and uses a conventional LC transmission filter to reduced any out-of-band signals before driving the antenna.

LocalOsc.

IF BandpassFilter

Synthesizer

DACPre-AMP

XmitFilter

LowpassFilter

Tuniing

DigitalInput

fc=915 MHz

fc=140 MHzBW =20 MHz Nom

fs=1055 MHz fs=155.5 MHz

f=29 MHz

fs=62 MHz

Figure 7. ISM Transmitter Block Diagram

The ISM receiver and transmitter uses a number of packaged modules from Mini-Circuits to perform the signal processing and conditioning required. In particular, the mixers and amplifiers are all catalog items available from Mini-Circuits.


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3.2. Programmable Digital Downconverter

The wide bandwidth digitized data from the ISM receiver is digitally tuned, filtered, and decimated to isolate narrower bandwidth signals of interest (SOIs) from the wide bandwidth input spectrum [5,6]. An integrated circuit digital downconverter (DDC) provides fine-tuning of the desired SOI to be centered at 0 Hz. It then uses a concatenated integrator comb or Hogenauer [7] filter to isolate a narrow bandwidth around 0 Hz and decimates the input data rate to a lower rate that is much more easily processed. The CIC filter is followed by a programmable FIR filter to flatten the signal passband and provide additional shaping and attenuation in the stopband.

The DDC is also available as an evaluation module. The block diagram for the AD6620S/PCB is shown in Fig. 8. The module has been designed to directly connect an input header to the output pin header of the AD6640 ADC module. For connection to the following Texas Instruments (TI) digital signal processor (DSP) a custom ribbon connector inserts between the output header shown and the high-speed serial input-output port (SIO) of the DSP module.

Data Latch

Header

AD6620

Data LatchData Latch

FIFO16k

Inputfrom ADC

Data Latch

Outputto SIO

T ransceiver

PC PrinterPort

Figure 8. Digital Downconverter Module Block Diagram

3.3. Programmable Digital Upconverter

To generate the baseband signal for ISM transmission , the FEAST transmitter inverts the processing performed in the ADC and DDC using a digital upconverter (DUC) and digital-to-analog converter (DAC). For this project, these components are combined on a single evaluation module from Analog Devices, the AD6622S/PCB. A block diagram of this recently released device and module is shown in Fig. 9.

3.4. Digital Signal Processor

The digital signal processor selected for the initial FEAST prototype is the Texas Instruments TMS320C6701. It has been selected based on two significant factors, it is the most recent offering in high speed DSPs and, through a previous grant to the WMU ECE department, a development and evaluation card with tools is available for use on this project. A block diagram of the card is shown in Fig. 10.


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Data Latch

Header

AD6620

CrystalOscillator

SIO Inputs

ControllerPC Com Port

AD9754

AnalogOutput

Figure 9. Digital Upconverter Module Block Diagram

Figure 10. TMS320C6701 DSP Evaluation Card Block Diagram [17]

Latest in a long line of TI DSPs, the ‘6701 is a high speed, very-long instruction word (VLIW) parallel floating point processor. With eight functional units consisting of four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-fixed-point multipliers, the '6701 can produce two multiply-accumulates (MACs) per cycle at a clock


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rate of 167 MHz for 334 million MACs per second (MMACS). With this inherent processing capability, the ‘6701 provides great flexibility for the development of real-time processing software.

The development card hosting the VLIW processor provides a large bank of on-chip memory and has a powerful and diverse set of peripherals for the FEAST system. Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space. Data memory consists of two 32K-byte blocks of RAM. The inherent ’6701 peripheral set includes two multichannel-buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals. The evaluation module includes a CD-quality, 16-bit audio interface with stereo microphone and line-level inputs and a stereo line-level output. A multimedia audio CODEC is used that supports all popular audio sample rates from 5.5kHz–48 kHz. The CODEC and audio interface will be used for received signal audio output and for providing transmitted signal audio input.

In operation, the CODEC, DDC, and DUC data are all in a bit serial format. To collect and transmit FEAST data, the ‘6701 will use the McBSP serial ports, one for CODEC data and the second for DDC and DUC data. In addition, the ‘6701 will use an internal four-channel direct memory access (DMA) controller programmed to work directly with the McBSP ports to efficiently handle the transfers of real time data.

3.5. Software Development

At the heart of FEAST technology and all-digital, software radios is the real-time processing software. This includes the critical firmware that handles all interfacing and device driver tasks and the principal digital signal processing code that provides filtering, demodulation, decoding, reformatting, encoding, and modulation. For real-time applications, the firmware and software must continuously operate within defined processing periods or have a total percent utilization of the time period of less than 100%.

By employing the high processing rate ‘C6701 and initially focusing on simple, conventional, narrowband modulation formats, the challenges of developing real-time software should be minimized. As a result, the FEAST digital processing software will be developed predominantly in C with critical firmware and drivers in assembly language where necessary. To support code development and achieving real-time operations, the '6701 modules came with a complete set of development tools, which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a WindowsTM debugger interface for visibility into source code execution.

3.5.1. Real-Time Software Structure

The FEAST code is divided between initialization and setup code, time critical interrupt service routines (ISRs) and an infinite main processing loop that calls various processing functions as flags are set by the ISRs. For real-time operation, the input and output of data


20

can take a significant amount of the processor clock cycles. To minimize the data handling load on the‘6701, the FEAST will use the internal McBSP ports and four channel DMA controller to transfer data on and off from the processor. With a firmware setup, the DMA controller will input and output data blocks at the required input and output rates. When an incoming data block is full or an outgoing block is empty, an interrupt will be generated. The corresponding ISR will then initiate the next DMA process and flag the main processing loop to provide or process more data. The data handling ISRs will have top priority and be allowed to interrupt all other system operations.

Lower priority and health check ISRs will be used for DSP communications with the host PC and a watchdog timer. The watchdog timer operation uses an internal timer to continuous count down from a preset value. The value is set slightly longer than the periodicity required to maintain real-time operation. Then, as every periodic loop completes, the timer is reset and begins counting down again. If the watchdog timer ISR ever occurs, real-time operation has been violated and appropriate action can be taken.

The FEAST main loop will monitor a set of operational flags that define which processes to perform during each cycle through the loop. The main loop contains the data processing objects, objects for communicating with the host for command, control and display functions, and monitor and health check functions. The processing flow of the main loop is shown in Fig. 11.

Initia lization

Main LoopStart

End MainLoop

Data BlockLoading for

DMA

DataProcessingOperation

HostCommand

and Control

Host Displayand Status

State FlagEvaluiation

State andMode

Updates

W atchdogReset

Figure 11. Main Software Loop Processing Flow


21

During each pass through the main loop the operational state will define which objects should be executed. The objects are separated into two classes, those executed on every loop and prioritized operating flags where only one process per loop is allowed. The objects that should be run on every loop are; command state and mode updating and the watchdog timer reset. The objects that are executed based on priority and their order of importance are:

• Data block loading for DMA – transmit data block loading – output audio block loading – receive data loading – input audio or data loading

• Data Processing Operations – processing received data into audio or output data – processing input audio or output data into transmit data – receiver functions include spectrum collection, noise floor estimation,

signal search and detection, and demodulation, – transmitter functions include of test signal generation and modulation

• Host command and control – host command reception and acknowledgement

• Host display and status data output. – requested displays and operational logs

3.5.2. Software Demodulation

One of the primary functions of the FEAST is to perform digital demodulation of the filter-decimated output of the DDC. In this mode, the RF and DDC are fixed tuned or set-on a particular frequency, a filter and decimation ratio is selected for the DDC based on the signal type, and a software demodulation process is enabled. Initially common modulation formats will be processed with know bandwidth and signal parameters. A list of the intended FEAST demodulation signal formats, their bandwidths, the planned pre-demodulation sample rate (into the DSP) and the DDC decimation ratio (assuming a 62 MHz sample rate) required is shown in Table 1.

In performing demodulation, the signal data entering the demodulator must have a bandwidth wider than that described by the signal parameters, be sufficient to meet the Nyquist criteria, and provide reasonable values within the capability of the preprocessing hardware. The demodulation processing will perform required operations and may also provide a further data rate reduction. For telephone quality audio output, a post demodulation signal with a passband of ±3 kHz and sample rate of 8 kHz is desired.

The following sections provide a brief description of each of the proposed demodulators for the signal types specified.


22

Table 1. Signal Types, Desired Filter Bandwidths, and Decimation Ratio and Signal Rates

Signal Type Rejection Level Predemod Bandwidth

Decimated Sample Rate

Decimation Ratio

SSB (U/L) 1.0 dB ±1350 kHz 8.0 kHz 7750

75.0 dB ±2000 kHz

AM 1.0 dB ±3000 kHz 16.0 kHz 3875

75.0 dB ±5000 kHz

FSK 0.2 dB ±8.75 kHz 50.0 kHz 1240

75.0 dB ±16.25 kHz

FM1 0.2 dB ±7.5 kHz 50.0 kHz 1240

75.0 dB ±17.5 kHz

FM2 0.2 dB ±17.5 kHz 100.0 kHz 620

75.0 dB ±32.5 kHz

3.5.2.1. Single Side-band (SSB):

Digital down conversion generates an 8 kilo-complex samples-per-second (kcsps) output with a passband of ±2 kHz and a stopband of nominally ±3.2 kHz. A 34-tap FIR filter is used to achieve the desired ±1.35 kHz passband and ±2.00 stopband (-60 dB). The baseband signal is complex modulated by ±1.65 kHz to place the sideband at the appropriate frequency. Demodulation is completed by taking only the real part of the complex result. The final real signal has a single sided passband from 0.30 to 3.00 kHz with a stop band at 3.65 kHz.

3.5.2.2. Amplitude Modulation (AM):

Digital down conversion generates a 16 kcsps output with a passband of ±4 kHz and a stopband of nominally ±6.4 kHz. A 35-tap half band FIR filter is used to achieve the desired ±3.25 kHz passband and ±4.75 stopband (-60 dB). Demodulation is performed by taking only the real part of the complex result. The final real signal has a single sided passband from 0 to 3.25 kHz with a stop band at 4.75 kHz. A final stage of low pass filtering and decimation by 2 is used to reduce the output sample rate to 8 ksps. The final 40-tap FIR filter has a single sided passband to 3.00 kHz and a stop band at 4.00 kHz.

3.5.2.3. Narrow Bandwidth Frequency Modulation (FM1)

Digital down conversion generates a 50 kcsps output with a passband of ±12.5 kHz and a stopband of ±19.91 kHz. A 15-tap half band FIR filter is used to achieve the desired ±7.5 kHz passband and ±17.5 stopband (-60 dB). Demodulation is performed by first extracting the phase from the complex representation. Then, the phase difference is used as the sample-by-sample derivative to find the baseband signal. The 50 ksps data is then


23

filtered and decimated by a cascade of half band filters and decimate by 2 stages. Two stages bring the audio data rate down to 12.5 ksps from the post-demodulation 50 ksps. The first 15-tap half band FIR filter has a cutoff at 7.5 kHz and stopband edge at 17.5 kHz. The second 35-tap half band FIR filter has a cutoff at 5 kHz and stopband edge at 7.5 kHz. A final 16-tap FIR filter is used to cleanup the audio output. This final filter has a cutoff at 3.0 kHz and stopband at 5.0 kHz.

3.5.2.4. Wider Bandwidth Frequency Modulation: (FM2):

Digital down conversion generates a 100 kcsps output with a passband of ±25 kHz and a stopband of ±39.81 kHz. A 23-tap half band FIR filter is used to achieve the desired ±17.5 kHz passband and ±32.5 stopband (-60 dB). Demodulation is performed by first extracting the phase from the complex representation. Then, the phase difference is used as the sample-by-sample derivative to find the baseband signal. The 100 ksps data is then filtered and decimated by a cascade of half band filters and decimate by 2 stages. Three stages bring the audio data rate down to 12.5 ksps from the post-demodulation 100 ksps. The first 19-tap half band FIR filter has a cutoff at 16.625 kHz and stopband edge at 33.375 kHz. The second 19-tap half band FIR filter has a cutoff at 8.375 kHz and stopband edge at 16.625 kHz. The third 35-tap half band FIR filter has a cutoff at 5 kHz and stopband edge at 7.5 kHz. A final 16-tap FIR filter is used to cleanup the audio output. This final filter has a cutoff at 3.0 kHz and stopband at 5.0 kHz.

3.5.2.5. Frequency Shift Keying (FSK):

Digital down conversion generates a 50 kcsps output with a passband of ±12.5 kHz and a stopband of ±19.91 kHz. A 23-tap half band FIR filter is used to achieve a ±8.75 kHz passband and ±16.25 stopband (-60 dB). Next, an interpolate by 2 and filter is needed prior to demodulation. A 19-tap half band FIR filter is used to eliminate the replicated component with a ±16.25 kHz passband and ±33.75 stopband (-60 dB).

Demodulation is performed by first removing the carrier by multiplying each sample by the complex conjugate of the previous sample. Next, the derivative of the arc tangent of the complex phase is taken and discretized using first differences with the following equations.

θ k( ) = arctan Q k( ) I k( )( )∂θ∂k

= I k( )2

I k( )2 + Q k( )2 ⋅ 1I k( )

⋅ ∂Q k( )∂k

− Q k( )I k( )2 ⋅ ∂I k( )

∂k

∆θ = I k( ) ⋅ ∆Q k( )− Q k( ) ⋅∆I k( )I k( )2 + Q k( )2

As an FSK signal is a constant modulus, the division is optional. This computes the discrete changes in phase that are required to track the baud rate and baud phase of the FSK signal. Figure 12 shows the delta phase estimate (top curve) verses the instantaneous phase of a 20 kbps CPFSK signal sampled at 100 kcsps (lower curve). A digital phase


24

lock loop uses the delta phase to lock onto the baud rate and baud phase. This information is then used to extract the digital symbols from the downconverted FSK data. The digital bit stream is CVSD decoded to generate audio data. Finally, the audio stream is filtered by a 32-tap FIR filter at the baud rate of the CPFSK signal to cleanup the audio output.

-2.5

-2

-1.5

-1

-0.5

0

0.5

0 0.2 0.4 0.6 0.8 1

Figure 12. Delta Phase Computation Simulation Results

3.6. PC Host, User Interface, Command and Control

The FEAST uses an IBM compatible personal computer (PC) for hosting the DSP card, development tools, and users interface. The primary development environment for the ‘6701 processor is the TI Code Composer Studio. With the complexity of writing and optimizing code for a VLIW, parallel DSP, TI has developed an extended suite of tools to support software conceptualization and design, writing source code, debugging the software and analyzing the performance. With an optimized compiler, DSP/BIOS that provides performance monitoring, and real time data exchange (RTDX) between the DSP and host, the software development for both the real-time software and PC host has the tools needed for success.

On the host platform, an RTDX library operates in conjunction with Code Composer Studio. Display and analysis tools can communicate with RTDX via an easy-to-use COM API to obtain the target data and responses or send commands or data to the DSP application. For a user-friendlier interface, software designers may use standard software display packages, such as National Instruments' LabVIEW, Quinn-Curtis' Real-Time Graphics Tools, or Microsoft Excel. Alternatively, designers can develop their own Visual Basic or Visual C++ applications.


25

4. Detailed Design

The detailed design, component acquisition, assembly, code development and test has been performed with the help, support, and involvement of a number of Western Michigan University students, staff, and faculty. From the concepts presented in Section 3.0, the following Section describes the developed FEAST prototype. A diagram showing the major transceiver subsystems is shown in Fig. 13.

RF to IFReceiver ADC

Custom AD6640 EVM

DigitalDown-

converter

AD6620 EVM

Buffers andCable

Connection

Custom InterfaceTMS320-C6701

DevelopmentBoard

Host PC

DigitalUpconverter and

DAC

AD6622 EVM

IF to RFTransmitter

Custom

Figure 13. FEAST Subsystem Block Diagram

The FEAST systems has been subdivided into basic section: • the RF design, consisting of the RF to IF Receiver and IF to RF transmitter; • the digital logic design, comprised by the Analog Devices evaluation modules

(AD6640, AD6620, and AD6622) and a custom module to provide interfacing; • the firmware design, developing and testing interface software for the ‘6701 to

input and output from the hardware interfaces; and • the software design, involving the development of various signal processing

software for the ‘6701.

The detailed design of each transceiver subsection follows.


26

4.1. RF Design

The receiver and transmitter design have proceeded from the conceptual stage described above through successively iterations based on various design factors to arrive at the prototype design described below. Critical design factors include: the primary operational frequency, selection of preferred intermediate and baseband frequencies, specification of bandpass and lowpass filters and available RF modules and components.

In implementing of a super-heterodyne receiver and transmitter structure, the IF bandpass filter is used to define the available passband characteristics and stopband attenuation. For a wide-band digitized design, a broad passband and steep stopband skirts are required to allow the ADC/DAC to process the widest possible signal bands and avoid signal aliasing. As a result, surface acoustic wave (SAW) filters that can meet these goals were selected. In reviewing SAW manufacturers and device characteristics, a family of standardized center frequency devices with varying bandwidths is available from SAWTEK at two useful IF frequencies, 70 and 140 MHz. To achieve the passband bandwidth desired of approximately 26 MHz, a 70 MHz center frequency filter is not readily available or practical. Therefore, a 140 MHz IF center frequency and appropriate SAW bandpass filter was selected (the SAWTEK 854923). With the IF center frequency defined, the remaining frequency relationships have a limited range of options.

The ADC and DAC sample rates also restrict the receiver design options. Here, ADC sample rates are typically less than available DAC clock rates and thereby define the maximum baseband signal rate, bandwidth, and characteristics of the RF subsystems. Using an Analog Devices AD6640, the maximum clock rate is 65 MHz.

For the receiver, the ADC has an SNR of approximately 68 dB and allows the input signal to have a maximum power between +4 to +10 dBm if the full SNR and system instantaneous dynamic range are to be used. Using these values, computing the thermal noise power in a 26 MHz RF band, and using the receiver noise figure and gains for two similar configurations, the receiver signal and noise thresholds can be plotted as shown in Fig. 14. The first configurations (a) represent a low-noise, high-dynamic range receiver employing maximum signal gain. The second configuration (b) represents the initial test configuration of the receiver (the 4th stage amplifier and output attenuator are removed). With limited RF test equipment and material resources available, the lower receiver gain and smaller maximum signal output level are a precaution against overdriving any components during the development and testing. Once the system (RF, digital , and software) is absolutely stable, the desired receiver configuration will be used.

For the transmitter, the DAC provides an output signal at approximately the level desired, but at the baseband frequency instead of the RF. As a result, the transmitter provides frequency conversion and filtering with little or no gain. The components used are identical to the receiver path, but attenuators are used to limit the gain and provide isolation between the various stages; baseband, IF, and RF.


27

-174 dBm /Hz

-99.85 dBm

+10 dBm

-28.66 dBm

-96.66 dBm

26 MH

z -74.15 dB

Gain

38.66 dBA

DC

SN

R68 dB

-94.64 dBm

NF 5.21 dB

S ignal PowerConsiderations

Noise PowerConsiderations

-174 dBm /Hz

-99.85 dBm

+0 dBm

-24.66 dBm

-92.66 dBm

26 MH

z -74.15 dB

Gain

24.66 dBA

DC

SN

R68 dB

-91.36 dBmN

F 8.49 dB

S ignal PowerConsiderations

Noise PowerConsiderations

+10 dBm

(a) Receiver Design Parameters (b) Receiver Test Parameters

Figure 14. Receiver Signal and Noise Power Levels

4.1.1. ISM Receiver

The receiver provides flexible downconversion for a wide range of RF bands, including the desired ISM band. The detailed receiver design is shown in Fig. 15, and the cascaded gain and noise figure analysis for the receiver is shown in Table 2.

The receiver front-end consists of a custom built preselection filter to isolate the desired RF band, in this case the ISM band and a low-noise amplifier (LNA). A preselector is necessary in order to avoid converting both a high-side and low-side band into the IF filter. For the ISM receiver, the preselector must meet the minimal requirements of filtering out the high-side band (at 1195 +/- 13 MHz). Currently, the tuned local oscillator references into the first mixer is provided by a synthesized signal generator capable of tuning between 200 and 2200 MHz. For the ISM band (902-928 MHz), the LO is set to 1055 MHz. The LNA provides the initial signal gain for the receiver and helps to minimize the additional noise contributed of the receiver to the output signal.


28

Pre-selector

IF Filter

LO

1 2 3 4 5 6

LNA Amp Amp

LO

7

LowpassFilter

Amp

8 9

RF to IF Converter IF Filter IF to BB Converter Antialiasing

Atten.

10

Figure 15. Receiver Processing Stages

Table 2. Receiver Cascaded Gain and Noise Figure

Stage 1 2 3 4 5 6 7 8 9 10

Component Gain -2.00 20.00 -5.90 20.00 -11.33 20.00 -4.78 -11.33 20.00 -6.00Noise FIgure (dB) 2.00 2.90 5.90 5.30 11.33 5.30 4.78 11.33 5.30 6.00

Noise Figure (linear) 1.58 1.95 3.89 3.39 13.58 3.39 3.01 13.58 3.39 3.98

Total Gain (dB) -2.00 18.00 12.10 32.10 20.77 40.77 35.99 24.66 44.66 38.66Total Gain (linear) 0.63 63.10 16.22 1621.81 119.43 11942.63 3972.83 292.55 29254.99 7348.52

Total NF (linear) 1.585 3.090 3.136 3.283 3.291 3.311 3.311 3.314 3.323 3.323Total NF (dB) 2.00 4.90 4.96 5.16 5.17 5.20 5.20 5.20 5.21 5.21


29

After the first mixer, stage four may be used to provide additional gain prior to the IF filter. Removing this amplifiers results in the two receiver configurations previously mentioned. The IF filter defines the receiver passband characteristics. The center frequency is 140 MHz with an insertion loss of 11.329 dB (typical). The filter 1 dB bandwidth is 23.16 MHz (typical) and the 3 dB bandwidth is 24.26 MHz (typical). The SAW filter 35 dB stopband bandwidth is 28.85 MHz (typical) with ultimate attenuation of greater than 50 dB. The passband ripple is 0.56 dB (typical) and phase variation is 6.1 degrees (typical). As a prototype receiver, this is significantly better than most high-volume commercial receivers, but would need to be improved to meet most requirements for commercial test and analysis equipment. Following the IF filter, additional amplification is required due to the high SAW filter insertion loss prior to the second mixer.

The second mixing stage translates the IF band to the receiver baseband for sampling. The receiver baseband is centered at Fs/4 or one-quarter of the ADC sample rate. As shown in Fig. 16 this helps to maximize the usable passband bandwidth by isolating IF filter transition bands to unused spectrum while minimizing any alias components to be less than the IF filter stopband attenuation. A final low pass filter and amplifier removes any mixing products provides both gain and buffering prior to the analog-to-digital converter and digitization.

Fs/2Fs/4 Fs

aliasalias

Passband

Stopband Atten.

Dynam

icR

ange

3Fs/40

Figure 16. ISM Receiver Processing Stages

The receiver parts list of critical RF/IF modules is shown in Table 3. A brief component description, the selected manufacturer, component make, model or part number and cost are shown. Additional cabling, connectors, and miscellaneous devices used will be described later. Of note in this table, the SAWTEK IF filters were provided as samples at no cost to the project, the attenuators were part of a attenuator kit described later, and the preselection filter is a custom LC design built for this project.


30

Table 3. Receiver Parts List and Cost

Component Quantity Type Company Make Model/PN Price1 1 Preselector Custom -$ 2 1 Low Noise Amplifier (LNA) Mini-Circuits ZFL 1000LN 89.95$ 3 1 Mixer Mini-Circuits ZFM 5X 59.95$ 4 1 Low Power Amplifier Mini-Circuits ZFL 500 69.95$ 5 1 IF Filter (BPF) SAWTEK 854923 -$ 6 1 Low Power Amplifier Mini-Circuits ZFL 500 69.95$ 7 1 Mixer Mini-Circuits ZFM 3 61.95$ 8 1 Low Pass Filter Mini-Circuits SLP 30 34.95$ 9 1 Amplifier Mini-Circuits ZFL 500 69.95$

10 1 Attenuator Mini-Curcuits SAT 6 -$ 11 1 Voltage-Controlled Oscillator Mini-Circuits ZOS 200 119.95$

TOTAL COST 576.60$

4.1.2. ISM Transmitter

The transmitter provides upconversion to a range of RF bands, including the desired ISM band. The detailed transmitter design is shown in Fig. 17, and the cascaded gain and noise figure analysis is shown in Table 4.

The transmitter first provides an analog low pass filter to minimize any high frequency components following baseband signal digital-to-analog conversion. A cascaded amplifier and attenuator then provide signal isolation prior to frequency translation to the transmitter IF. The first mixer converts the baseband centered at 16 MHz to 140 MHz using a high-side LO at 156 MHz. An IF filter identical to that of the receiver is used to filter images, the LO feedthrough, and other signal harmonics. After the IF filter, an amplifier and attenuator pair are again used to compensate for the mixing and IF filter losses. In this case, the loss is sufficient to eliminate the 7th stage attenuator. As a note, the amplifiers used have a maximum signal input power 0f +5 dBm; therefore, in the transmitter design every amplifier is followed by an attenuator whether it is installed or not.

The buffered IF signal is converted to the RF frequency by the second mixer. A synthesized RF signal generator provides the fixed LO at 1055 MHz to upconvert to the ISM band. Since a programmable synthesizer has been used, alternate output frequencies can be generated for spectral analysis and non-radiated testing. A custom design RF filter is used to eliminate image bands and harmonics prior to the final amplifier stage. The output amplifier is a conventional low-power amplifier. If higher signal levels are required a pre-amplifier and power amplifier can be added, but for the initial work the available output signal level is sufficient.

The transmitter parts list of critical RF/IF modules is shown in Table 5. A brief component description, the selected manufacturer, component make, model or part number and cost are shown. Of note in this table, the SAWTEK IF filters were provided as samples at no cost to the project, the attenuators were part of a attenuator kit described later, and the RF output filter is a custom LC design built for this project.


31

RF FilterIF Filter

LO

1 2 3 4 5 6

AmpAmp

Tuned LO

7

LowpassFilter

Amp

8 9

BasebandFilter IF FilterBB to IF Converter IF to RF

Atten. Atten.

10

Filtered Preamp Figure 17. ISM Transmitter Processing Stages

Table 4. Transmitter Cascaded Gain and Noise Figure

Stage 1 2 3 4 5 6 7 8 9 10

Gain -2.00 20.00 -20.00 -4.78 -11.33 20.00 0.00 -5.90 -11.33 20.00Noise FIgure (dB) 2.00 5.30 20.00 4.78 11.33 5.30 0.00 5.90 11.33 6.00

Noise Figure (linear) 1.58 3.39 100.00 3.01 13.58 3.39 1.00 3.89 13.58 3.98

Total Gain (dB) -2.00 18.00 -2.00 -6.78 -18.11 1.89 1.89 -4.01 -15.34 4.66Total Gain (linear) 0.631 63.096 0.631 0.210 0.015 1.546 1.546 0.397 0.029 2.925

Total NF (linear) 1.585 5.370 6.939 10.119 70.054 224.584 224.584 226.455 258.120 360.019Total NF (dB) 2.00 7.30 8.41 10.05 18.45 23.51 23.51 23.55 24.12 25.56


32

Table 5. Transmitter Parts List and Cost

Item # Quantity Type Company Make Model/PN Price1 1 Low Pass Filter (LPF) Mini-Curcuits SLP 21.4 34.95$ 2 1 Low Power Amplifier Mini-Circuits ZFL 500 69.95$ 3 1 Attenuator Mini-Curcuits SAT 20 -$ 4 1 Mixer Mini-Curcuits ZFM 3 61.95$ 5 1 IF Filter (BPF) SAWTEK 854923 -$ 6 1 Amplier Mini-Circuits ZFL 500 69.95$ 7 1 Attenuator Mini-Curcuits SAT 6 -$ 8 1 Mixer Mini-Curcuits ZFM 5X 59.95$ 9 1 RF Filter Custom -$

10 1 Amplifier Mini-Curcuits ZFL 1000 79.95$ 11 1 Voltage-Controlled Oscillator Mini-Circuits ZOS 200 119.95$

TOTAL COST 496.65$

4.1.3. Additional RF Considerations

In addition to the RF/IF components and modules previously presented, additional components, cable assemblies, and connectors were purchased to support working on the ISM receiver and transmitter. They are listed with quantities, suppliers, part numbers and pricing in Table 6.

Table 6. Additional RF Components, Cable Assemblies, and Connectors

Item # Quantity Type Company Make Model/PN Price Total Price1 2 High Pass Filter Mini-Circuits SHP 400 38.95$ 77.90$ 2 2 Low Pass Filter Mini-Circuits SLP 21.4 34.95$ 69.90$ 3 1 Attenuator Kit Mini-Circuits K1-SAT 109.95$ 109.95$ 4 2 Splitter Mini-Circuits ZFRSC 2050 59.95$ 119.90$ 5 4 Terminator Mini-Circuits STRM 50 9.45$ 37.80$ 6 10 SMA(M) to SMA(M) Jameco 161293 2.25$ 22.50$ 7 10 SMA(F) to BNC(M) Jameco 153453 2.25$ 22.50$ 8 10 SMA Bulk Head Jameco 153285 2.25$ 22.50$ 9 2 SMA Cable Ass. (0.5 ft.) Jameco CSMA05 169800 3.75$ 7.50$

10 10 SMA Cable Ass. (1 ft.) Jameco CSMA1 163854 3.49$ 34.90$ 11 2 SMA Cable Ass. (2 ft.) Jameco CSMA2 153381 4.25$ 8.50$ 12 2 SMA Cable Ass. (4 ft.) Jameco CSMA4 153390 4.95$ 9.90$ 13 2 SMA Cable Ass. (6 ft.) Jameco CSMA6 159450 5.75$ 11.50$

TOTAL COST 555.25$

As may be expected, the RF electronics are by far the most costly element of this project. The total cost of components is shown in Table 7. This may initially seem excessive, but the RF receiver and transmitter support tremendous flexibility for continued work.

Table 7. Total RF Costs

Item # Type Total Cost1 Receiver 576.60$ 2 Transmitter 496.65$ 3 Misc. RF 555.25$

TOTAL COST 1,628.50$


33

The receiver and transmitter are not frequency specific or confined to a particular modulation type. The receiver/transmitter as wholes can be reused for any RF band or application with minor changes and/or simple filter modifications. Further, each of the receiver and transmitter components can be disconnected and arbitrarily used for other RF or IF applications. The prototype MSGC-FEAST receiver and transmitter, picture in Fig. 18, can and will be used and reused as an indispensable tool for future work.

Figure 18. Prototype FEAST RF Receiver and Transmitter Photo


34

4.2. Digital Design

The FEAST digital signal processing components provide dedicated, programmable hardware processing between the RF and software programmable digital signal processor (pDSP). In the receiver, the dedicated hardware includes the analog-to-digital converter (ADC), the digital downconverter (DDC), and the interface to the DSP development card hosted in a personal computer. For the transmitter, the DSP output is buffered in a custom interface, processed in a programmable multichannel digital up converter (DUC) and converted by a digital-to-analog converter (DAC) into an analog baseband signal.

The principal components are available as evaluation modules from Analog Devices. While a number of manufacturers produce similar parts for performing the digital processing, the components from Analog Devices are state-of-the-art, have matured over multiple generations of devices, and have highly functional evaluation modules for rapid verification and system prototyping. The components and evaluation modules are:

• AD6640 evaluation module, a single board with all necessary components to support the AD6640 12-bit, 65 Msps ADC including a buffered parallel output port and integrated sample rate crystal clock.

• AD6620 evaluation module, a single board that can be directly connected to the AD6640 module with digital buffers, an AD6620 DDC, a FIFO for collecting either raw ADC samples or DDC output samples, and a PC parallel port interface for command, control, and snap shot data transfer to operational software on a PC.

• AD6622 evaluation module, a single board that receives commands and data over a PC communications port from available development software, an AD6622 four-channel DUC, an AD9754 14-bit, 125-Msps DAC, and on board sample rate crystal clock.

4.2.1. Analog-to-Digital Converter

The AD6640 data sheets provides a useful description of the device as follows:

The AD6640 is a high speed, high performance, low power, monolithic 12-bit analog-to-digital converter. All necessary functions, including track-and-hold (T/H) and reference are included on-chip to provide a complete conversion solution.

The AD6640 runs on a single +5 V supply and provides CMOS-compatible digital outputs at 65 MSPS. Specifically designed to address the needs of multichannel, multimode receivers, the AD6640 maintains 80 dB spurious-free dynamic range (SFDR) over a bandwidth of 25 MHz. Noise performance is also exceptional; typical signal-to-noise ratio is 68 dB.

The AD6640 is built on Analog Devices’ high speed complementary bipolar process (XFCB) and uses an innovative multipass architecture. Units are packaged in a 44-terminal Plastic Thin Quad Flatpack (TQFP) specified from –40°C to +85°C. [13].


35

A functional block diagram of the ADC is shown in Fig. 19.

Figure 19. AD6640 Functional Block Diagram [13]

4.2.2. Digital Downconverter

The AD6620 evaluation module block diagram is shown in Fig. 20.

Data Latch

Header

AD6620

Data LatchData Latch

FIFO16k

Inputfrom ADC

Data Latch

Outputto SIO

T ransceiver

PC PrinterPort

Figure 20. Digital Downconverter Module Block Diagram

The module not only provides critical signal processing for the FEAST receiver but initially provided spectrum analysis capability for the integration and test of the FEAST RF receiver subsystem. When combined with the AD6640 ADC module, the “pass-through” mode allows ADC data to be written into the module FIFO. The module development software then reads the FIFO data, performs a Fast-Fourier Transform (FFT), and plots the spectral magnitude result on the controlling PC’s display. A standard PC parallel port cable is used to connect the DDC to a host PC.

Figure 21 shows the ADC and DDC modules connected and ready for performing spectral testing. Figure 22 shows the DDC command and control graphical user’s interface (GUI) and spectral display used to help integrate the RF receiver.


36

Figure 21. ADC and DDC Development Modules Connected for Testing

Figure 22. DDC Development Modules Spectral Display

The AD6620 is a four-stage digital downconverter providing tuning, filtering, decimation, and output formatting for received signal processing. The AD6620 accepts a high input sample rate of up to 67 Msps and provides a numerically controlled oscillator (NCO) with worse case spurs below 100 dBc and tuning resolution of better than 0.02 Hz. Mixing is


37

followed by two separate cascaded integrator-comb filters (CIC), a 2nd order CIC2 with decimation of from 2 to 16 and a 5th order CIC5 with decimation of from 2 to 32. The CIC filters are followed be a programmable coefficient, decimating FIR cleanup filter that can compute up to 134 million taps per second and provide additional decimation of from 1 to 32. An output formatter provides a range of data formats, from serial to parallel for flexible application. The AD6620 is commanded and controlled through either a serial port or generic microprocessor parallel port [14]. A functional block diagram of the DDC, is shown in Fig. 23.

Com plexNCO

CICFilter-

Decim ator

F IRFilter

O utputForm at

RateSettings Coef. RAM Contro l

ADC DataInput

Com plexData

O utput

Program m ing Interface

Figure 23. AD6620 DDC Block Diagram

4.2.3. Digital Upconverter

To generate the baseband signal for ISM transmission , the FEAST transmitter inverts the processing performed in the ADC and DDC using a digital upconverter (DUC) and digital-to-analog converter (DAC). For this project, these components are combined on a single evaluation module from Analog Devices, the AD6622S/PCB. A block diagram of and module is shown in Fig. 24 and a picture of the actual board is shown in Fig. 25. A standard DB9 PC COM port cable is used to connect the DUC to a PC host for command and control.

Data Latch

Header

AD6620

CrystalOscillator

SIO Inputs

ControllerPC Com Port

AD9754

AnalogOutput

Figure 24. Digital Upconverter Module Block Diagram


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Figure 25. Digital Upconverter Module Photograph

The AD6622 data sheets provides a useful description of the device as follows:

The AD6622 comprises four identical digital Transmit Signal Processors (TSPs) complete with synchronization circuitry and cascadable wideband channel summation. An external digital-to-analog converter (DAC) is all that is required to complete a wide band digital up-converter. On-chip tuners allow the relative phase and frequency for each RF carrier to be independently controlled. [16].

The AD6622 DUC, shown in Fig. 26, provides digital transmission signal processing for up to four unique signal channels within a common baseband. The device accepts complex serial data , converts the data to parallel in-phase and quadrature-phase (I and Q) samples, and provides a programmable interpolating FIR filter followed by a CIC filter-interpolator. The interpolated complex output data is then digitally mixed and summed to form the desired wideband digital IF output. The AD6622 forms four distinct transmission streams prior to summing them in the final stage of the device.


39

ComplexNCO

CICFilter-

Interpolate

Interpolat-ing (1-8)FIR Filter

SerialInput

Format

RateSettings

Coef. RAMand RateContro l

Serial Ch A

Outputto DAC

DUC Channel A

Serial Ch BDUC Channel B

Sum

Serial Ch CDUC Channel C

Serial Ch DDUC Channel D

Figure 26. AD6622 DUC Block Diagram

4.2.4. Digital-to-Analog Converter

The AD9752 on the AD6622 evaluation module (shown in the lower right quadrant of Fig. 25) is a high performance DAC with 14-bit resolution and a 125 Msps update rate. The device has excellent spur-free dynamic range, 83 dBc for a 5 MHz output [15]. A functional block diagram of the DAC is shown in Fig. 27.

Figure 27. AD9754 Functional Block Diagram [15]

4.2.5. Digital Interface

The AD6620 and AD6622 are connected to an external interface on the DSP processor module using simple serial connections. A simple proto-board for leaded discrete components was used to connect cables from ports on the DDC, DUC, and DSP boards. Due to the distances between components, SN74ALS541AN buffers were added to insure proper signal levels and isolation.


40

For the DDC, the serial clock (SCLK) output, serial data output (SDO), and the serial data frame sync (SDFS) signals were all connected through cables and buffers to the McBSP1 input port of the ‘C6701 DSP. The DDC uses a standard two-row, 0.100” center connectors that can be easily connected with a ribbon cable to the proto-board. The ‘6701 DSP module uses a 0.050” connector and required a unique connector and cable to the proto-board for interfacing. The cable and connectors to the DSP module consisted of a Samtec FFSD-10-D-32.00-01-N 0.050” cable and a modified Samtec FTSH-140-04-D connector.

For the DUC, serial connections are also used from the DSP to the proto-board (the same cable used for the DDC), the output/input signals are buffered, and then a two-row, 0.100” center ribbon cable goes from the proto-board to the DUC. The DUC can use up to four transmit signal processors using four three-wire interfaces. Each processor has a unique serial clock (SCLK) output, serial data frame sync (SDFS) output, and serial data input (SDIN). With appropriate hardware and software programming, a single serial line may be used to provide all four serial data inputs.

4.2.6. DDC/DUC Development Environment

The evaluation modules from Analog Devices are delivered with a very helpful CD titled “Advanced Signal Processing for Wireless” [8]. It contains a wide range of seminars, applications notes, data sheets, and PC based development software for various evaluation boards. The software folders included for the AD6620 and AD6622 include executable code for board command and control and executable code for the generation of programming values and filter coefficients based on the user specifications.

For the AD6620, the filter generation software includes a “Filter Design Wizard” that walks the user through a set of questions, generates a control file based on the answers, and finally generates various CIC2, CIC5, and FIR filter combinations with spectral plots of the resulting responses. While a useful paper titled “Designing Filters with the AD6620” has been included, the Design Wizard allows a user to rapidly capture the operating state required and review a range of filters based on the allowed decimation per processing stage.

An example filter for FEAST testing has been generated. The MSGC_Ref100 files are based on a 50 MHz ADC sample rate, a 500 kHz output data rate (decimation by 100), a single sided lowpass passband of 100 kHz, and a stopband at 200 kHz. The design wizard provide a range of decimation for the CIC2, CIC5, and FIR. After reviewing the filters, the design with decimation rates per stage of 2, 25, and 2, respectively was used. The following spectral plots, Fig. 28 a and b, shows the resulting composite filter response.


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100 200 300 400 500 600 700 800 900 1000-150

-100

-50

0

10 20 30 40 50 60

-150

-100

-50

0

(a) Transition and Stop Band (b) Passband Figure 28. AD6620 Filter Design Wizard Composite Filter

4.2.7. Digital Design Components and Cost

The components required for digital design were purchased, acquired from WMU ECE Department supplies, or donated by the manufacturer. The costs for the digital electronics is shown in Table 8. The miscellaneous components required for the digital interface were available, except for the unique connectors described that had to be ord3er from Samtek. The evaluation modules were all selected and acquired from Analog Devices and there distributors. While the ADC and DDC modules were purchased, discussions with Analog Devices lead to the donation of the DUC evaluation board. As one of their more recent component and evaluation boards, finding a DUC had been difficult and seemed to be costly. Fortunately, Ms. Leslie Adams, a marketing administrator for Analog Devices’ Wireless Infrastructure Group Digital Radio Systems graciously provide a DUC as a donation.

Table 8. Total Digital Design Component Costs

Item # Type Unit Cost Total Cost1 AD6640S/PCB 150.00$ 150.00$ 2 AD6620S/PCB 500.00$ 500.00$ 3 AD6622S/PCB 500.00$ -$ 4 Misc Cables/Connectors 50.00$ 50.00$

TOTAL COST 650.00$


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4.3. TMS320C6701 DSP Evaluation Module

The TMS320C6701 evaluation module (EVM) is a general-purpose platform for the development, analysis, and testing of digital signal processor (DSP) algorithms and applications. The ’C6701 EVM hardware design and software development environment also provide a reference design that facilitates FEAST rapid prototyping and software radio application code generation. A photograph of the EVM used on this project is shown in Fig. 29.

Figure 29. TI TMS320C6701 Development Module Photo

The EVM contains many useful components and features for FEAST applications. A block diagram of the EVM is shown in Fig. 30.

Specific features include: • The Advanced TMS320C6701 VLIW DSP processor; • PCI Interface for allowing the PC host and development environment access to

the EVM and DSP; • External Board Memory for code and data, two banks of 1M x 32-bit SDRAM, • Memory Expansion Interface to provide additional storage as needed; • Audio Interface using a modern Codec with interfaces for a microphone, analog

line input, and an analog line output; • Peripheral Expansion Interface to provide board and processor interfaces for

external boards, daughterboards, or other circuitry; • Integrated Voltage Regulation to provide appropriate voltages and power to the

DSP and EVM circuitry; and • TI Code Composer Studio software development environment and tools.


43

Figure 30. TMS320C6701 DSP Evaluation Card Block Diagram [17]

For hardware connection, the FEAST makes direct use of the expansion peripheral interface and the Multi-Channel Buffered Serial Port number 1 (McBSP1) that is directly connected to the interface. Both the DDC and DUC data can be transferred using a serial format that can be read and written by McBSP1. In addition, the McBSP0 port connection to an audio codec allows the microphone input and audio line out to provide audio signal inputs and output to a speaker.

For software consideration, the Code Composer Studio software tools and capability have been a great help in FEAST development. A block diagramming showing the host support software available is shown in Fig. 31. Of particular help have been the software tutorials, user’s code, and wide range of C programming examples available. Standard practice for starting with the EVM consists of running the tutorials, reading the user’s and reference guides on DSP/BIOS, and then loading and executing an audio codec input to output example provided. The audio example was particularly useful as it defined the initialization necessary to operate the EVM, McBSP0 port, and codec, provide an


44

explanation and code for both hardware and software interrupts, and resulted in an audio waveform generated input being collected and sent back out the line-out port to a speaker.

Figure 31. TI320C6701 Host Support Software Block Diagram [17]

4.4. Firmware Design

Whenever a processor is used to interact with a real-time environment and/or various signal sensors, critical software is required to facilitate communications. For the FEAST project, firmware is used for initializing the DSP EVM, initializing and configuring the DSP interfaces and peripherals devices needed, and providing the low level hardware service routines. The FEAST processing requires firmware programming for the following devices and peripherals;

• EVM Codec and CPLD, • Multi-Channel buffered Serial Port 0 (McBSP0) connected to the codec, • McBSP1 connected to the DDC and DUC through the EVM external interface, • Direct Memory Access processor 0 (DMA0) for McBSP0 data transfer to on-chip

memory , and • DMA2 for McBSP1 on-chip[ data transfers.

4.4.1. Multi-Channel Buffered Serial Port (McBSP)

The basic architecture of a McBSP port is shown in Fig. 32. For the Multi-channel buffered serial port operation, the registers shown that control the functionality must be addressed and initialized. Both McBSP0 and McBSP1 are required to support full FEAST operation, McBSP1 to input data from the DDC and output data to the DUC and McBSP0 to provide audio input and output through the EVM coder-decoder (codec). The EVM codec line-in and line-out lines are used to input test tones from an audio waveform generator and output audio to a set of stereo speakers.


45

Figure 32. McBSP and Control Registers [19]

Proper configuration of each McBSP requires programming the 32-bit serial port control register (SPCR) and the pin control register (PCR). Next, the appropriate receive and transmit control registers (RCR and XCR) must be configured based on the test and/or application. A complete list of the McBSP register is shown in Table 9.

4.4.1.1. McBSP Receive

To receive complex serial data from the DDC, the McBSP firmware must perform the following functions. First, data from the Digital Down Converter (DDC) is received on the DR pin of the McBSP. The data is then shifted into the Receive Shift Register (RSR) on every receive clock (CLKR). The actual shifting does not begin until after the detection of a receive frame sync (FSR), which is also supplied by the Digital Down Converter. The data in the RSR was then copied to a Receive Buffer Register (RBR) and finally to the Data Receive Register (DRR) This allowed the CPU or DMA to read the DRR.

4.4.1.2. McBSP Transmit

The register of the McBSP must also be initialized to allow transmitting. The transmitter section is responsible for the serial transmission of data written in the Data Transmit


46

Register (DXR). The contents of DXR were copied to the transmit shift register (XSR). The transfer occurred as soon as the transmit frame sync (FSX) is detected. One bit of data is transmitted out of XSR on every transmit clock (CLKX). New data is written into the DXR directly by the CPU or under DMA control.

Table 9. McBSP Register Names and Addresses McBSP 0 McBSP 1 Name McBSP Register Name

– – RBR Receive buffer register

– – RSR Receive shift register

– – XSR Transmit shift register

018C 0000 0190 0000 DRR Data receive register ‡¶

018C 0004 0190 0004 DXR Data transmit register #

018C 0008 0190 0008 SPCR Serial port control register

018C 000C 0190 000C RCR Receive control register

018C 0010 0190 0010 XCR Transmit control register

018C 0014 0190 0014 SRGR Sample rate generator register

018C 0018 0190 0018 MCR Multichannel control register

018C 001C 0190 001C RCER Receive channel enable register

018C 0020 0190 0020 XCER Transmit channel enable register

018C 0024 0190 0024 PCR Pin control register

4.4.2. Direct Memory Access (DMA)

The Direct Memory Access (DMA) processors facilitate data movement between on-chip memory buffers and the McBSP peripherals. As in the McBSP, the DMA must be initialized by firmware before it can get the data from the source and store it in the destination. The internal DSP interconnection of the DMA is shown in Fig. 33.

Figure 33. DMA Controller Interconnection within the ‘C6701[19]


47

Before data is received or transmitted, the DMA source and destination addresses are defined and the size of the block to be processed is defined and preferably held constant for FEAST applications. Received data from the McBSP DDR are stored in a buffer that is equal to the block size defined. Once the data is stored it may be processed demodulated or modulated. The processed data is then stored in another buffer, which had the same size as the receive buffer. The DMA then reads the transmit data and places it into the McBSP DXR. The FEAST uses two DMA processes, one for the audio input and output through the Codec and the second for baseband data to the DUC or from the DDC. The DMA memory map for command, control and status registers resides from 01840000hex to 01840073hex. The Addresses and register definitions are shown in Table 10. A complete description can be obtained from the TMS320C6000 Peripheral Reference Guide [19].

Table 10. DMA Command and Control Register Assignments Address DMA Register Name

0184 0000 DMA channel 0 primary control


0184 0008 DMA channel 0 secondary control

0184 000C DMA channel 2 secondary control

0184 0010 DMA channel 0 source address


0184 0018 DMA channel 0 destination address

0184 001C DMA channel 2 destination address

0184 0020 DMA channel 0 transfer counter


0184 0028 DMA global count reload register A

0184 002C DMA global count reload register B

0184 0030 DMA global index register A

0184 0034 DMA global index register B

0184 0038 DMA global address register A

0184 003C DMA global address register B



0184 0048 DMA channel 1 secondary control

0184 004C DMA channel 3 secondary control



0184 0058 DMA channel 1 destination address

0184 005C DMA channel 3 destination address



0184 0068 DMA global address register C

0184 006C DMA global address register D

0184 0070 DMA auxiliary control register


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4.4.3. TI Supporting Documents

Texas Instruments has a vested interest in supporting the TMS320C6701 user community through the Code Composer Studio, supporting user’s guides and reference manuals, and a wide range of application notes and description. Firmware for execution on the ‘C6701 was developed with the above concepts and support of many of the documents listed in Table 11 available directly from Texas Instruments web site at www.ti.com.

Table 11. TI Development Support Literature spra291 Implementing Fast Fourier Transform

Algorithms of Real-Valued Sequences with the TMS320 DSP Family

spra297 EXTENDED PRECISION RADIX-4 FAST FOURIER TRANSFORM IMPLEMENTED ON THE TMS320C62XX

spra477 TMS320C6000 McBSP Interface to the CS4231A Multimedia Audio Codec

spra478 INTERFACING A DAUGHTERBOARD TO THE TMS320C6201 EVM

spra488 TMS320C6000 MCBSP INITIALIZATION

spra491A TMS320C6000 MCBSP AS A TDM HIGHWAY

spra515 UNDERSTANDING TMS320C62XX DSP SINGLE-PRECISION FLOATING-POINT FUNCTIONS

spra529 TMS320C6000 DMA APPLICATIONS spra551 TMS320C6000 MCBSP: DATA

PACKING (w/ DMA) spra559a A Multichannel Serial Port Driver Using

DMA on the TMS320C6000 DSP spra591 DSP/BIOS By Degrees: Using

DSP/BIOS Features in an Existing Application

spra598 AN AUDIO EXAMPLE USING DSP/BIOS

spra614a TMS320C620x/TMS3206701 DMA and CPU: Data Access Performance

spra630 TMS320C6000 Memory Test spra636 TMS320C6000 Enhanced DMA:

Example Applications spra640 Programming and Debugging Tips for

DSP/BIOS spra646 DSP/BIOS II Technical Overview spra648 Understanding the Functional

Enhancements of DSP/BIOS II and Their Utilization

spra653 Understanding Basic DSP/BIOS Features

spra654 AUTO-SCALING RADIX-4 FFT FOR TMS320C6000 DSP

spra675 Upgrading to DSP/BIOS II spra697 How to Get Started With DSP/BIOS II sprs051f Datasheet: TMS320C6201, FIXED-

POINT DIGITAL SIGNAL

PROCESSOR sprs067e Datasheet: TMS320C6701,

FLOATING-POINT DIGITAL SIGNAL PROCESSOR

spru186e TMS320C6000 Assembly Language Tools User’s Guide

spru187e TMS320C6000 Optimizing C Compiler User’s Guide

spru188d TMS320C6x C Source Debugger User’s Guide

spru189e TMS320C6000 CPU and Instruction Set Reference Guide

spru190c TMS320C6000 Peripherals Reference Guide

spru197d TMS320C6000 Technical Brief spru198d TMS320C6000 Programmer’s Guide spru224 TMS320C6x C Source Debugger For

SPARCstations spru269d TMS320C6201/6701 Evaluation

Module User’s Guide spru273b TMS320C6x Peripheral Support Library

Programmer’s Reference spru301c Code Composer Studio Tutorial spru303b TMS320C6000 DSP/BIOS User’s

Guide spru305 TMS320C6201/6701 Evaluation

Module Technical Reference spru313 Code Composer Studio: Quick Start

Reference Guide spru328 Code Composer Studio User’s Guide spru313 Code Composer Studio Quick Start

Reference spru356 Code Composer Studio: Quick Start

Guide spru360b TMS320 DSP Algorithm Standard API

Reference spru403a TMS320C6000 DSP/BIOS Application

Programming Interface (API) Ref Guide spru424 TMS320 DSP Standard Algorithm

Developer's Guide

http://www.ti.com/


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4.5. Software Design

The FEAST firmware and software code is partitioned between initialization and setup code, time critical interrupt service routines (ISRs) and an infinite main processing loop that calls various processing functions as flags are set by the ISRs. While the firmware addresses initialization, setup, and hardware peripheral interactions, the operating software must execute real-time processing, system operation and health monitoring, and support user commands, control, and status. A block diagram of the FEAST from an embedded software perspective is shown in Fig. 34.

AudioLine-In

AudioLine-Out

Audio Codec

DDR DXR

DMA0

McBSP0Serial Port

AudioDMA ISR

ReceiverDDC Output

TransmitDUC Input

DDR DXR

DMA1

McBSP1Serial Port

BasebandDMA ISR

Demodulation

Audio InMemory

Audio OutMemory

BasebandIn

Memory

BasebandOut

Memory

ModulationCommandand Control

Display andStatus

Main Program Loop Routines

W atch DogTimeout

W atchDog ISR

Figure 34. FEAST Software Processing Block Diagram

Critical software components include interrupt service routines for: Audio DMA data transfer completion (Audio DMA ISR), transceiver baseband DMA data transfer completion (Baseband DMA ISR) and watch dog timeout (Watch Dog ISR). principal software processing code residing in the main program loop include: the modulation of audio input for baseband transmitter output (Modulation), the demodulation of baseband


50

receiver input into audio output (Demodulation), the processing of user command and control operations (Command and Control), the periodic output of system status and user display data (Display and Status), and, finally, the error and recovery processing performed when a watch dog interrupt occurs (Watch Dog Timeout).

The following subsections will briefly describe the software development methodology and flow and the critical code components.

4.5.1. Software Development Flow

The TI ‘C6701 is a VLIW processor with up to eight parallel operations occurring on each clock cycle. This makes software programming of the DSP quite a challenge. Fortunately, TI has attempted to address this problem by creating useful compilation and code optimization software. They have also developed a suggested code development flow which is shown in Fig. 35 and described in Table 12 [20].

Figure 35. TI ‘6701 Suggested Software Development Flow[20]


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Table 12. Software Development Flow Description [20] Phase Goal

1 You can develop your C code for phase 1 without any knowledge of the ’C6000. Use the ’C6000 profiling tools that are described in the Code Composer Studio User’s Guide to identify any inefficient areas that you might have in your C code. To improve the performance of your code, proceed to phase 2.

2 Use the intrinsics, shell options, and techniques that are described in this book to improve your C code. Use the ’C6000 profiling tools to check its performance. If your code is still not as efficient as you would like it to be, proceed to phase 3.

3 Extract the time-critical areas from your C code and rewrite the code in linear assembly. You can use the assembly optimizer to optimize this code.

4.5.2. Real-Time Signal Processing

The real-time processing software is based on Interrupt Service Routines (ISR). When a DMA interrupt occurs it indicates that either a DMA input buffer is available for processing or that a DMA output buffer requires additional, processed data. When the ISR occurs, an appropriate processing flag is set. The program main loop uses a prioritized scheme to then execute code associated with each flag. The prioritization for FEAST is based on maintaining real-time, continuous data streams for receiving and transmitting. Top priority is given to output data streams to insure that are never empty. Second priority is to incoming data to insure that data can never be over-written by subsequent samples. The next highest priorities are for command and control operations and then display and status. The watch dog ISR indicates that a system error or problem has occurred. As a result, it functions as a non-maskable interrupt (NMI) that would suspend system execution or initiate a recovery routine.

The detailed design to generate software code components that can be integrated into a fully operation transceiver is ongoing. Currently, code development has focused on firmware, the input and output of raw data, and the analysis of received data signals. This area of development is incomplete and remains for future work.

4.5.3. Personal Computer Host

User command, control and status software for the FEAST is hosted on a personal computer with an installed ‘C6701 EVM. Originally, the development of a flexible GUI and interface to the other FEAST components was envisioned. While acquiring and performing initial test and evaluation of the various evaluation boards, each module came with functional command, control, status, and monitoring software. In all cases the software proved invaluable in learning about the modules but the programs were also completely independent of each other and were not delivered with source code. The independence of the code even extends to the hardware interfaces employed; the ‘C6701 is accessed through the PCI and internal EVM, the DDC is accessed using the parallel printer port, and the DUC is accessed through a COM port


52

The TI DSP/BIOS environment provides for the development and integration of custom application programming interfaces (APIs). Therefore, it is possible to develop custom host software to integrate all of the operational modules and interfaces. This would entail significant software code design, development, integration, and test time. As a further concern, the near term goals of this task would be to recreate what the current software already does. Since the goal of this work is to develop a prototype transceiver able to support the investigation of new, broader capabilities, the reverse engineering and duplication of effort software was not pursued. As a result, no work on a GUI or user interfaces has been performed beyond familiarization with the tools/programs already available. A brief description of the DDC and DUC operational software follows.

4.5.3.1. AD6620 DDC

The AD6620 evaluation board is delivered with operational software. In addition, a filter development program with “smart” programming capability is included. For a known application, the user begins by executing the filter generation program. Executing the design wizard walks the user through a set of questions, including the data sample rate, the desired decimation rate, the number of filter regions to specify, the region frequency bounds, and the region attenuation. The program records the basic programming and then generates various filters that meet the criteria defined (if possible). By selecting decimation combinations with valid filters, the user can quickly review a range of options and then store a selected configuration. Next, the AD6620 operational program is executed. The AD6620 software is then used to command, control, and display sampled data spectrum for the evaluation module. The control and monitoring GUIs are shown in Fig. 36.

Figure 36. AD6620 Board Command and Control GUI [21]


53

When the operational code is executed, it verifies the presence of the AD6620 and establishes communication. Next, a selected controller configuration must be loaded and “tuned” into the device. The AD6620 monitor is used to select a particular setup. Among the selections is whether data is taken from the raw digital input or after processing by the DDC. Once the setup is complete, the user can select a single scan (fill the on-board FIFO, stop, and display the resulting spectrum), continuous operation (continuing periodic FIFO snap shots, FFTs, and new spectral displays), or sweep (continuous sweeping of the DDC internal oscillator across a predefined frequency range with snap shots and spectral result plotting). Two examples of continuous DDC spectral plots are shown in the Test and Verification Section. The first plot, Fig. 38, shows the FFT of digitally sampled ADC inputs from signals in the cellular telephone band around 860 MHz. The second plot, Fig. 39, shows the spectrum for signals in the ISM band centered at 915 MHz.

4.5.3.2. AD6622 DUC

The AD6622 evaluation board software provides command and control, but does not capture or display data. As before, filter generation software is available to provide appropriate programming and filter coefficients. The GUI is shown in Fig. 37.

Figure 37. AD6622 Board Command and Control GUI [22]


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5. Test and Verification

The FEAST program entails the development and integration of a number of critical pieces. The tasks were partitioned so that different students with the principal investigator could work on somewhat independent parts of the whole. While excellent progress was accomplished on every piece, the overall integration and full operation of the FEAST transceiver has not yet been accomplished. The following accomplishments and results have been achieved.

5.1. RF Receiver and Transmitter

The FEAST receiver and transmitter have been built and tested. Using the AD6640 ADC module, AD6620 module, and PC host with software, a snap shot spectrum analyzer was available for testing along with a 100 MHz oscilloscope, a 0.1 to 990 MHz synthesized signal generator, and an audio waveform generator. With such limited resources, the receiver was methodically constructed and tested from the baseband output to the IF section and finally the RF front-end. Once the receiver path was constructed and operationally verified, construction of the transmitter began.

In constructing the transmitter elements, the concept of looping signals back through the receiver was used. First, the baseband conversion to IF was tested by feeding the output of the waveform generator to the transmitter baseband input, upconverting to the IF and then looping the IF back through the receiver. The IF filter was identical to that of the received path, so testing by substitution was performed. The RF testing was again performed by looping back the resulting RF output (with sufficient attenuation) to the RF input while using a splitter on the output of the synthesized signal generator to create the RF oscillators required by both transmit and receive paths. With careful thought, the analysis of many partial receiver and transmitter configurations, and the available test equipment, the RF receiver and transmitter were completed.

Since the initial construction and verification of the RF designs, BAE systems has donated additional RF test equipment, an RF spectrum analyzer and a second RF synthesized signal generator. With a true RF spectrum analyzer and two signal sources further work on these designs has been greatly simplified.

5.2. ADC and DDC

The AD6640 and AD6620 were the first evaluation modules and/or components acquired for the FEAST program. With the direct connection of the two boards, addition of a crystal oscillator sampling rate clock, and an available PC, validation of simple spectral analyzer was easily accomplished. A simple audio waveform generator was used to provide an analog input to the ADC. By executing the AD6622 development software, a continuous spectrum of the raw data or DDC processed data could be observed and verified.


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Once the RF receiver was completed, further verification was performed. By tuning the receiver to a frequency band of interest (e.g. 860 MHz cellular telephone or 915 MHz ISM band), the local spectrum could be observed. Two such collections are shown in Fig. 38 and Fig. 39. In Fig. 38, the spectral plot shows spectral activity centered around 860 MHz, a frequency band assigned for cellular telephone services. The second plot, Fig. 39, shows the spectrum for signals in the ISM band centered at 915 MHz.

Figure 38. Spectral Snap Shot Centered at 860 MHz (Cellular Telephone)

5.3. DSP

The TMS320C6701 EVM has available when the program started. Familiarization with the Code Composer software development environment and EVM hardware capability was a necessary step by everyone interested in the embedded firmware and software.

A standard methodology for working with the EVM has been used. Initially, a tutorial for the Code Composer Studio is available [23]. After executing all the sections, a greater understanding of writing software for real-time operations is needed. Texas Instruments has composed a number of application notes and user’s guides on their DSP/BIOS and DSP/BIOS II. How to Get Started With DSP/BIOS II (spra697.pdf), Understanding Basic DSP/BIOS Features (spra653.pdf), and TMS320C6000 DSP/BIOS User’s Guide (spru303b.pdf) are particularly helpful.


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Figure 39. Spectral Snap Shot Centered at 915 MHz RF Band (ISM)

After gaining and understanding of how to partition and develop the software an actual audio example is provided. An Audio Example Using DSP/BIOS (spra598.pdf) is a coding example of using the EVM’s Codec to collect, store, transfer, and output an audio signal . By providing an analog source to the EVM line-in (audio waveform generator) and connecting speakers to the line-out, audio signals or music can be “played” through the DSP.

The next step is to make the data collection, transfer, and output more efficient. The audio example uses CPU interrupts to move data around. By using internal DMA processors, the data movement tasks can be removed from the CPU. A Multichannel Serial Port Driver Using DMA on the TMS320C6000 DSP (spra559a.pdf) and DSP/BIOS by Degrees: Using DSP/BIOS Features in an Existing Application (spra591a.pdf) provide information for implementing DMA transfers.

This code has been developed for the FEAST. To date, the receipt and buffering of valid DDC data has been accomplished, but no further software has been completed.

5.4. DUC and DAC

The AD6622 evaluation module was the last component focused on in the development. Rudimentary operations was verified using the available filter generation software and


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controller software. A simple AM filter was designed for one of the DUC channels and loaded into the device. Digital input data was provided to the channel and the converted analog output was observed using the ADC and DDC. Additional testing will be performed once modulation software has been developed.

6. Key Contributors

The Michigan Space Grant Consortium, with the awarding of a seed grant , has set the foundation for this and continuing efforts. As work has progressed, a number of individuals have been recruited and have contributed to performing the design and development tasks. Additional support has also been received in the form of material donations and grants either directly to the principal investigator and project or through other WMU faculty. The following briefly describes these important contributions.

6.1. Principal Investigator

Dr. Bradley J. Bazuin is the principal investigator for the project. He is an assistant professor who recently (Jan. 2000) joined Western Michigan University’s Electrical and Computer Engineering (ECE) Department. Dr. Bazuin completed his Ph.D. work in the Center for Integrated Systems at Stanford University in 1989. Dr. Bazuin has entered the academic community following 19 years of full- and part-time industrial experience, developing commercial and military communication components, processors, and systems. He was employed for over 10 years (6/81-12/91) by ARGOSystems, Inc., which became a wholly owned subsidiary of The Boeing Company during his tenure, and for over eight years (12/91-7/00) by Radix Technologies, Inc..

6.2. Staff, Student Involvement

The principal FEAST research team consists of three undergraduates: Mr. Jonathan Barber, Mr. Cazzie Williams, and Mr. Garett Spalo. These students have taken on the wide range of tasks and roles required to complete the first FEAST prototype. These tasks include: the RF and analog receiver designs, the real-time hardware digital signal processing, the interfacing of hardware processing to the selected programmable digital signal processor, the generation of real-time processing software, and the design of embedded software for performing command, control, and operational displays. Mr. Williams performed the RF receiver and transmitter development, Mr. Spalo was responsible for the digital hardware and digital interfaces, and Mr. Barber developed firmware and software and has been involved in this project since it’s inception.

6.3. Funding Support

This research is supported by a combination of Michigan Space Grant Consortium (MSGC) Research Seed Grant funding, matching funds from the WMU ECE department, and indirect cost funding from the WMU Research Office.


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The MSGC has provide the nucleus for beginning this effort. Without their support this work would not have been possible. The matching and indirect cost support provided by WMU and the ECE department are greatly appreciated.

6.4. Additional Support and Donations

The WMU ECE department and chairperson, Dr. Hossein Mousavinezhad, have provided space and resources for this work. Beyond matching funds, the technical support from Mr. David Florida and the access to critical test equipment have allowed work to progress.

After e-mailing the Wireless Infrastructure Group of Analog Devices, Ms. Leslie Adams, a marketing administrator for Digital Radio Systems, arranged the gracious donation of an AD6622S/PCB evaluation module to the project. This key component provides the hardware digital upconverter and DAC for the transmit processing.

Dr. H. Mousavinezhad and Dr. Abdel-Qader of the WMU ECE department through a grant made available a complete TMS320C6701 development station, including a PC, TI tools and a development card. Without these resources, the DSP processing and software development would have been greatly restricted and significantly more challenging. Partial support for these components was provided by the National Science Foundation’s Course, Curriculum and Laboratory Improvement Program under grant DUE- 9952512 and from Texas Instruments.

The BAE Systems division in Gaithersburg, Maryland (formerly a division Watkins-Johnson) has donated an RF spectrum analyzer and synthesized RF signal generator. Mr. Mike Cholewczynski of BAE Systems graciously located this equipment and arranged for this donation after interviewing one of the undergraduates working on the project, Mr. Cazzie Williams, and having further discussions of the work with Dr. Bazuin.

The interest and support of the WMU MSGC representative, Dr. Frank Severance, has been instrumental in developing the initial seed grant proposal and becoming more involved with the MSGC. His enthusiasm and encouragement are a great help.


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7. Summary

The FEAST MSGC seed grant project has made steady progress since getting underway in August 2000. The project goal of developing the first generation FEAST prototype, the flexible, electrical and software programmable transceiver, has nearly been accomplished. The components, modules, evaluation boards, subsystems, and code completed provide tremendous resources for continued work in this area and have expanded the teaching and research opportunities at Western Michigan University.

The project has provided new contacts to commercial industry, facilitating both discussions with and equipment donations from both Analog Devices and BAE Systems. This work has provided a foundation and catalyst for additional funding opportunities and grant proposals. The first of which is expected to be a proposal to the Army Research Office under the Defense University Research Instrumentation Program.

The students working on this project have been inspired by the technologies and their ability to contribute and perform state-of-the-art development. An added benefit to the graduating undergraduates has been the interest and job interviews from a range of commercial companies, including BAE Systems, Motorola, Intel, Lucent, and Raytheon. The interest, acceptance and support of industry has been particularly gratifying.

The following sections provide a more detailed enumeration and description of the FEAST progress to date.

7.1. Progress

Significant progress has been made in all areas of the program, with the following specific accomplishments:

• Soliciting and finding student support – Three undergraduates have been working on the project during the entire

Fall 2000 semester and will be continuing for the Winter 2001 semester. In addition, they used the FEAST development work for their senior project in ECE 481 and ECE 482.

– Two additional undergraduates have been developing all-software base digital downconversion and a uniform filter-bank analysis capability.

– One graduate student is starting Master’s Thesis studies based on the FEAST architecture for the Fall 2001 semester.

– Additional work at WMU that is beneficial to these efforts is being performed by graduate students under the direction of Dr. Abdel Qader. They are developing a range of DSP processes for the TMS320C6701.

• Selecting and acquiring evaluation modules and a DSP development card – The receiver ADC and DDC evaluation modules have been purchased

using ECE department matching funds from analog devices.


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– A complete TI TMS320C6701 development station, including the internal PC PCI bus card, has been made available by Dr. Qader and Dr. Mousavinezhad of the WMU ECE department.

– The transmitter DUC evaluation module with a DAC has been donated to this research by Analog Devices’ Digital Radio Systems.

• RF design of the FEAST receiver and transmitter – The receiver and transmitter have been successfully completed. – The electronics use a synthesized signal generator to provide the RF to IF

conversion local oscillator. As a result, any frequency bands from 200 kHz to 1000 MHz can be have signals transmitted and/or received.

– The receiver has completed loop-back test and verification in the desired ISM RF band from 902 to 928 MHz.

• Critical component verification – The ADC and DDC modules have been independently tested using tools

provide with the purchased components. The ADC and DDC have also been integrated and verified.

– The ‘6701 development station and card have been tested and verified. Functional testing used software available with the development station to verify the Codec and processor operation by inputting the signal from a waveform generator and then both observing and listening to the output with an oscilloscope and speakers.

– The DUC module has also been tested using tools provide with the donated components. Simple test tones have been generated, transmitted and received in combination with for RF loop-back testing.

• Digital interface design and development – The digital interface between the DDC and DSP and the DSP and DUC

has been built, tested, and verified. A proto-board contains all required buffers and connectors required for prototype operation.

• Software design and development – The code composer development tools have been extensively studied and

used. The complete set of tutorials have been coded, executed and debugged. Within this software set are all the initialization code for the McBSP ports and Codec.

– All required initialization software and firmware has been coded, executed, and verified. Routines are available for all EVM hardware and the necessary ‘C6701 peripherals.

– Software components have been developed or are available for performing baseband mixing, signal filtering, and FFT spectral analysis with programmable windowing.


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7.2. Conclusion

The FEAST project has provided an excellent focus for a new area of research in the Electrical and Computer Engineering Department of Western Michigan University. The interest and involvement of undergraduate and graduate students has been gratifying. With an understanding of the basic fundamentals behind the technology required to develop the FEAST, the students have made significant efforts to grasp new concepts, learn about specific technical areas, and go beyond the bounds of their class work. As added benefits, they have already had higher expectations and grades in courses related to the project and received a number of job interviews from companies and departments specifically involved in technologies related to the FEAST.

The FEAST project has already become a teaching example for undergraduate and graduate classes. Dr. Bazuin has made reference to this work in all his courses; Computer Architecture (ECE 357) and Linear Systems (ECE 371) for undergraduate students and Advanced Computer Architectures: Parallel Processing (ECE 650) and Design Factors for Distributed Systems (ECE 680) for graduate students. In his current course, Time-Varying Fields in Communications (ECE560), Dr. Bazuin has used the FEAST receiver architecture as classroom material and a homework assignment. The receiver has also been used for class demonstrations and is available for independent, hands-on operation and testing to the ECE560 students. Student feedback has been positive with numerous inquiries about supporting Master Degree research and thesis work and the addition of new courses. The access and application of state-of-the-art techniques and components to wireless communications has and will continue to motivate students.

The initial and future FEAST prototypes lend themselves to a wide range of applicable research and development. For NASA satellite and aerospace communication, all-digital, software based, reprogrammable transceivers can provide tremendous benefits. Multiple common devices can provide increased redundancy with higher reliability at reduced size, weight and power. The FEAST flexible also provides for software reprogramming and upgrades. This allows simple upgrades to processing algorithms, addition of new features, the incorporation of new modulation techniques, and the optimization of the available resources.

The FEAST architecture readily lends itself to the analysis of emerging signal formats, particularly 3rd and 4th generation cellular communications. Using all-digital processing, the waveforms structure and modulation and demodulation techniques can be evaluated and optimized. This flexibility also supports the creation of new waveforms. Hybrid signals simultaneously employing time, spectral, and spatial processing techniques may provide the next great advancement in wireless communications.

As a final direction for research, spatial beamforming (smart antenna) research and implementations can be developed using multi-element array antennas and a parallel array of FEAST with cross connected DPS communications. For wireless communications, beamforming promises significantly higher network capacities and robustness.


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8. References

[1] Stark, H. and Tuteur, F.B., Modern Electrical Communications, Prentice-Hall, 1979.

[2] Gagliardi, R., Introduction to Communication Engineering, 1978.

[3] Carlson, A.B., Communication Systems, 3rd ed., McGraw-Hill, 1986.

[4] Proakis, J., Digital Communications, McGraw-Hill, 2001.

[5] Crochiere, R.E. and Rabiner, L.R., "Multirate Digital Signal Processing," Prentice-Hall, Inc., Englewood Cliffs, NJ, 1983, Chapter 7.

[6] Vaidyanathan, P.P., "Multirate Systems and Filter Banks," Prentice-Hall, Inc., Englewood Cliffs, NJ, 1993, Chapters 5-9.

[7] Hogenauer, E.B., “An Economical Class of Digital Filters for Decimation and Interpolation,” IEEE Transactions on Acoustics, Speech, and Signal Processing, Volume ASSP-29, Number 2, April 1981.

[8] Analog Devices, Advanced Signal Processing for Wireless, CD #ADV-SIG-PROC-DISK, Analog Devices, Fall, 2000.

[9] Texas Instruments, Code Composer Studio User’s Guide, spru328, May 1999.

[10] Texas Instruments, Code Composer Studio Tutorial, spru301c, Feb. 2000.

[11] Texas Instruments, TMS320C6201/6701 Evaluation Module Technical Reference, spru305, Dec. 1998.

[12] Texas Instruments, TMS320C6201/6701 Evaluation Module User’s Guide, spru269d, Dec. 1998.

[13] Analog Devices, AD6640 Data Sheet, AD6640.pdf available at www.analog.com, Rev. 0, 1998.

[14] Analog Devices, AD6620 Data Sheet, AD6620.pdf available at www.analog.com, Rev. A, 2000.

[15] Analog Devices, AD9754 Data Sheet, AD9754.pdf available at www.analog.com, Rev. A, 1999.

[16] Analog Devices, AD6622 Data Sheet, AD6622.pdf available at www.analog.com, Rev. 0, 2000.

[17] Texas Instruments, TMS320C6201/6701 Evaluation Module User’s Guide, spru269d.pdf available at www.ti.com, Rev. D, 1998.

[18] Texas Instruments, TMS320C6201/6701 Evaluation Module Technical Reference, spru305.pdf available at www.ti.com, Rev. D, 1998.

http://www.analog.com/




http://www.ti.com/

http://www.ti.com/


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[19] Texas Instruments, TMS320C6000 Peripherals Reference Guide, spru190c.pdf available at www.ti.com, Rev. C, April 1999.

[20] Texas Instruments, TMS320C6000 Programmer’s Guide, spru198d.pdf available at www.ti.com, Rev. D, March 2000.

[21] Analog Devices, AD6620 Evaluation Board Manual, AD6622evb.pdf available at www.analog.com, Rev. 2.10, 27 April, 2000.

[22] Analog Devices, AD6622 Evaluation Board Manual, AD6622 Manual.pdf available at www.analog.com.

[23] Texas Instruments, TMS320C6000 Code Composer Studio Tutorial, spru301c.pdf available at www.ti.com, Rev. C, 2000.

http://www.ti.com/

http://www.ti.com/



http://www.ti.com/