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DVClub Bristol 22-April-2009

The Verification Methodology Landscape

Jonathan Bromley, Doulos1Copyright 2008 by Doulos. All rights reserved.

The Verification Methodology Landscape

CONTENTS The M-word Languages, methodologies, tools and standards The big players: OVM, VMM, eRM

Interoperability and convergenceConclusions?2Copyright 2008 by Doulos. All rights reserved.

Verification Environment

Coverage collector

Scoreboard / Checker

Transaction recording

Test controller Monitor

TLMStimulus generator Driver DUTTransactionsCopyright 2008 by Doulos. All rights reserved.

3

Constrained Random VerificationChecker Constrained random stimulus Did we see a bug?

11001001 01001010 00001001 01110110 01100110 01001001 01001110

Design Under Test

000010 010011 000010 100100 001000 110010 000011 Functional CoverageAre we done?4

ConstraintsHeader Payload Checksum

Increase coverageCopyright 2008 by Doulos. All rights reserved.

The Verification SpaceVerification Formal Verification Acceleration + Emulation Property Checking Equivalence Checking

Simulation

Dynamic FormalSimulation Simulation Simulation Formal Simulation Formal

Transaction Level Modelling

Constrained Random Intelligent Testbench

Assertions

Coverage

5

Copyright 2008 by Doulos. All rights reserved.

What Our Customers Want

Ease of deployment Customizable environment

but it must do something useful straight out of the box

Simple, uniform interface to any verification IP block Gentle learning curve for the whole team

PowerComplex testcases co-ordinated across the whole environment Randomization Sophisticated coverage analysis

InteroperabilityEvery customer we meet has legacy verification IP6Copyright 2008 by Doulos. All rights reserved.

Methodology (or just a toolkit?)

Tame the language monster e, SystemVerilog, C++ are big and complicated Many ways to solve a problem Wheel reinvention is a hazard

ToolkitOOP encourages encapsulation of standard functionality in base classes Ideal for component hierarchy, reporting, block-to-block communication, DUT connectivity

Methodology Published methodology encourages interoperability and re-use Promote best practice7Copyright 2008 by Doulos. All rights reserved.

Mature Language StandardsList unchanged for 4 years...

Crude CaricatureFPGA, RTL, Europe, Mil-Aero

IEEE 1076 VHDLIEEE 1850 PSL

IEEE 1364 Verilog

ASIC, RTL, USA/RoW Hardware verification

IEEE 1800 SystemVerilog

IEEE 1647 e

Hardware verification

ISO/IEC 14882 C++ IEEE 1666 SystemC

Modelling, verification Virtual hardware prototypes for S/W dev

Tcl/Tk, Perl

Scripting8Copyright 2008 by Doulos. All rights reserved.

8

New Standards ActivityVerilog and SystemVerilog unified

LRM this year, currently in ballot feedback Major enhancements to assertions

Verification methodology

OVM 2.0, OVM-SC VMM open-source eRM3 - e / SV interoperability (Cadence) OVM / VMM interoperability (Accellera)

SystemC TLM-2.09Copyright 2008 by Doulos. All rights reserved.

The Big Methodology Players

www.ovmworld.org

www.vmmcentral.org

eRM

www.cadence.com

10Copyright 2008 by Doulos. All rights reserved.

Static View of TestbenchEnvironment Configuration checker

eRM

Sequencer active agent Driver BFM Monitor BFM

Sequencer passive agent Driver BFM Monitor BFM

simple ports (e) virtual interfaces (SV)

DUT11Copyright 2008 by Doulos. All rights reserved.

Static View of Testbench (VMM)... test_env env = new; env.run(); ...

Constraints; directed tests

GeneratorHigh level transactions Atomic transactions

Self Check

Transactor

Monitor

Functional Coverage

Checker

Driver

Properties

Checker

Monitor

DUT12Copyright 2008 by Doulos. All rights reserved.

OVM Key Features Constrained random, coverage-driven verification Separation of tests from verification environment Configuration of verification environment

through a table (canonical structure and guidelines)

Verification IP reuse

TLM communication Automation(where missing from SystemVerilog language)

Hierarchical sequential stimulus (sequences)

Standardized messaging13Copyright 2008 by Doulos. All rights reserved.

eRM Key Features Constrained random, coverage-driven verification Separation of tests from verification environment Configuration of verification environment

through AOP extension and pre-run constraints (rigorously standardized rules)

Verification IP reuse

Communication via ports Automation(using e language's macro features)

Hierarchical sequential stimulus (sequences)

Standardized messaging14Copyright 2008 by Doulos. All rights reserved.

VMM Key Features Constrained random, coverage-driven verification Configuration of verification environment

through configuration objects passed to verification components (conventions)

Verification IP reuse

Communication via channels, callbacks, notifications Automation(scripts and macros)

Hierarchical sequential stimulus (scenarios) Standardized messaging

Strongly influenced by RVM (Synopsys Vera)15Copyright 2008 by Doulos. All rights reserved.

Structure of an OVM Componentclass my_driver extends ovm_driver #(my_transaction);

Base class TLM port (inherited) Connection to DUT Constructor

// ovm_seq_item_pull_port #(...) seq_item_port;my_dut_if_wrapper m_dut_if; function new(string name, ovm_component parent); super.new(name, parent); endfunction: new function void build; super.build(); endfunction: build

Build phase callback

virtual task run; forever begin ... end endtask: run endclass: my_driver

Run phase callback

16Copyright 2008 by Doulos. All rights reserved.

Phase Methods (OVM)build connect end_of_elaboration start_of_simulation run extract check report

Call factory Make TLM connections After connections hardened

Get ready to runTask (executed concurrently)

Post-processing

Similar phase arrangements in VMM, eRMCopyright 2008 by Doulos. All rights reserved.

17

Reconfigurable Environment (OVM)By type or instance path

set_inst_override_*

Test Test

Customize environments

set_config_*

Reusable verification environment

Customize types

Scoreboard

Virtual sequencer

set_type_override_*

Config

Sequencer

Monitor

Existing verification component

Existing verification component

Monitor

Driver

DUT18Copyright 2008 by Doulos. All rights reserved.

Layered Sequential StimulusTests enumerate possible top-level sequences

Virtual or layered sequences

seq1

seq2

seq2

Constrained random sequence of transactionsRandomized transactions are not enough

tx1

tx2

tx3

Drive transactions into DUT

tx1

Driver

DUT

19Copyright 2008 by Doulos. All rights reserved.

Virtual SequencesComponent hierarchy ovm_env Stimulus hierarchy (co-ordinated interfaces)

ovm_sequencer

ovm_sequence

ovm_agent

ovm_agent

ovm_sequencer

ovm_sequencer

ovm_sequenceovm_sequence_item

ovm_driver

ovm_driver

dut_if DUT

dut_if

20Copyright 2008 by Doulos. All rights reserved.

Scenario Generator (VMM)Verification environment Scenario generator scenario_set [0] atomic burst items

select_scenarioselect

[1] burst

[2] RMW

copies of items

generator's output channel

Downstream transactor21

Copyright 2008 by Doulos. All rights reserved.

Now and NextVMM: rapidly growing collection of "applications"

register abstraction layer, hierarchy, ...

OVM/VMM interoperability toolkits/standards

OVM/eRM mixed-language tools

OVM-SC

Increasing availability of verification IP22Copyright 2008 by Doulos. All rights reserved.

Conclusion Interesting times

standards don't always keep up with user needs

Challenges for users choosing a new approach:

tools? methodology? decisions are not yet completely decoupled

Training is important:

VMM, OVM, eRM are not difficult ...... but jump-starting your efforts pays dividends

23Copyright 2008 by Doulos. All rights reserved.

24Copyright 2008 by Doulos. All rights reserved.