JOURNAL OF TELECOMMUNICATIONS, VOLUME 15, ISSUE 2, AUGUST 2012 1

HDBMn: A Novel Line Coding Scheme with Re-encoding Detection Assistance

Christos S. Koukourlis

Abstract— In this paper an alternative Line Coding technique is described. This technique belongs to the general family of modified AMI (Alternate Mark Inversion) line coding, like the HDB3 (High Density Bipolar of order 3). The name given to the proposed technique is HDBMn, i.e. High Density Bipolar Manchester of order n. For simplification purposes, it will be referred as HDBM3, i.e. n=3. The proposed scheme uses a much simpler decoder while maintains the number of transitions in the transmitted waveform. Due to the simplified receiver design a reduced BER (Bit Error Rate) is expected. One of the motivations is to show that the HDB3 coding scheme, which was adopted by the industry in RZ format during the last decades, was not optimally implemented. It will be shown that almost in all cases where an error gets in to the stream, the proposed method is superior compared to the ubiquitous HDB3, because of the straightforward decoding of the incoming signal and the error detection capability of AMI which is preserved. An additional feature here is the clock recovery at the receiver which is extracted by re-encoding the decoded data and comparing the re-encoded waveform with the input waveform in order to reduce any phase ambiguity of the recovered clock. Index Terms— AMI, B8ZS, Clock Extraction, E-carrier, HDB3, Line Coding, Re-encoder, Remodulator.

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1 INTRODUCTIONThe digital transmission systems usually adopt three fun-damental types of coding in order to improve their per-formance: source, channel and line coding. From these three the line coding has the general purpose of improv-ing the transmission reliability and its introduction is founded more on practical considerations than on the intellectuality of information theory [1]. Traditionally the codes were designed to produce a digital pulse train with specific spectral properties. These properties generally include the absence of a DC component and the presence of a strong spectral component from which timing can be extracted [2]. So, this paper refers to a rather technical field and is supported by a comparative rather theoretical study, attempting to show that the HDB3 coding scheme which was adopted by the industry in RZ format during the last decades in repeatered carrier systems could be implemented in a more straightforward and efficient way although preserving the spectral characteristics and ab-sence of DC of the standard HBD3 encoding scheme. In carrier systems, as applied in trunk telephony like the European E-carrier system, several line coding techniques have been adopted [3], [4]. The common characteristic of these techniques is that the encoded stream must lack any DC component, and consequently any low frequency spectral content in order to ensure that the signal passes through galvanic isolated stages where appropriate trans-formers are used. This capability is ensured by using bi-polar techniques like the AMI (Alternate Mark Inversion) where the “mark” level (usually logic one) is denoted

alternatively by positive and negative pulses of equal value, while the “space” level (say logic zero) is denoted by the zero line voltage, i.e. absence of pulse. Although the new technologies like ADSL, DSL, and the other IP based systems are now being widely deployed, current technologies that have given good service over many years will remain in use, as a result of their wide deployment, for the years to come. There are still many applications where an E1 tranceiver can be used, like PDH Multiplexers, ATM Switches, ISDN Terminals, xDSL Modems and Radio Modems [5]. Despite that in some text books the HDB3 is referred ei-ther as NRZ or RZ, the format that is used in industrial applications of E-carrier is Return-to-Zero [5], and this is also the case where the proposed method is applicable. The early and simpler members of this encoding family, like the AMI, suffer by prolonged absence of transitions due to many consecutive logic zeroes and may be delib-erately result in lack of system synchronization at the re-ceiver side, because the clock recovery stage of the receiv-er synchronizes itself on the transitions of the received waveform. So, for the purpose of preventing the pro-longed lack of transitions, several more advanced meth-ods like HDB3 and BxZS1 [3] have been adopted in order to insert pulses which result in transitions, but in some way these inserted pulses should be recognized as such and not interpreted as logic ones at the receiver side. For example the HDB3 line code which is used in all levels of the European E-carrier system replaces any instance of four consecutive 0 bits with the pattern “000V”, i.e. when four consecutive zeroes are to be coded, the fourth zero is encoded as pulse which seems like logic one, but of the same polarity of the previous pulse transmitted (called

1 Bipolar with x-Zero Substitution, where x=8 for the North American T1 carrier system, x=6 for T2 and x=3 for T3.

———————————————— • Christos S. Koukourlis is with the Department of Electrical and Computer

Engineering, Democritus University of Thrace, Telecommunications Sys-tems Lab, Xanthi, GR-67100, Greece

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violation pulse, “V”) in order to be discriminated from the valid logic ones. If the coding method was continuing in this way, then, for prolonged series of zeroes, each fourth pulse would have the same polarity of the previ-ous, resulting in the accumulation of long series of the same polarity pulses, giving rise to the accumulation of DC component, actually cancelling the first desirable characteristic which was the lack of DC. So, HDB3 uses a more complicated algorithm according to which the en-coder replaces any instance of 4 consecutive 0 bits with one of the patterns "000V" or "B00V". The choice of "000V" or "B00V" is made so that the number of B pulses, which are also called “balancing pulses” or “extra ones”, between consecutive V pulses is odd. In other words, suc-cessive V pulses are of alternate polarity so that no DC component is introduced. The encoding techniques like HDB3 use complex encod-ing and decoding circuitry and also complex state dia-grams when implemented as finite state synchronous machines [6], [7]. For example an HDB3 encoder must implement as many as 32 machine states [6]. In contrast, the proposed method uses a different and much more simplified rule in order to insert “violations”: The viola-tion of the RZ-AMI rule is not on the identical polarity of the pulse inserted, but on the time instant (position) that the pulse occurs during the bit period. In this paper the HDBM3 version, which directly com-pares with the well known HDB3, has been developed and constructed for a bit rate of 2 Mbps, although it is applicable for any rate, depending on the electronics em-ployed.

2 ENCODING/DECODING RULES OF HDB3 For the purpose of highlighting the complexity of the most frequently applied HDB3 encoding scheme, its rules are presented here. In Fig 1 a sample of an HDB3 encoded signal is shown. The pulses denoted by “V” and “B” are not actual logic ones and must be recognized by the de-coder and interpreted as logic zeroes. According to the encoding rules of HDB3, every time a sequence of trans-mitted bits occurs to be “0000”, the fourth bit changes to a level with the same polarity as the previously transmitted pulse, i.e. by violating the “rule” of alternating polarity (“V” pulse).

HDB3V

VV

BB

1 0 00 0 0 0 0 0 0 0 0 0 1

Fig. 1. HDB3 Line Code: the pulses denoted by “V” and “B” are not actual logic ones and must be recognized by the decoder.

In the case of longer sequences of zeroes this is not ade-quate, as soon as violation pulses (of the same polarity) will give rise to a DC component. In these cases an “extra one” is added (“B”) in the place of the first zero of the “0000” pattern, i.e. different polarity to the previous pulse while the fourth bit of the “0000” pattern is replaced also by a violation pulse i.e. of the same polarity to the just inserted “B” pulse. In conclusion, for long sequences of

zeroes, each pattern of “0000” is replaced either by a “+00+” pattern or by a “-00-” pattern depending on the polarity of the last transmitted pulse. In order to accomplish the decoding, the receiver must keep at least three next time intervals and at least one previous time interval in memory. An HDB3 receiver has to interpret any received pulse as one of three cases: logic one (“1”), violation pulse (“V”) or extra one (“B”). To ac-complish this task it has to know the polarity and the dis-tance (in clock cycles) of both the previous and the next pulses to the current one: If the previous pulse is of the same polarity (in any distance or alternatively, according to the encoding rule, at a distance of 3 or 4 clock periods) the current pulse is considered as a “V” and definitely it is interpreted as a logic zero. If the distance of the previ-ous pulse is one, then the receiver has to check if the next pulse has the same polarity and lies in a distance of three clocks. In this case the current pulse is an extra one (“B”) and must be interpreted as logic zero also. If the status of the current pulse does not fall in any of the two previous cases it is interpreted as logic one. Although the rules of encoding are well-known [3] and presented in Table 1, the decoding rules of HDB3, as summarized in Table 2, are given here in order to correspond to the encoding rules, as they are implemented in the hardware which is developed for comparative study.

TABLE 1 ENCODING RULES OF HDB3

TABLE 2

DECODING RULES OF HDB3

3 HDBMn, THE NOVEL ENCODING SCHEME From the above description the complexity of the HDB3 encoding/decoding format is obvious, although the above rules can be easily implemented and manufactured in hardware. Seeking for an encoding scheme that pre-vents the prolonged transmission of consecutive zeroes, but at the same time keeping strictly the rule of toggling the polarity of the transmitted pulses we ended up with the proposed method, HDBMn as a general format, or

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HDBM3 to be directly compared with the ubiquitous HDB3. This method uses a different and much more sim-plified rule in order to insert “violations”. Actually, the violation of the AMI rule is not introduced by “violating” the rule of alternative pulse polarity, but “violating” the time position that the pulse occurs during the bit period. To clarify this, let’s consider that we have AMI –RZ en-coded data, Fig. 2, which means that the alternate polarity pulses are generated during the first half of the clock pe-riod. According to the proposed method, when a viola-tion pulse is to be inserted, the rule of alternate polarity pulses is not violated as in HDB3, but it is maintained, as explained above. The violation regards the time position of the inserted pulse which takes place during the other half of the bit interval. This alteration of time interval dur-ing which the pulse is inserted gives rise to the letter “M”, from the well known “Manchester” encoding scheme, in the name of the proposed technique, HDBMn, or HDBM3. In Fig. 2, for clarification purposes, the AMI line code as well as the HDB3 and HDBM3 line codes are given. Also, another line code, named HDBM3* is given. This code inserts the data into the first half clock period and the violation to the second one. Unfortunately, when a long series (multiple of four) of zeroes is followed by a logic one, this gives rise to a pulse pattern which swifts from all negative to all positive (or vice-versa) without stepping through zero voltage. This is shown in Fig.2 in the dashed square of the waveform named HDBM3*. Although this does not seem to be a problem, it could amplify some spectral lines and intuitively the encoding rule of HDBMn is somewhat modified, which now becomes the infor-mation (data) being inserted in the second half while the violation pulse is inserted in the first half of the bit dura-tion. Also, comparing HDBM3* and HDBM3 in Fig. 2, the latter seems to have two transitions instead of one (but of full height).

1 0 00 0 0 0 0 0 0 0 0 0 1

AMI

HDBM3*V

VV

HDB3V

VV

BB

HDBM3V

VV

Fig. 2. AMI, HDBM3 and HDB3 Line Codes compared. HDBM3* is as intermediate step for explanation purposes.

The proposed encoding scheme maintains the density of violations (“V” pulses) and spectral properties of HDB3, i.e. it gives rise to the necessary transitions for the clock recovery stage of the receiver and, at the same time, does not pose any problem of DC accumulation since the rule of alternate polarity pulses is strictly maintained. On the receiver side, after the recovery of the clock waveform, the decoding of the received signal is extremely simple as the clock waveform just samples the data waveform al-

ways during the second half of the bit period where the transmitted information lies and never during the first half where the “violation” pulses lie. Compared to HDB3, this greatly simplifies the decoding rule, which, in the case of HDB3, is rather complicated as shown in Table 2 because the HDB3 receiver has to keep several bits of the bit pattern in order to decide which was the actual trans-mitted data and not confuse any violation pulses or the so called “extra ones” (“B” pulses) from interpreted as logic ones. Actually, the major goal of the receiver is restricted to the clock recovery, since the decoding is extremely simple for the proposed method. Then the decoding is achieved simply by sampling the “rectified” HDBM3 waveform by a D flip-flop triggered by the rising edge of the recovered clock. The timing is shown in Fig. 3.

Recovered Clock

NRZDecoded data

1 0 00 0 0 0 0 0 1 0 0 1 1

HDBM3“rectified”

V V

1 0 00 0 0 0 0 0 1 0 0 1 1

HDBM3V

V

RZDecoded data

Fig. 3. An illustration of decoding an HDBM3 encoded waveform. The violation is entered into the first half of the bit interval (clock period), while the data at the second one.

4 CLOCK RECOVERY – DATA RE-CODING Regarding the implementation of the proposed method, the recovery of the clock at the receiver is based on the use of a Digital Phase Locked Loop (DPLL), the 74HC297. This device is manufactured by several companies. In our case the DPLL was introduced to an Altera chip (EPM 7064LC44-10) from the appropriate library, together with the rest of the circuitry. Based on this, the clock recovery itself is simple, but other design problems were intro-duced, specifically the 1800 phase ambiguity of the recov-ered clock. As previously mentioned, before the decoding, the in-coming data has to be somewhat “rectified”. This takes place, as will be explained below, by a combination of analog comparators and an OR gate which sums all the pulses, either positive or negative, in a unipolar pulse stream. The recovered clock can have a 1800 phase ambi-guity because the recovery is based on both kinds of puls-es, i.e. actual data or violation pulses. It is possible instead of the real data to decode the violation pulses as data due to 1800 phase ambiguity of the recovered clock. This un-certainty, although similar to the one in BPSK modula-tion, obviously cannot be cancelled by using some kind of differential encoding. Initially, the incoming waveform is decoded by randomly selecting one of the two 180o recovered clock waveforms. The decoded data produced by this decoding are re-encoded at the receiver giving a locally produced HDBM3

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waveform in order to be compared with the received one. The local encoder at the receiver inserts the violation pulses according to the encoding rule but actually the re-encoded waveform does not need to be bipolar. It is suffi-cient and more appropriate that the re-encoded waveform is like the “rectified” HDBM3 waveform. The two “recti-fied” waveforms, after the appropriate synchronisation with the same clock at the receiver, are compared: if iden-tical, the randomly selected clock is the appropriate one, otherwise the inverted clock is selected and the decoding proceeds correctly. Additionally, for stability purposes, the decision for clock phase selection is not taken imme-diately after the detection of a single incompatibility, but it is delayed for at least three incompatibility detections in order to cancel erroneous actions.

5 COMPARATIVE STUDY OF BIT ERROR RATE PERFORMANCE

A mathematical analysis of the BER improvement would require studying the HDB3 decoder as a Markov process. The impact of every possible input detection error would have to be examined for every possible state of the pro-cess to determine the bit errors it would cause. The indi-vidual state BER could then be evaluated taking into ac-count the probability of a sample detection error Pe and the respective steady state probability. The total BER of the system would be the sum of these individual-state error probabilities. However, such an analysis is beyond the scope of this technical paper, particularly since the presented study is not about the HDB3 system as is, but a modified implementation which renders this analysis irrelevant, as the BER is evaluated directly by the sample detection error probability, i.e. Pe. Instead, it will be illus-trated that in the HDB3 scheme a single sample error, at the physical layer, can result in multiple bit errors in sev-eral cases due further decoding, whereas in the proposed HDBM3 system a single sample error at the physical layer results mostly in one bit error, which is sufficient to make the point that the BER performance is improved. So, the BER performance of the proposed method (HDBM3 case) will not be studied independently but comparatively to the industry dominating coding scheme, the HDB3. One of the goals of this paper is to show that the HDB3 coding scheme, in the manner that it was adopted during the many previous years, was not the optimum one. From Table 2 it can be seen that the HDB3 decoder must take into account as much as four incoming bits in order to decide about the final value of a specific bit because any error introduced affects the decision of other bits giv-ing rise to new errors after decoding. There are two cases of errors in the physical layer level: a “1” is missing or a “1” is erroneously interpreted as such in a place that it does not exist. For the case of HDB3 this is analysed in Table 3. It must be emphasized here that the errors inserted in the transmitted signal (physical lay-er) of Fig. 4 are denoted by “E” while the symbol “E” un-der the recovered data, at the bottom of each pattern, marks the position of the error in the decoded data stream. These errors have been marked by applying the

rules of Table 2. In the HDB3 every single bit is detected by sampling appropriately during the bit interval and then applying the decoding rules, while in the proposed HDBM3 scheme any bit is detected just by sampling the incoming waveform (it is meaningless to mention that the sampling takes place in the second half) without further decoding. It is straightforward to assume that if both waveforms (HDB3 and HDBM3) are affected by the same level of noise they will exhibit identical probability of bit error in the transmitted signal over the channel. However, due to the required memory of the HDB3 decoder each error can affect as many as three decoded bits, as illus-trated in Fig.4. On the contrary, in the proposed scheme, each channel error will result at most to one data error since no further decoding is applied.

VV

VB

B1 0 00 0 0 0 0 0 0 0 0 0 1

E

1 0 00 0 0 0 0 0 0 0 0 11E

VV

VB

B1 0 00 0 0 0 0 0 0 0 0 0 1

1 0 10 0 0 0 0 0 1 0 0 0 1E E

E VV

VB

B1 0 00 0 0 0 0 0 0 0 0 0 1

E

1 0 00 1 1 0 0 0 0 0 0 0 1E E

VV

VB

B1 0 00 0 0 0 0 0 0 0 0 0 1

1 0 00 0 0 1 0 0 1 0 0 0 1E E

E VV

VB

B1 0 00 0 0 0 0 0 0 0 0 0 1

E

1 0 10 0 0 0 1 0 0 0 0 11EE E

VV

VB

BE1 0 00 0 0 0 0 0 0 0 0 0 1

1 0 00 0 0 0 0 0 0 0 0 0 1

VV

BB

1 0 00 0 0 0 0 0 00 01 0

0V 0 00 0 0 0 0 0 01 01 0E E

E

(a). A “1” is missing

(b). A “B” is missing (either polarity).

(c). A “V” is missing (either polarity).

(d). A same polarity pulse is inserted between “1” and “V”.

(e). A same polarity pulse is inserted between “B” and “V”.

(f). An opposite polarity pulse is inserted between “1” and “V”.

(g). An opposite polarity pulse is inserted between “B” and “V”.

(h). A pulse (either polarity) is inserted between two successive “1”.

VV

VB

B1 0 00 0 0 0 0 0 0 0 0 01

0 0 00 0 1 1 0 0 0 0 0 01E E E

E

Fig. 4. Each waveform, affected by an error at the physical layer, corresponds to one case of Table 3. Above each waveform the cor-rect data are given, while below this the decoded data are given. Where “E” denotes the position of Error.

This results in higher BER for the HDB3 when compared to the proposed scheme since the HDBM3 decoder’s deci-sion is straightforward in contrast to that of HDB3. As deduced from Table 3, due to this effect, the HDBM3 cod-ing scheme exhibits on the average more than three times better BER than the HDB3 scheme. Moreover it must be emphasized again that the proposed scheme maintains the error correction capability of AMI (i.e. the rule of al-ternate polarity signaling is never violated in AMI and also in HDBM3) while this is not possible for the HDB3 case, due to the inherent violation. This means that in any case of same polarity error pulse insertion, the error will be self corrected in HDBM3, boosting the error correction capability since the receiver knows the expected polarity. Also, it can be observed from Fig. 4 and Table 3, that there is only one occasion (Case d) where the HDB3 scheme self corrects the error pulse inserted, because, although a pulse exists, it is translated as violation (which results in logic “0” after decoding) because it has the same polarity with the previous pulse. Even in this case, if the detection of a “V” was stricter, i.e. examining the exact distance

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from the previous pulse (3 or 4 clock periods to accept as a “V”) the result would be against the HDB3 scheme.

TABLE 3 COMPARISON OF ERROR BEHAVIOUR OF HDB3 AND HDBM3

CODES

6 DESIGN AND IMPLEMENTATION The proposed encoding scheme has been implemented for a bit rate of 2Mbps instead of the nominal 2,048 Mbps of the European E1 standard. Although it is not essential to mention this detail, it is done here since the measure-ments with spectrum analyzer or oscilloscope (which are to appear later) must be justified in a more practical sense. The first stage of the HDBM3 encoder, Fig. 5, is a four-successive-zeroes detector which serves for the insertion of the violation pulses and combines them to the actual data. Two pulse streams are produced which drive the two inputs of a differential amplifier which finally pro-duces the bipolar signal. Equivalently the two pulse streams could be combined on a line transformer. For experimental purposes this stage was built around a high frequency op amp (AD8047).

HDBM3 output(Bipolar RZ signaling)

Bipolar SignalingDifferential Stage

Conversion to two streams for positive and negative pulses

Detection of “0000” data pattern

Insertion of “V” pulsesNRZ input data

Fig. 5. Block diagram of the HDBM3 Encoder.

Decoded DataDecoder Stage

Removal of bipolar signaling(”rectification”)

HDBM3 bipolar input

Clock Recovery Stage (DPLL)

----------------------------------Re-Coder

Recovered Clock

Fig. 6. Block diagram of the HDBM3 decoder.

The block diagram of the decoder is shown in Fig. 6. Both the phase comparators of the 74HC297 DPLL which is adopted for clock extraction are employed (XOR Phase Detector and Edge Controlled Phase Detector). In the pre-sent case a ten stage loop has been adopted, i.e. the coun-ter of the DPLL counts up to != 210=1024. The crystal of the receiver needs to be eight times higher, i.e. 16 MHz in order to recover the 2 Mbps associated clock.

7 HARDWARE IMPLEMENTATION In Fig. 7 photographs of the implemented encoder and decoder are shown. In the Altera chips, in addition to the HDBM3 encoder/decoder, AMI and HDB3 pairs of en-coders/decoders have been incorporated so that the ex-perimental measurements can be compared. The selection of the encoding/decoding scheme takes place via the DIP switches shown in the pictures.

Fig. 7. Photo view of the experimental implementation of the encoder / decoder stages.

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8 EXPERIMENTAL RESULTS Several osciloscope and spectrum analyzer image captures are given. In Fig. 8 the insertion of violation pulses is shown. Fig. 9 shows random HDBM3 encoded data in bipolar format and the “rectified” version of this data at the first stage of the decoder. In Fig. 10 the unipolar re-encoded data with the synchronized unipolar received data are shown, while the middle trace shows that their algebraic difference is almost zero. In Fig. 11 the recovered clock is shown. Finally, Fig. 12 shows both random input data and the decoded data waveforms.

In Fig. 12 the spectral densities of HDBM3, HDBM3*, HDB3 and AMI are presented. As stated previously, all these encoding schemes have been implemented in the same Altera chip and can be selected via the DIP switches of the experimental boards.

Fig. 10. Upper trace: HDBM3 waveform at the decoder’s input. Lower trace: Recovered Clock.

Fig. 11. Upper trace: Original data. Lower Trace: Decoded data. A delay is obvious.

Fig. 12. Spectra of Line coding schemes of HDBM3, HDBM3*, HDB3 and AMI.

For all the above measurements the frequency span of the spectrum analyzer is 6 MHz with center frequency 3 MHz. For experimental purposes the input data of 2 Mbps rate were generated in an 8-flip-flop long pseudo-random generator (scrambler) incorporated in the Altera chip. The spectra shown in Fig. 13 look almost identical, as expected. Since the input data source is not guaranteed to produce an uncorrelated data stream, the above spectra

Fig. 8. Upper Trace: Data (scrambler output). Lower trace: Encoder output. It is noted that the violation pulse lies in the first half of the bit duration.

Fig. 9. Upper trace: HDBM3 encoded data in bipolar format. Lower trace: “Rectified” data at the first stage of the decoder.

Fig. 9. Upper Trace: Unipolar Re-coded data waveform. Lower trace: synchronized unipolar received data. Middle trace: the algebraic difference of the two is almost zero.

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present minor differences depending on the capture instant because of the unavoidable data correlation [8].

9 CONCLUSION In this paper an alternative line coding scheme for data transmission is proposed and described. It is directly comparable to the European E-carrier standard for data transmission, HDB3. Especially the receiver design is greatly simplified giving rise to lower BER, while the transition density of the transmitted signal is maintained the same as in HDB3. Also, the clock recovery is assisted by a re-encoding technique, in order to overcome any phase ambiguity of the recovered clock at the receiver.

ACKNOWLEDGMENT The author wishes to thank Mr. Dimitrios C. Chrysos-tomidis, graduate student of the Telecommunications Systems Laboratory of Democritus University of Thrace, for his collaboration in the implementation and construc-tion of the hardware of both the encoder and decoder.

REFERENCES [1] G.L. Cariolaro, G.L. Pierobon and G.P. Tronca, "Analysis of Codes and

Spectra Calculations", Int. Journal of Electronics, Vol.55, No.1, pp.35-79, 1983.

[2] B.S.Bosik, "The Spectral Density of a Coded Digital Signal", Bell System Technical Journal, Vol.51, No.4, pp.921-933, 1972.

[3] Ericsson Telecom AB, Telia AB, Understanding Telecommunications, Studentenliterature, Lund, Sweden, 1998.

[4] ITU-T G.703, Series G: Transmission Systems and Media, Digital Sys-tems and Networks, Digital Terminal Equipment – General Physi-cal/Electrical Characteristics of Hierarchical Digital Interfaces ITU-T Recommendation G.703.

[5] A.Vasilliou, K. Gounaris, K. Adaos, D. Mitsainas, G.Alexiou, D. Ni-kolos, “Development of a Reusable E1 Transceiver Suitable for Rapid Prototyping”, IEEE International Workshop on Rapid System Prototyping, Clearwater, FL , USA, Jul 1999, pp. 21-26.

[6] D. Keogh, “The State Diagram of HDB3”, IEEE Trans. Comm., Vol. COM-32, No 11, Nov. 1984, pp. 1222-1224.

[7] Yang Zhang, Xiumin Wang, Yuduo Wang, "A New Design of HDB3 Encoder and Decoder Based on FPGA," Conference on Hybrid Intelligent Systems, International, vol. 1, pp. 210-213, 2009 Ninth International Con-ference on Hybrid Intelligent Systems, 2009.

[8] G.L. Cariolaro and G.P. Tronca, "Spectra of Block Coded Digital Sig-nals", IEEE Trans. Comm., vol. COM-22, pp. 1555-1564, Oct. 1974.

Christos S. Koukourlis was born in Kavala, Greece, on August 13, 1957. He received the Electrical Engineering Diploma in 1981 and the Ph.D degree in Electrical Engineering in 1990 both from the Democritus University of Thrace, Xanthi, Greece. He currently serves as Dean of the School of Engineering of Democritus Universi-ty of Thrace. He served also as Head of Department of Electrical & Computer Engineering of Democritus University of Thrace where he also serves as Associate Professor working on digital modulation and high spectral efficiency techniques. His interests also include Data Transmission over TV Broadcasting, Power Line Modems, Direct Digital Synthesis (DDS) methods, Communications Networks and Fleet Management (GPS based) Systems over GSM network.