keith morrisevla front-end cdr – new evla receiver card cage april 24, 2006 1 evla front-end cdr...

Keith Morris EVLA Front-End CDR – New EVLA Receiver Card CageApril 24, 2006

1

EVLA Front-End CDR

The New EVLA

Receiver Card Cage


2

Overview

• The EVLA Card Cage shall:– Provide 8 stages of conditioned LNA bias– Control and monitor cryogenic sensors– Interface to Monitor/Control system

• (But allow stand-alone bench testing)

– Mount to EVLA receivers– Minimize EMI– Minimize assembly time and cost


3

Block Diagram

FE Card Cage

Control/Sensor Card

Spare/OptionalCard Slot

DC VoltageRegulator

Board

Bac

k P

lan

eFront Panel User Interface

VacStby Cool Heat

FailL/R

LNA Bias Card

PotsLCP

VD ID

VD

VD

VD ID

ID

ID

RCP

VD ID

ID

ID

ID

VD

VD

VD

Scott-TeeXformer

DC PowerDistribution

AC RelayBox

PumpController

Module

M&C F317 Module

MIB

Dewar

LNA Over-Voltage

ProtectionBoard LCP

LNA

RCPLNA


4

Pseudo-passive Scheme

• 96 available analog monitor points, selectable in banks of 3

• Default critical diagnostic parameters– Gate voltage sums (RCP, LCP)– 15K stage temperature

• MIB mounted remotely• No digital signal traffic during observation


5

Card Cage:EVLA vs. VLA/VLBA

VLA/VLBA EVLA4 stages of bias/card 8 stages of bias per card

Hard-wired logic Programmable logic

Hand-wired interconnects Backplane/ribbon cable

Clock-driven display Pseudo-passive monitoring

Unique to each Rx band Universal design

AC/digital EMI No AC or fast clocks

Open, custom chassis Modified COTS enclosure


6

Chassis: VLA


7

Chassis: EVLAInterim only


8

Wiring: VLA

•250-300 individual solder points•Wire directions hand- randomized to prevent EMI due to AC


9

Wiring: EVLA

•6 IDC connections•8 solder points•16 crimps•No AC, clocks


10

Enclosure

• COTS Stamped Al VME Chassis

• Pre-assembled with hardware

• 1/3 the weight of extruded aluminum

• 1/4 the cost!


11

Minimizing Assembly

• IDC/Crimp vs. hand-soldering

• Pre-assembled chassis

• Modular, universal design


12

Control/Sensor Card

• Replaces VLA:– Control,

– Sensor and

– Monitor cards

• Altera CPLD• No fast clock!• 4” x 6” Eurocard


13

Control PLD

• Communication registers for Digital IO– 32 x 4 latching input registers

– 32 x 4 output registers

– SPI-compatible


14

Cryogenic State Machine

• 9 sensor comparators

• 4 user-set state commands

• 14-way LED state indicator

• Local/remote control


15

Cryogenic Control

-2

0

2

4

6

8

10

0:00

:00

0:10

:30

0:21

:00

0:31

:30

0:42

:00

0:52

:30

1:03

:00

1:13

:30

1:24

:00

1:34

:30

1:45

:00

1:55

:30

2:06

:00

2:16

:30

2:27

:00

2:37

:30

2:48

:00

2:58

:30

3:09

:00

3:19

:30

3:30

:00

3:40

:30

3:51

:00

4:01

:30

4:12

:00

4:22

:30

4:33

:00

4:43

:30

4:54

:00

5:04

:30

5:15

:00

5:25

:30

5:36

:00

5:46

:30

5:57

:00

6:07

:30

Time (10 second interval)

Vo

lta

ge

15K

50K

Vd

Solenoid Status

Pump Request Status


16

AC Relay Box

• Removes AC & its EMI from Card Cage

• Allows logicbypass for Fridge

• Separate LEDfor each request


17

8-Stage Bias Card

• Based on GBT 6-stage design

• Allows disabling of stages in banks of 2

• VD, ID, and VG are monitored

• 4” x 6” Eurocard


18

LNA Diode Protection Board

• Accommodates 8 bias stages

• Drain voltage clamped to +6V/-1V

• Gate voltage clamped to +1V/-2V

• Soldered to hermetic feedthrough


19

Receiver ID

• Band code, Receiver S/N, and revision stored in 64kB EEPROM

• Spare capacity for text—CAL files, bias settings, etc.

• Follows receiver, not Card Cage


20

RF/IF Box Interface

• Accommodates VLA and EVLA solar calibration• 28V noise cal is not switched in Card Cage


21

RF/IF Box Interface

• SPI for logic, step attenuators• LVTTL from Card Cage to external

switching circuit• Separate voltage

regulation for Room-TempRF components


22

DC Power

• +17, -17, +7, +32V from DC distribution– Through to RF/IF interface

• +15, -15, +5, +3.3V for Card Cage, AC Relay BoxVoltage from

DC Distribution

Card Cage

RF/IF Box

AC Relay Box

Total at DC Distribution

Current (A)

Current (A)

Current (A)

Current (A)

+17 VDC 0.60 1.40 0.00 2.00

-17 VDC 0.26 0.10 0.00 0.36

+7 VDC 0.64 0.90 0.05 1.59

+32.0 VDC 0.00 0.08 0.00 0.08


23

Monitor & Control

• Up to 35’ cable run Differential ( 25 STPs)– +/-5V analog range– LVDS for digital

• Monitor 3 of 96 possible analog points– Select with 5-bit address from F317– Change only when data will not be corrupted


24

Production Costs

Unit cost for 30 (5 antenna/yr.) cost for 165 (entire array)

Backplane $5,263 $13,657

Daughtercard $7,042 $22,169

Bias Card $6,913 $32,386

Control/Sensor Card $9,630 $34,485

Voltage Regulator Card $2,243 $9,613

RF/IF Box Cal Switching $3,516 $13,536

Ribbon Cable Assemblies $1,897 $8,286

Chassis $8,163 $39,271

Total $44,667 $173,403

Each $1490 $1050


25

Summary

• Eliminates EMI from fast clocks/AC

• Universal to all receivers

• Minimizes assembly time & cost

• Leverages existing NRAO designs (where possible)


26

Questions?


27

Effect of Bias Card on Receiver Performance

C Band #05 LCP Trx Including warm test polarizerOld vs New card cage

10

12

14

16

18

20

22

4.5 4.6 4.7 4.8 4.9 5 5.1 5.2

Frequency (GHz)

Trx

(K

)

LCP New

LCP Old


28

Effect of Bias Card on Receiver Performance

C Band #05 RCP Trx Including warm test polarizerOld vs New Card cage

10

12

14

16

18

20

22

4.5 4.6 4.7 4.8 4.9 5 5.1 5.2

Frequency (GHz)

Trx

(K

)

RCP New

RCP Old


29

Monitor and Control

VD1VD2VD3VD4VD5VD6VD7VD8

ID1ID2ID3ID4ID5ID6ID7ID8

VG1VG2VG3VG4VG5VG6VG7VG8

A[4..0]

Temp 15KTemp 50KDewar VacuumPump VacuumPower Supply MonitorNoise Cal Mon2nd Bias MonitorSpare Monitor

BiasMonitor

SensorMonitor

AnalogMonitorto F317

3

Analog Multiplexers


30

Monitor & Control: Digital Monitors


31

Monitor & Control: Analog Monitors

keith morrisevla front-end cdr – new evla receiver card cage april 24, 2006 1 evla front-end cdr...

Documents

evla card cage

evla receivers

evla interim

controlsensor card

ac slide

vla slide

cost slide

observation slide