InterruptsKhaled A. Al-Utaibialutaibi@uoh.edu.sa

Agenda

Interrupt-Driven I/O Hardware Interrupts Responding to Hardware Interrupts INTR and NMI Computing the ISR Address Hardware Interrupt Timing Interrupt Acknowledge Cycles

The 80x86 processors receive interrupts from three different sources: −(1) The processor itself, due to an internal fault (e.g. an

attempt to divide by zero)−(2) The software interrupt instruction INT n (commonly

used in the PC to access the BIOS and DOS functions),−(3) External hardware.

I/O devices that interface to the processor using a hardware interrupt are said to be interrupt driven.

Interrupt-Driven I/O

When interfacing I/O devices to a microprocessor, the real problem for the microprocessor is that it does not know when the I/O device is ready.

One way of determine if a device is ready is to program the processor to repeatedly poll (check) the I/O device BUSY/READY line (flag).

The disadvantage of this approach (hardware polling) is that all of the resources of the processor are wasted waiting for this flag (i.e. no other tasks can be performed).

Hardware Interrupts

A more logical approach would be to have the I/O device tell the processor when it is ready.

This is the purpose of the microprocessor's interrupt input (hardware interrupt).

Using this technique, the processor can spend most of its time with other tasks, only servicing the I/O device briefly when interrupted.

Hardware Interrupts

At the end of each instruction, the processor samples its interrupt input.

If active, control is transferred to a special Interrupt Service Routine (ISR).

Figure 1 shown the sequence of this process: −(1) The processor is assumed to be executing its main task. −(2) The I/O READY flag causes an interrupt to occur. −(3) The current instruction is finished. −(4) The CS, IP (or EIP), and flag registers are pushed onto the

stack at time 4. −(5) The control transfers to the ISR. −(6) The ISR is executed, terminating with the instruction lRET

(interrupt return). −(7) The CS, lP, and flag registers are recovered from the stack. −(8) The original task is resumed.

Responding to Hardware Interrupts

Figure: Sequence of hardware interrupt process.

The 80x86 processors have just 2 hardware interrupt pins: −(1) INTR−(2) NMI.

NMI (Non-Maskable Interrupt)−It cannot be blocked; the processor must respond to it. −For this reason the NMI input is usually reserved for critical

system functions, for example, saving the processor state when a power failure is eminent.

INTR (Interrupt)− It is maskable via the IF flag. −Using the instruction STI-set interrupt flag-interrupts are enabled

on INTR. −Similarly, the instruction CLI-dear interrupt flag--disables

interrupts on this input.

80x86 Interrupts Pins

Figure 2 shows the flowchart of the 80x86 processors response to internal and external interrupts.

The internal interrupts have the highest priority (they are serviced first when multiple interrupts are received).

The processor automatically clears IF when an interrupt (internal or external) is received.

This means an INTR interrupt cannot interrupt a previous service routine that has not yet completed (unless that routine specifically sets IF to allow this).

80x86 Interrupts Pins

When the IRET instruction is executed, the flags are restored, and if the IF (the interrupt flag) was previously set, INTR interrupts will again be enabled.

When the TF (the trap flag) is set, the processor will execute a type 1 interrupt after each program instruction.

Typically, this is used in debugging mode, as it allows the processor to be single-stepped one instruction at a time.

This interrupt has lowest priority (it is serviced last when multiple interrupts occur).

80x86 Interrupts Pins

Figure 2: Flowchart of the 80x86 processors response to internal and external interrupts.

In Real Mode (8086), the address of the interrupt service routine is stored in 4 consecutive memory locations (a double-word) in an interrupt vector table beginning at address 00000H.

When an interrupt occurs, an 8-bit type number is supplied to the processor, which identifies the appropriate entry in this table.

The method for determining the type number depends on the interrupt source:−(1) Software interrupts supply the type number as part of the

instruction (INT n, where n is the type number). −(2) Internal interrupts have predefined type numbers: for example, a

divide-by-zero error causes a type 0 interrupt (Refer to Table 1 for a complete list.)

−(3) The NMI hardware interrupt is predefined as type 2 and extracts its vector from locations 00008H-0000BH.

−(4) INTR must gate its type number onto data bus lines D0-D7 during a special interrupt acknowledge cycle.

Computing the ISR Address

The address where the vector is to be stored is computed by the processor by multiplying the type number by four (or by eight in Protected Mode).

The resulting number is then used as a pointer to one of the 256 possible interrupt vectors.

Computing the ISR Address

Table 1: Predefined interrupt type numbers.

Example 1: A particular Real Mode interrupt has a type number n = 41H. If the corresponding ISR begins at address 09E3:0010H, determine the locations in the vector table to store this address.−The vector address is calculated by

multiplying 41H by four. −This is done most easily by rotating 41H left

twice. 41H = 0100 0001; rotate left twice -> 01 00000100 = 104H.

−The offset address of the ISR is stored in the low word

−location and the segment address in the high-word location.

Computing the ISR Address

The 80x86 processors sample the INTR and NMI inputs at the end of each currently executing instruction.

The NMI input is rising-edge-triggered and internally synchronized.

The INTR input is level-triggered and must be held high until acknowledged by the processor.

The 8086 and 8088 provide the INTA signal for this purpose; the 386 and later processors provide a unique bus cycle that can be decoded for this purpose.

The NMI input (and all internal interrupts) are not acknowledged.

Hardware Interrupt Timing

Regardless of the processor, when the INTR interrupt is accepted, two interrupt acknowledge cycles are executed (two INTA’ pulses), separated by four idle clock pulses (to allow for 8259A programmable interrupt controller recovery time).

The first cycle acknowledges the interrupt request and alerts the external hardware to prepare to gate the type number onto the data bus lines.

During the second cycle, the processor inputs the contents of its D0-D7 data lines, which it interprets as one of the 256 possible type numbers.

Interrupt Acknowledge Cycles

Figure shows a circuit that can be used to drive the INTR input of the 8086.

In this case the I/O device is assumed to supply a falling edge to indicate that it is ready for more data.

This signal clocks the flip-flop, driving INTR high. The first INTA’ pulse resets Q, removing INTR

before it can be interpreted as a second interrupt request.

The RESET’ input ensures that INTR will be low after the system is reset.

Interrupt Acknowledge Cycles

Figure 3: circuit that to drive the INTR input of the 8086

Figure 4 illustrates a technique for gating the type number onto the low data bus lines.

The LOCK signal is combined with INTA’ to enable the tri-state gates during the

second INTA’ pulse, when the processor expects the type number.

In this example, the gates are wired to input n = 41H.

Interrupt Acknowledge Cycles

Figure 4: Gating the type number onto the low data bus lines