A Functional Hybrid Memristor Crossbar-Array/CMOS System forData Storage and Neuromorphic ApplicationsKuk-Hwan Kim,† Siddharth Gaba,† Dana Wheeler,‡ Jose M. Cruz-Albrecht,‡ Tahir Hussain,‡

Narayan Srinivasa,‡ and Wei Lu*,†

†Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, Michigan 48109, United States‡HRL Laboratories LLC, 3011 Malibu Canyon Road, Malibu, California 90265-4797, United States

*S Supporting Information

ABSTRACT: Crossbar arrays based on two-terminal resistiveswitches have been proposed as a leading candidate for futurememory and logic applications. Here we demonstrate a high-density, fully operational hybrid crossbar/CMOS systemcomposed of a transistor- and diode-less memristor crossbararray vertically integrated on top of a CMOS chip by takingadvantage of the intrinsic nonlinear characteristics of thememristor element. The hybrid crossbar/CMOS system canreliably store complex binary and multilevel 1600 pixel bitmapimages using a new programming scheme.

KEYWORDS: Memristor, resistive memory (RRAM), crossbar, hybrid integration, multilevel, neuromorphic system

The crossbar resistive memory array, in which the storageelements are two-terminal resistive switches (sometimes

termed memristors) forming a passive interconnected network,and hybrid crossbar/CMOS systems have been identified as aleading candidate for future memory and logic applications.1−11

However, a fundamental problem for such a passive array is that‘sneak paths,’ which correspond to parasitic current paths thatbypass the target storage element, can be formed (Figure S1,Supporting Information) and cause the array to be nonfunc-tional. To suppress current flowing through sneak paths, amemory cell in the crossbar memory essentially needs twocomponents: a memory switching element which offers datastorage and a “select device” which regulates current flow.Several reports have shown that it is possible to scale theswitching element down to nanometer scale with excellentperformance in terms of speed, retention, and endurance.12−15

On the other hand, obtaining a suitable select device that canbe integrated in a crossbar array has become a significantchallenge in resistive memory research, since diodes based oncrystalline materials are not suitable for low-temperaturefabrication, while those based on low-temperature materialssuffer from performance and reliability issues.16−18 Due tothese difficulties, even though a number of approaches havebeen proposed to address the sneak path problem using diodesas the select device or using novel complementary cellstructures,16−20 the demonstrations have been essentiallylimited to the single-device level (either from standalonedevices or from arrays in which all nonselected devices werekept in the off-state), and actual array-level operations wheremany cells are written then read out together have remainedelusive.

Instead of relying on an external diode as the select device, amore ideal approach is to take advantage of the inherentnonlinear current−voltage (I−V) characteristics obtained insome resistive switches themselves to break the sneak currentpaths.21−24 Here we demonstrate that fully operational crossbararrays that do not require external transistor or diode selectdevices can indeed be built by employing switching elementswith inherently nonlinear I−V characteristics. The transistor-and diode-less crossbar arrays can be readily stacked on top ofeach other to further maximize the density advantage offered bythe nanoscale devices.4 Furthermore, by eliminating therequirement of having an external select device at eachcrosspoint, this approach significantly simplifies the arrayfabrication processes and enables the array to be completedat low temperature and directly integrated on top of underlyingCMOS circuits. In this demonstration, the CMOS circuitsprovide peripheral functionality, such as address decoding, tocomplement the data storage functionalities of the crossbararray. A new programming scheme is also developed to controlthe device on-resistance and allow for multilevel storage in thearray.The device structure studied here consists of a W/SiGe stack,

an amorphous Si (a-Si) layer, and a Ag layer acting as thebottom electrode, the switching medium, and the top electrode,respectively. The thickness of each layer was carefully designedfor arrays of 50 nm half pitch. To prevent CMOS degradationin this back-end-of-line (BEOL) approach, the maximum

Received: October 19, 2011Revised: November 19, 2011Published: December 5, 2011

Letter

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temperature involved in all the fabrication processes was keptbelow 425 °C. The final structure shown in Figure 1a has 40top nanowire electrodes crossed with 40 bottom nanowireelectrodes with a switching element formed at every crosspoint.A 50 nm half pitch was achieved through electron beamlithography and yielded an equivalent data storage density of 10Gbits/cm2 (Figure 1b) when storing one bit per memory cell. Ahigher data storage density was also achieved by multileveloperation as discussed below. To integrate the crossbarstructure directly on top of the CMOS circuit, every row

(top electrode, corresponding to the word-line) and column(bottom electrode, corresponding to the bit-line) inside thecrossbar array was connected through nanoscale (∼300 nm)vias to the output of a specific CMOS decoder unit underneath,as schematically illustrated in Figure 1c. In this integratedsystem, a row decoder enables the selection of a row wire(word line) for connection to the data input (DATA A) viaCMOS pass transistors based on a row−address code input.Unselected rows (whose addresses do not match the inputaddress code) are connected to a separate data input (DATA

Figure 1. (a) SEM image of a crossbar array fabricated on top of a CMOS chip. Scale bar: 5 μm. (b) SEM image of the active crossbar array areashowing 50 nm half pitch and 10 Gbits/cm2 density. Scale bar: 500 nm. (c) Schematic of the hybrid integrated system. Insets: schematic highlightingthe vertical integration of the crossbar array with the on-chip CMOS circuitry. (d) Schematic of the program/read schemes. Each column or row inthe crossbar array is connected to one of the two external signal pads (DATA A for signal applied to the selected column/row, DATA B for signalconnected to the unselected column/row) through CMOS decoder circuits controlled by address I/O pads. (e) I−V switching characteristics from10 different cells in the crossbar array. Insets: I−V switch characteristics plotted in log scale demonstrating current suppression at negative bias in theon-state. (f) Threshold voltage distribution of 256 cells in the fabricated crossbar array. The threshold voltage is defined as the voltage at which themeasured current is above 10−6 A.

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B), as schematically illustrated in Figure 1d. A similarconfiguration exists for the columns (bit lines). With theword- and bit-line combinations selected, the desiredprogramming or read voltage (supplied to DATA A) is appliedacross the selected cell only. All other cells are biased withpredefined protective voltages, grounded, or left floatingthrough DATA B. As a result, the integrated system allowsrandom programming of the 1600 cells inside the 40 × 40 arrayusing only two DATA inputs and five address inputs at eachside (20 rows or columns are connected to decoders on each

side of the array), instead of having to supply 40 × 2 data inputssimultaneously, as is the case without CMOS decoder circuitry.Figure 1e shows the I−V switching characteristics of the

integrated memristor crossbar/CMOS system using theprogramming method described above. Significantly, thefabrication of the memristor crossbar array in BEOL processingdoes not affect the CMOS device performance, and allprogramming and read signals can be passed through theCMOS circuit to the crossbar array as designed. In addition,Figure 1e shows that very similar switching curves can beobtained from devices in the fabricated crossbar array with a

Figure 2. (a) The original black and white 40 × 40 bitmap image representing the University of Michigan logo. (b) The reconstructed bitmap imageobtained by storing and retrieving data in the 40 × 40 crossbar array. (c) A second test image, which is complementary to the original, to be stored inthe array. (d) The reconstructed image, obtained by storing the image in (c) in the same array. (e,f) Histograms of the on- and off-state resistancesfor the data in (b) and (d), respectively.

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narrow threshold voltage distribution. Tight distribution of theswitching characteristics is a prerequisite for the operation ofresistive memories at large scale to avoid accidentalprogramming/erase events during the application of protectiveor read voltages. To further illustrate the switching parameterstatistics, Figure 1f plots the histogram of the threshold voltagesobtained from 256 cells in an array, showing a tight distributionwith an average threshold voltage of 2.30 V and a standarddeviation of 0.07 V. We note that the devices studied here arestrictly speaking memristive devices instead of linear mem-ristors,25 but these two terms are commonly used interchange-ably in the literature and will not be distinguished in this paper.It is also noteworthy that the cells maintain an intrinsic

current-rectifying behavior as shown in Figure 1e (and itsinset), such that the current at reverse bias is pronouncedlysuppressed compared to the current at forward bias, consistentwith earlier reports on similar stand-alone cells.21 It needs to benoted that even though the current through the device issuppressed at relatively small reverse bias, the device remains inthe on-state, and only transitions to the off-state become erasedwith large (e.g., < −1.5 V) negative voltages. This effect isverified in Figure S2, Supporting Information, which shows thatthe on-state is not destroyed with reverse biases up to −1 V.The intrinsic current-rectifying characteristic can effectively

break the sneak current paths (Figure S1b, SupportingInformation) and is a key reason that the array studied herecan operate without having an external transistor or diode ateach crosspoint.To test the operation of the integrated crossbar array, a

binary bitmap image with 1600 pixels (40 × 40) representingthe University of Michigan logo was prepared (Figure 2a, withthe black pixels representing data 0, i.e., the ‘off-state’ and whitepixels representing data 1, i.e., the ‘on-state’). The image wasthen programmed into the 40 × 40 integrated array and readout. For writing ‘1’ into a cell inside the array, a 3.5 V, 100 μspulse was applied across the selected cell through the CMOSdecoder circuit using the protocol discussed above, while theother unselected electrodes in the 40 × 40 array wereconnected to a protective voltage with amplitude equalinghalf of the programming voltage to minimize disturbance ofunselected cells. A similar approach was used for writing ‘0’using a −1.75 V, 100 μs erase pulse. The programming/erasespeed here was mainly limited by the RC delay associated withthe setup and can be significantly improved with integrated on-chip programming and sensing circuitry, as much faster intrinsicprogramming speed has been reported on similar devices.14,21

The programming/erasing was carried out based only on theinput pattern and ignored the existing state of the memory

Figure 3. (a) I−V characteristics of a single cell programmed with four different series resistance values (0.1, 0.5, 1, and 5 MΩ), demonstratingmultilevel capability. (b) Histogram of the on-state resistances for the four target values. The data were collected from 30 different cells, each ofwhich was programmed into all four levels. (c) Measurement diagram for the conventional programming scheme. In this case, the effective seriesresistance seen by the target cell consists of additional current paths through half-selected devices and cannot be predicted beforehand. (d) Newmeasurement diagram that enables multilevel storage in the crossbar array. Parallel current paths through the half-selected devices are blocked due tothe external diodes at the outside and the intrinsic current-rectifying characteristics at each crosspoint. Asymmetric protecting voltages Vpw and Vpbcan be applied to the unselected word- and bit-lines, respectively, to minimize disturbances during programming.

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cells, and a single programming/erase pulse was sufficient foreach cell. Once all data were programmed in an array, theinformation in the array was then read out one cell at a time byapplying a 1 V, 500 μs read pulse across the target cell, whilegrounding all unselected electrodes through the CMOSdecoder. To minimize cell wear out, the 40 × 40 array wasdivided into 25 8 × 8 subarrays, and each subarray wasprogrammed as a whole followed by readout. The 40 × 40 pixelbitmap image was reconstructed by stitching results from the 258 × 8 subarrays together. The resulting image in Figure 2baccurately reflected the initial target image and clearlydemonstrated that by taking advantage of the intrinsicnonlinear I−V characteristics, the integrated crossbar/CMOSsystem could function well without added transistor or diodesas select devices at each cell. Operations based on largersubarrays (e.g., 20 × 20) have also been performed, and resultsare shown in Figure S3, Support Information.To further illustrate the full functionality of the integrated

crossbar array, a complementary image (Figure 2c) of theoriginal was stored into the same array using the sameapproach. The reconstructed image for the complementarybitmap is presented in Figure 2d, verifying every bit in thecrossbar array can be reliably reprogrammed to either the 1 or 0state. The reliability of the memory array is further illustratedby examining the on- and off-state resistance distribution, asplotted in Figure 2e,f for the two cases. Clear separationbetween the 1 and 0 states is obtained, with at least 20×difference in resistance between the worst cases, verifying that

the integrated crossbar/CMOS system can reliably store data atthe array level.In addition, the large on/off ratio offered by the cells (e.g.,

Figure 1e) suggests the possibility for multilevel cell (MLC)storage. Storing multiple levels in a single memory element isnecessary to satisfy the needs of increased storage density and isalso required for many neuromorphic applications for whichresistive switches (memristors) are ideally suited.26 MLCcapability has been demonstrated in resistive memories bycontrolling the current compliance during switching orequivalently by controlling the series resistance the cellsees.27−29 To verify MLC capability for devices in theintegrated system, a single cell in the crossbar array wasprogrammed (with all other cells in the off-state in this case)using different series resistances (0.1, 0.5, 1, and 5 MΩ). Theresults shown in Figure 3a demonstrated that MLC is indeedpossible with the on-state resistance of the cell controlled bythe series resistor value. This multilevel storage effect can beexplained by the self-limiting filament growth model in whichthe filament growth rate is roughly an exponential function ofthe applied voltage across the memory device.27,28 As theresistance of the memory device approaches the seriesresistance value, the voltage across the device is reduced bythe voltage divider effect, and filament growth significantlyslows down resulting in a device resistance determined by theseries resistance.27,28 The reproducibility of the MLC operationis verified in Figure 3b, which plots the resistance distribution

Figure 4. (a) A color 40 × 40 test image with 10 different target levels to be stored in the array. The resistances are represented by the differentcolors as defined in the color scale bar on right. (b) The reconstructed data map from the 40 × 40 array obtained by storing and retrieving the imagein (a) (same color scale). (c) False-color image of the error for the stored data. The error is defined as (Rtarget − Rmeasured)/(Rtarget) and representedby different colors in the color scale bar on right. (d) Histogram of the error values for the stored data.

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from 30 different cells, each programmed into four differentresistance states.However, achieving multilevel storage in crossbar arrays is

inherently much more difficult than achieving binary storage,since the series resistance seen by the target cell (orequivalently, the programming current through it) is affectedby other cells in the array. As illustrated in Figure 3c, thecurrent flowing through the target cell is not only affected bythe external resistor but also by the states of the half-selectedcells sharing the same word-line, i.e., the actual series resistancethe target cell sees is the combination of the external seriesresistance and the resistance of the half-selected cells in parallelwhich cannot be determined beforehand. This effect explainswhy the resistance distributions obtained in the array shown inFigure 2e,f are larger than those shown in Figure 3b forindividual cells and why the distributions are also worse inFigure 2f, which corresponds to a configuration with more cellsin the on-state (and hence, more leakage paths) than those inFigure 2e. To address this problem and block the parallelcurrent paths, we developed a new programming scheme. Inthis approach, schematically illustrated in Figure 3d, externaldiodes (e.g., P6KE15A, Littelfuse Inc. used in this study) areconnected to each unselected bit- and word-line to preventcurrent flow into the external electrodes and to allow only theapplied input voltage signals to path through. Once again, theintrinsic current-rectifying characteristic plays a crucial role inmaking the approach feasible since it prevents current fromflowing backward at the crosspoints to reach the selected bit- orword-line. Combining the intrinsic-rectifying characteristicswith external diodes, current flow through the half-selected cellscan now be fully prohibited, enabling control over current inthe target device during programming for multilevel storagecapability. In addition, since no current flows through the half-selected cells, this approach reduces power consumption whichis another drawback in conventional crossbar array program-ming. For comparison, our simulations (Figure S4, SupportingInformation) show that without the intrinsic current-rectifyingcharacteristics, programming current through the target cellcannot be controlled even with the application of externaldiodes at the unselected electrodes.In the new scheme shown in Figure 3d, since the unselected

bottom electrodes are virtually floated due to the reverse-biaseddiodes, they may be charged up during programming to apotential close to the programming voltage. As a result, theinternal voltage on the unselected bit-lines, Vub shown in Figure3d, may be higher than the externally supplied protectivevoltage Vpb, and during programming the unselected cells canpotentially see large negative voltages (<−1 V) across them. Toreduce this effect, asymmetric protecting voltages were used forthe unselected word- and bit-lines (labeled as Vpw and Vpb,respectively, in Figure 3d with Vpw > Vpb). The exact potentialdistribution across the entire crossbar array was simulated forthe worst case scenario and presented in Figure S5, SupportingInformation. By properly selecting the protective voltages, themaximum negative voltage the unselected cells could see wasshown to be ∼−0.8 V (in the worst case) during programming,not sufficient to disturb the state of the unselected cells.Based on this new programming scheme, a randomly

generated color (multilevel) map with 10 different levels(0.025, 0.05, 0.1, 0.25, 0.5, 0.75, 1, 5, 7.5, and 10 MΩ) aspresented in Figure 4a, was stored into the 40 × 40 array. Eachtarget resistance value was set by a switchable series resistor andprogrammed using a single 3.5 V, 100 μs voltage pulse. A set of

5 × 5 subarrays were programmed, followed by a retrieval of allbits in the subarrays with 1 V, 500 μs read pulses without seriesresistor. The process was repeated to complete the 40 × 40array, and the reconstructed image is presented in Figure 4b.The stored/retrieved image roughly follows the same patternsas the original image; however, some errors are also visible dueto the relatively small spacings between the different resistancevalues used to store the 10 levels. The error, defined as ((Rtarget− Rmeasured)/(Rtarget)), is presented in Figure 4c,d. Overall 75%(1200/1600 cells) of the measured resistance values werewithin 50% of the target value, i.e., 0.5Rtarget < Rmeasured <1.5Rtarget. The apparent asymmetry of the histogram plot shownin Figure 4d is mainly due to the way error is calculated hereusing an asymmetric range from −∞ to 1. For digitalinformation storage, the error reported here is relatively largebut may be improved further by using on-chip integratedcurrent compliance setups instead of an off-chip resistor toreduce parasitic effects. On the other hand, this level of errormay not be a significant problem for neuromorphic applicationsas biological systems typically exhibit similar sized or evenlarger noise.30

In summary, high-density, vertically integrated, hybridmemristor/CMOS systems have demonstrated and functionwell by taking advantage of the intrinsic rectifying I−Vcharacteristics of the switching device itself. Binary bitmapimages were successfully stored and retrieved with considerableread margin. A new programming scheme was developed toallow the integrated crossbar array to store up to 10 differentlevels by eliminating the parallel current paths. Thesedemonstrations verify that it is possible to build high-densityfunctional crossbar arrays without having to incorporateexternal select devices at each crosspoint, and the hybridcrossbar/CMOS systems are well-suited for the proposedfuture data storage and neuromorphic applications.1,7−11

■ ASSOCIATED CONTENT

*S Supporting InformationAdditional supplementary figures showing the sneak pathproblem, the intrinsic rectifying behavior, results obtained fromoperating 20 × 20 subarrays, simulation results, and devicefabrication processes and measurement setups of the integratedsystem. This material is available free of charge via the Internetat http://pubs.acs.org.

■ AUTHOR INFORMATION

Corresponding Author*E-mail: wluee@eecs.umich.edu.

■ ACKNOWLEDGMENTS

This work was supported in part by the DARPA SyNAPSEprogram under contract number HRL0011-09-C-001 and bythe National Science Foundation (NSF) Career award (ECCS-0954621). This work used the Lurie Nanofabrication Facility atthe University of Michigan, a member of the NationalNanotechnology Infrastructure Network (NNIN) funded bythe NSF. The authors acknowledge M. Yung, D. Matthews andA. Soldin for assistance in design of CMOS circuitry. The viewsexpressed are those of the authors and do not reflect the officialpolicy or position of the Department of Defense or the U.S.Government.

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