kitfs6522laeevm, kitfs6523caeevm, and kitfs4503caeevm ... · kitfs6522laeevm, kitfs6523caeevm, and...

NXP SemiconductorsUser’s guide

Document Number: KTFS4500-FS6500UGRev. 1.0, 5/2016

© 2016 NXP B.V.

KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM evaluation boards

Figure 1. FS45xx/FS65xx evaluation board

KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM evaluation boards, Rev. 1.0

2 NXP Semiconductors

Contents

1 Getting started. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.1 Kit contents/packing list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.2 Jump start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.3 Required equipment and software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Getting to know the hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.1 Board overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.2 Board features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52.4 Device features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52.5 Board overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.6 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.7 Jumper settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.8 Test point definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.9 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.10 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3 Configuring the hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183.1 Connecting the hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4 Evaluation board settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194.1 VCCA and VAUX setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194.2 VCORE settings and related configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204.3 MCU settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5 Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245.1 Installing the FlexGUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245.2 Creating and using a register configuration file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255.3 Using the FlexGUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265.4 Use case example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 Board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.1 Assembly layer top . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307.2 Assembly layer bottom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8 Board bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 Accessory item bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3210 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

10.1 Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3310.2 Warranty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34


NXP Semiconductors 3

Getting started

1 Getting started

1.1 Kit contents/packing listThe KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM kit contents include:

• Assembled and tested evaluation boards/modules in anti-static bag• Connector, terminal block plug, 2 pos., str. 3.81 mm• Connector, terminal block plug, 10 pos., str. 3.81 mm• Cable, assy, USB-STD A to USB-B-mini 3.0 ft.• Quick start guide

1.2 Jump startNXP’s analog product development boards provide an easy-to-use platform for evaluating NXP products. The boards support a range of analog, mixed-signal and power solutions. They incorporate monolithic ICs and system-in-package devices that use proven high-volume SMARTMOS technology. NXP products offer longer battery life, a smaller form factor, reduced component counts, lower cost and improved performance in powering state of the art systems.

1. Go to the tool summary page: www.nxp.com/KITFS6522LAEEVM www.nxp.com/KITFS6523CAEEVM www.nxp.com/KITFS4503CAEEVM

2. Review the tool summary page

3. Look for

4. Download the documents, software, and other information

5. Once the files are downloaded, review the user guide in the bundle. The user guide includes setup instructions, BOM, and schematics. Jump start bundles are available on each tool summary page with the most relevant and current information. The information includes everything needed for design.

1.3 Required equipment and software This kit requires the following items:

• Power supply with a range of 8.0 V to 40 V and a current limit set initially to 2.0 A• Standard A plug to Mini-B plug USB cable• FlexGUI graphical user interface• FlexGUI register definition XML file

Jump Start Your Design

http://www.nxp.com/KITFS6522LAEEVM

http://www.nxp.com/KITFS6523CAEEVM




Getting to know the hardware

2 Getting to know the hardware

2.1 Board overviewThe KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM are hardware evaluation tools supporting system designs based on NXP’s FS4500 and FS6500 product families. The kits allow testing the devices as an integral part of the overall system being developed. They provide access to all FS45xx and FS65xx functions (SPI, IOs) and support functional modes such as debug, normal, buck, and boost.

2.2 Board featuresThe main features of the KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM evaluation boards are:

• VBAT power supply either through power jack (2.0 mm) or phoenix connector• VCORE configuration:1.23 V, 3.3 V, and 5.0 V• VCCA configuration:

– 3.3 V or 5.0 V– Internal transistor or external PNP

• VAUX configuration: 3.3 V or 5.0 V• Buck or boost setting• DFS configuration• Ignition key switch• LIN bus (optional)• CAN bus• FS0B• FS1B (Option) • IO connector (IO_0 to IO_5)• Debug connector (SPI bus, CAN digital, LIN digital, RSTB, FS0B, INTB, Debug, MUX_OUT)• Signalling LED to give state of signals or regulators• KL25Z MCU installed on board for easy connection to host computer on USB link

Table 1. Kits supporting the FS45xx/FS65xx family

KIT name Supported silicon Options

KITFS6522LAEEVM (1) MC33FS6522LAE CAN, LIN, No FS1b, VCORE DC/DC 2.2 A

KITFS6523CAEEVM MC33FS6523CAE CAN, FS1b, No LIN, VCORE DC/DC 2.2 A

KITFS4503CAEEVM (1) MC33FS4503CAE CAN, FS1b, No LIN, VCORE LDO 500 mA

Notes1. Prototype only. Contact sales for availability.




2.3 Block diagram

Figure 2. Block diagram

2.4 Device featuresThe FS65xx/FS45xx are multi-output power-regulating SMARTMOS devices aimed at the automotive market. They include CAN flexible data (FD) and/or LIN transceivers.

Multiple switching and linear voltage regulators—including low-power mode (32 μA) — provide a variety of wake-up capabilities. An advanced power management scheme maintains high efficiency over a wide range of input voltages (down to 2.7 V) and output current ranges (up to 2.2 A).

The FS45xx/FS65xx family includes enhanced safety features with multiple fail-safe outputs. The devices are capable of fully supporting safety-oriented system partitioning with a high integrity safety level (up to ASIL D).

The built-in CAN FD (flexible data-rate) interface meets all ISO11898-2 and -5 standards. The LIN interface is compliant with LIN protocol specifications 2.0, 2.1, 2.2, and SAEJ2602-2.

FS54XXFS65XX

MUX_OUT

VCORE

VPRE

FS0/1RST

VSUP

TXC

RXC

CANH

CANL

CANTransceiver

SPIInterfaceUSB to SPI

ADC

IOs

TXL

RXL

LIN/Vpu_fs

LINTransceiver

KL25 MCU

USB Debug

I/O

LIN(Option) CAN

VCCA

VAUX

Regulators

IO1_to_5

PIFilter

VBAT

VPRE

(switching)

VCORE

(switching)

VCCA

PMOS or ext. PNP

VAUX PNP

Power Supply Connector

J33

J23

J36

J4

J8

SW2

SW4KEYIO0

JP1

J37

J30




Table 2. FS45xx/FS65xx features

Device Description Features

FS4500/ FS6500

Automotive control devices

• Battery voltage sensing and MUX output pin

• Highly flexible SMPS pre-regulator, allowing two topologies: non-inverting buck-boost and standard buck

• Switching mode power supply (SMPS) dedicated to MCU core supply, from 1.0 V to 5.0 V, delivering up to 2.2 A

• Linear voltage regulator dedicated to auxiliary functions, or to sensor supply (VCCA tracker or inde-pendent), 5.0 V or 3.3 V

• Linear voltage regulator dedicated to MCU A/D reference voltage or I/Os supply (VCCA), 5.0 V or 3.3 V

• 3.3 V keep alive memory supply available in low-power mode

• Long duration timer available in low-power mode (1.0 s resolution)

• Multiple wake-up sources in low-power mode: CAN, LIN, IOs, LDT

• Five configurable I/Os

MKL25ZKinetis L 32-bit MCU USB controller

• Regulator voltage read back (via ADC)

• SPI command and control

• IO checking

• CAN and LIN TX signal support

• MCU disconnect capability




2.5 Board overviewThe primary components of the evaluation boards are the onboard MCUs. The boards include an FS45xx or FS65xx and provide full access to all the device’s features. An MKL25Z MCU USB controller enables access to the FS45xx/FS65xx through a USB connection.

In normal operation, configuration and monitoring applies to the on-board FS45xx/FS65xx device. However, the board can be totally isolated from the on-board MCU. This allows connection to an off-board MCU without interference from the on-board device functions.

Figure 3. Board description

Table 3. Board description

Number Description

1 VBAT connectors — Use either jack connector or Phoenix connector to supply board

2 VBAT switch — Select VBAT from jack or from Phoenix connector

3 Ignition key — Ignition key from car

4 LIN bus — LIN bus connector

5 CAN bus — CAN bus connector

6 I/Os — Input and Output from FS45XX/FS65XX (IO0, IO2, IO3, IO4, IO5, GND, VKAM, VDDIO, VBAT)

7 DBG mode select

8 Debug connector — Could be used for debug purpose (CAN TX/RX, LIN TX/RX, SPI, Debug, FS0B, FS1B, INTB)

9 VCCA & VAUX selection — Select 3.3 V/5.5 V configuration for VCCA & VAUX

10 MCU to FS65/FS45 connection — Connects part or totality of signals between the KL25Z MCU and FS65XX/FS45XX.

11 KL25 MCU — Location of MCU and USB connector for control through FlexGUI

12 DFS mode select — Enables or disables the deep fail-safe function

1

2

3

4

5

6 7 8 9 10

11

12

13

14

15161718




13 VCORE selection — Selects either 1.23, 3.3, or 5.0 V on VCORE DC/DC

14 Compensation network — Selects either Network 1 or 2

15 Power supplies LED — Visualizes regulator state (on or off). The switches can disconnect LEDs

16 Power supplies — Connector for power supplies (CAN_5V/VPRE/VCORE/VCCA/VAUX)

17 Buck/buck or boost selection — These jumpers select VPRE mode as a buck or buck or boost.

18 FS45xx/FS65xx

Table 3. Board description (continued)

Number Description




2.6 LEDsThe LEDs are located on the board as shown in Figure 4.

Figure 4. LEDs

The LEDs can be switched on or off through jumpers or switches. Table 4 shows the function of all LEDs.

Table 4. LEDs

Schematic label Name Color LED activation Description

D1 VPRE Green D1/SW1-1 VPRE on

D3 VAUX Green D3/SW1-2 VAUX on

D4 VCCA Green D4/SW1-3 VCCA on

D5 VCORE Green D5/SW1-4 VCORE on

D10 IO_4 Green D10/J21-2/3 IO_4 high level

D11 KEY Green D11/J16 Ignition key switch to VSUP3 (tied to IO_0)

D13 RSTB Red D13/J25 RSTB asserted (logic level = 0)

D14 INTB Red D14/J28 INTB asserted (logic level = 0)

D15 P3V3_KL25 Green D15/NA MCU KL25 power supply ON

D17 CAN_5V Green D17/J27 CAN_5V ON

D18 VBAT Green D18/J28 VBAT ON

D20 FS0B Red D20/J39 FS0B asserted (logic level = 0)

D21 FS1B Red D21/J40 FS1B asserted (logic level = 0)

CAN_5V

Vbat

FS1b

FS0b

RSTbKEY

INTb

VpreVauxVccaVCor

e

IO_0

P3V3_KL25

Green LED Red LED




2.7 Jumper settingsFigure 5 shows the location of all jumpers on the board. Table 5 provides the name and function of each jumper.

Figure 5. Jumpers

Table 5. Jumper settings

Schematic label Function Pin Number Jumper/pin function

JI VCORE load 1-2 Connect 30 Ω resistor load on VCORE

J2 VPRE mode1-2 Both jumper plugged: VPRE Buck configuration

Both jumper unplugged: VPRE Boost configuration3-4

J3 VPRE load 1-2 Connect 60 Ω resistor load on VPRE

J5 VDDIO selection

1-2 VDDIO referenced to VCCA

2-3VDDIO referenced to VCORE or P3V3_KL25Z. Configuration is selected with R106 or R107, respectively VCORE or P3V3_KL25Z

J6 VCORE output capacitor 1-2 VCORE output capacitance. When set, adds 20 µF on VCORE.

J7Comp. network1 1-2 Select compensation network1. Used in conjunction with J10:1-2

Comp. network2 3-4 Select compensation network2. Used in conjunction with J10:3-4

J9VCCA PNP External PNP used Used in conjunction with J11:1-2

VCCA MOS 1-2 Internal MOS used Used in conjunction with J11:2-3

J10Comp. network1 1-2 Select compensation network1. Used in conjunction with J7:1-2

Comp. network2 3-4 Select compensation network2. Used in conjunction with J7:3-4

J11VCCA PNP 1-2 External PNP used in conjunction with J11:1-2

VCCA MOS 2-3 Internal MOS used in conjunction with J11:2-3

J12VSUP1-2 1-2 Connect VSUP1 and VSUP2 to the power supply on the output of PI filter

VSUP3 3-4 Connect VSUP3 to the power supply (before PI filter)

SW3

SW6

SW5

Jumper




J13 VCORE setting

1-2 VCORE = 1.23 V

3-4 VCORE = 3.3 V

5-6 VCORE = 5.0 V

J14 VSENSE 1-2 Connect VSENSE to VBAT

J15 Debug mode 1-2 ON: Debug mode off: normal mode

J16 KEY LED 1-2 Enable KEY signaling LED

J18 DFS1-2 DFS enabled

2-3 DFS disabled

J21 IO_41-2 IO_4 tied to GND through 510 k

2-3 IO_4wired on LED signaling works in conjunction with J19:1-2

J22IO_5 1-2 Connect IO_5 to KL25Z and I/O connector (J36-5)

VKAM 2-3 Connect VKAM to I/O connector(J36-8) and 220 nF capacitor.

J25 RSTB 1-2 Enable RSTB signaling LED

J26 INTB 1-2 Enable INTB signaling LED

J27 CAN_5V 1-2 Enable CAN_5V signaling LED

J28 VBAT 1-2 Enable VBAT signaling LED

J31 VCORE drift

1-2 VCORE = 1.23 V

3-4 VCORE = 3.3 V

5-6 VCORE = 5.0 V

J32 FCRBM1-2 Connect FB_Core to FCRBM

2-3 Connect potentiometer R40 to FCRBM

J35 IO-0 1-2 Connect IO_0 to ground through 510 k

J38 FS0B Pull-up1-2 FS0b pull-up connected to VSUP3

2-3 FS0b pull-up connected to VDDIO

J39 FS0B LED 1-2 Enable FS0B signaling LED

J40 FS1B LED 1-2 Enable VPU FS signaling LED (FS1B)

J41 VCORE 1 SMB connector on VCORE

J42 VPRE 1 SMB connector on VPRE

J43 IO_5 1-2 Connect IO_5 to ground through 5.1 k

Table 5. Jumper settings (continued)

Schematic label Function Pin Number Jumper/pin function




2.8 Test point definitionsFigure 6 shows the location of the test points on the board.

Figure 6. Test points

The following test points provide access to various signals to and from the board.

Table 6. Test points

Schematic label Signal name Schematic label/description

TP1 GND Ground

TP2 GND Ground

TP3 VPRE TP3/VPRE regulator output voltage

TP4 GND Ground

TP5 CAN_5V TP5/CAN power supply

TP6 GND Ground

TP7 VAUX TP7/VAUX output voltage

TP8 GND Ground

TP9 VCCA TP9/VCCA output voltage

TP10 PGND TP10/power ground

TP11 VCORE TP11/VCORE output voltage

TP12 GND Ground

TP13 GND Ground

TP14 PGND Power ground

TP15 VSW_PRE TP15/VPRE switcher signal

TP16 VSUP3 TP16/VSUP3 voltage

TP17 GND Ground

INTb

MU

X_O

UT

FS0b

FS1b

RSTb

CANL

CANH

LIN

GND

Vsup3

PGND

GND

Vpre

Vcor

e

Vaux

Vcca

CAN

_5V

VSW_Pre

VSW_Core

GND

GND

P5V0

_USB

_VBU

S

SELECT

FCRBM

GND

TC_U

SB_I

D_TP




2.9 ConnectorsFigure 7 shows the location of connectors on the board. Table 7 and Table 8 list the pin-outs for each connector.

Figure 7. Connectors

TP18 VSW_Core TP18/Vcore switcher

TP19 SELECT TP19/SELECT pin voltage

TP20 TC_USB_ID_TP TP20/USB Identification pin

TP21 LIN TP21/LIN bus signal

TP22 GND Ground

TP23 FCRBM TP23/feedback core resistor bridge monitoring

TP24 CANH TP24/CAN high

TP25 CANL TP25/CAN low

TP26 MUX_OUT TP26/MUX_OUT signal

TP27 INTB TP27/INTB/interrupt pin level. Active low

TP28 RSTB TP28/Reset. Active low

TP29 FS1B TP29/fail-safe 1 signal. Active low

TP30 FS0B TP30/fail-safe 0 signal. Active low

TP31 GND Ground

TP32 P5V_USB_CONN_VBUS TP32/USB power supply level

TP33 GND Ground

Table 6. Test points (continued)

Schematic label Signal name Schematic label/description

Power Supply

Vbat(Jack)

Vbat(Phoenix)

CAN

LIN

I/Os Debug

USB

SWD




2.9.1 VBAT connectors (J4 and J8)VBAT connects to the board either through jack connector (J4) or Phoenix connector (J8) at the user’s discretion. Switch SW2 switches from one source to the other.

2.9.2 Debug connector (J37)The Debug connector (J37) gives access to the FS65xx main signal for debug or experimentation purposes.

Table 7. VBAT jack connector (J4)

Pin number Connection Description

1 VBAT Connects to VBAT when switch SW2 is set to VBAT

2 Ground Connects to ground when switch SW2 is set to ground

Table 8. VBAT Phoenix connector (J8)


1 VBAT Connects to VBAT when switch SW2 is set to VBAT

2 Ground Connects to ground when switch SW2 is set to ground

Table 9. Debug connector (J37)


1 FSOB Fail-safe 0.

2 VDDIO Reference voltage for IOs.

3 MISO SPI, Master Input Slave Output

4 RSTB Reset, active low

5 MOSI SPI Master Output Slave Input

6 GND Ground

7 SCLK SPI serial clock

8 GND Ground

9 NCSB SPI chip select, active low.

10 GND Ground

11 MUX_OUT Multiplexer output

12 INTB Interrupt output. Active low.

13 RXD_L LIN receiver data. Logic level.

14 TXD_L LIN transmit data. Logic level.

15 GND Ground

16 FS1B Fail-safe 1

17 RXD CAN receiver data. Logic level

18 TXD CAN transmit data. Logic Level

19 DBG Debug pin selection

20 GND Ground




2.9.3 LIN connector (J23)The LIN connector is mounted on all three kits, but LIN is supported only on the KITFS6522LAEEVM.

2.9.4 CAN connector (J30)

2.9.5 USB connector (J33)The USB connector provides a communication link between the evaluation board’s MKL25Z device and a PC running the FlexGUI software.

2.9.6 I/O connector (J36)The I/O connector accesses the device under test (DUT) IO and VKAM signals.

Table 10. LIN connector (J23)


1 LIN Connects to the LIN bus

2 GND Connects to ground.

Table 11. CAN connector (J30)


1 CANH Connects to the CANH bus line

2 CANL Connects to CANL bus line

Table 12. USB connector (J33)


1 P5V0_USB_CONN_VBUS +5.0 V DC supply

2 USB_CONN_DN Data–

3 USB_CONN_DP Data+

4 TC_USB_ID_TP USB OTG ID

5 GND Ground

Table 13. I/O connector (J36)


1 Not connected Not connected

2 IO_0 Input/Output 0





7 VDDIO Reference voltage for IOs.

8 VKAM Keep alive memory voltage

9 VBAT Battery voltage

10 GND Ground




2.9.7 Power supply connector (JP1)The power supply connector (JP1) connects any of the SBC regulators to an external load or board for evaluation purposes.

2.10 Switches

Figure 8. Switches

Table 14. Power supply connector (JP1)


1 CAN_5V CAN voltage regulator

2 GND Ground

3 VCCA VCCA output voltage

4 GND Ground

5 VAUX VAUX auxiliary voltage regulator

6 GND Ground

7 VCORE VCORE voltage output

8 GND Ground

9 VPRE VPRE regulator output regulator

10 GND Ground

SW3

SW6

SW5

SwitchesONOFF




2.10.1 SW3

2.10.2 SW5

2.10.3 SW6

Table 15. SW3

Position Function Description

1 IO_O Connection between IO_O from product to MCU

2 NA Not used

3 IO_2 Connection between IO_2 from product to MCU




Table 16. SW5

Switch VCCA VAUX

1 – 8 3.3 V 3.3 V

2 – 7 5.0 V 5.0 V

3 – 6 3.3 V 5.0 V

4 – 5 5.0 V 3.3 V

Table 17. SW6


1 RSTB Connection between RSTB from product to MCU

2 FS0B Connection between FS0B from product to MCU


4 DBG Connection between DBG from product to MCU



Configuring the hardware

3 Configuring the hardware

3.1 Connecting the hardwareThe KITFS6522LAEEVM/KITFS6523CAEEVM/KITFS4503CAEEVM must be connected to a PC through the USB port on the board. A 13.5 V power supply connects either to a jack connector (J4) or a Phoenix connector (J8). The evaluation board connects to an external load or another board through connector JP1.

Caution:

To avoid damaging the board, the VBAT voltage must not exceed 40 V.

1. With the power switched off, attach the DC power supply to either the Jack connector (J4) or the Phoenix connector (J8) on the evaluation board. (There is no difference between the two connectors other than plug compatibility.)

2. Attach a load or an external board through connector JP1.

3. Connect a USB cable from the evaluation board USB port (J33) to the USB port on a PC with the FlexGUI installed.

4. Turn on the DC power supply.

Figure 9 illustrates the hardware configuration.

Figure 9. Evaluation board hardware configuration

13.5 V Power Supply

+

USBPortJ33

USB Cable -

ConnectorJ4 or J8

KITFS4503CAEEVM/ KITFS6522LAEEVM/KITFS6523CAEEVM

FS65XX / FS45XX regulator output

External Load/Board(Resistor Load or MCU power Supply)

PC with FlexGUI software installed



Evaluation board settings

4 Evaluation board settings

4.1 VCCA and VAUX settingTo select various voltage levels on VCCA and VAUX, set the switch SW5 as shown in Table 18 and Figure 10 below:

Figure 10. VCCA and VAUX voltage settings

VCCA regulator can be configured to use the internal PMOS transistor at current levels up to 100 mA. To achieve higher current levels (up to 300 mA), use a PNP external transistor. Table 19 and Figure 11 show the jumper settings for both configurations.

Figure 11. VCCA transistor setting

The VCCA regulator is always tied to the external PNP transistor. Resistors R105 and R10 limit the power dissipation in the PNP transistor.

Table 18. SW5 VCCA/VAUX voltage configurations

Switch VCCA VAUX

1 – 8 3.3 V 3.3 V

2 – 7 5.0 V 5.0 V

3 – 6 3.3 V 5.0 V

4 – 5 5.0 V 3.3 V

Table 19. J9/J11 VCCA PNP configurations

Jumper J9 J11

Internal MOS OFF 2 – 3

External PNP ON 1 – 2

J18

123

R65 12KR64 24K

SW51234

8765

Vpre

R66 5.1K

GNDR63 51K

SELECT

Q50PHPT60603PY

4

15

2 3

VCCA_B

J9

1 2

Vcca_E

Vcca

Vpre

J11

123

C534.7uF

Vcca [4]

GND




Figure 12. VAUX external transistor

4.2 VCORE settings and related configurations

4.2.1 VCORE and F45xx versus FS65xxThe FS45xx family of devices only support VCORE LDO (low dropout) voltage regulators. The FS65xx family only supports VCORE DC/DC voltage regulators. The evaluation board circuitry accommodates this discrepancy by implementing a separate circuit network for each of the two device families. Populating or not populating resistors R7 and R8 depend on which device family is in use and determines which network is enabled.

For the FS45xx family, R7 is populated and R8 is not populated. For the FS65xx family, R8 is populated and R7 is not populated. Because resistor R8 is not populated for FS45xx devices, the compensation network is also disabled for those devices. See Figure 13.

Figure 13. VCORE configuration

Q51PHPT60603PY

4

15

2 3

Vaux

Vaux_B

Vaux_E

C564.7uF

Vaux [4]

GN D

R109 2.4

R105 for Vaux = 5VR109 for Vaux = 3.3V

R105 0

C 110uF

J 13

12

34 6

5

C 522uF

V core

C 210uF

R5

84

3K

R 5115

R 5215

D 7P MEG3030B EPA

C

P GN D

5 - 6 Vcore = 5.0V

3 - 4

1 - 2 Comp. Network 1

J7/J10

Comp. Network 2GN D

VSW _C ore

R 1215

FB _C ore

Product with Vcore DC/DC only (FS65XX)

Product with Vcore LDO only (FS45XX)

R 5739K

C 7 150pF

R 8 0

C 3680P F

J 612

J 1

H D R 1X2

12

1 - 2

3 - 4

Vc ore [4]

Vcore = 3.3V

Vcore = 1.23V

B oos t _c ore

PGN D

PGN D

PGN D

C 190. 1UF

L4 2. 2uH1 2

R1

54

.32

K

R 98. 06K

R 10200

R13

24.

9K

C 15180PF

C 52 1000PF

R 6510

C 4220PF

R 5618K

C 910nF J7

1

2

3

4

J 10

1 23 4

C om p_core

R7 0DN P

FB _C ore

J13

PGN D

Vcore




4.2.2 Compensation networkBoth LDO and DC/DC voltage regulators use VCORE voltage feedback to control the output voltage. For this reason, two separate external bridges enable feedback support for either FS45xx or FS65xx devices (see Figure 13).

For FS45xx devices using static (steady-state) LDO regulators, a simple resistor bridge (resistors R15/R13/R58 and R9) in conjunction with jumper settings on jumper J13 determines the feedback voltage.

For FS65xx devices using DC/DC voltage regulators, a selectable pair of RC voltage dividers control the dynamic behavior of the regulator. One RC divider --compensation network 1-- consists of the resistor-capacitor series R10/C4/R57/C52. The other RC divider --compensation network 2-- consists of the resistor-capacitor series R6/C3/R56/C7. Jumpers J7 and J10 select which of the two compensation networks is enabled.

The default value for compensation network 1 is 1.23 V. For compensation network 2, the default value is 3.3 V. These values can be changed for other configurations. The compensation network tool referenced in Table 26 is useful in calculating the appropriate values.

Table 20 illustrates the jumper settings for each feedback voltage level.

4.2.3 FCRBM resistor bridgeThe feedback core bridge monitoring (FCRBM) resistor bridge is an evaluation board safety feature.

The bridge generates the same voltage as the bridge connected to the FB_core pin. If the difference between the two voltages is greater than the VCORE_FB_DRIFT value, the FS state machine is impacted (refer to data sheet).

To implement this functionality, use jumper J31 to configure the second resistor bridge as shown in Figure 14. Then, set the potentiometer R40 to match the voltage of the first VCORE bridge.

To disable the FCRBM function, place a jumper on position 1–2 of J32. This connects FB_CORE directly to the FCRBM bridge, causing the drift to be zero.

Figure 14. FCRBM bridge resistor

Table 20. VCORE compensation network settings

Jumper setting

Static behavior Dynamic behavior

VCORE J13 J7 J10

1.23 V 1–2 1–2 1–2

3.3 V 3–4 3–4 3–4

5.0 V 5–6 (2) (2)

Notes2. Use compensation network tool to calculate value

R32

4.3

2K

R3

32

4.9

K

R405. 0K

13

2

R425. 6K

J31

12

34 6

5

J 32

123

1 - 2 Vcore = 1.23V

3 - 4 Vcore = 3.3V

J31VcoreFB Drift

5 - 6 Vcore = 5V

V core

R6

043

K

FC RB MFB_C ore

GND




4.3 MCU settings

4.3.1 MCU jumper configuration

Figure 15. MCU jumper configuration

4.3.2 MCU switch configuration

4.3.2.1 Switch SW3

Table 21. MCU Jumper configuration

Schematic label Pin number Function Jumper/pin function

J24

1–2

SPI

Connect MISO to KL25Z

3–4 Connect MOSI to KL25Z

5–6 Connect MSCLK to KL25Z

7–8 Connect NCSB to KL25Z

J291–2

LINConnect RXD_L LIN to KL25Z

3–4 Connect TXD_L LIN to KL25Z

J341–2

CANConnect RXD CAN to KL25Z

3–4 Connect RXD CAN to KL25Z

Table 22. Switch SW3


1 IO_O Connection between IO_O from product to MCU

2 NA Not used





J29

HDR 2X2

1 23 4

RXD_L_SH

J24

HDR_2X4

1 23 4

657 8

TXD_L_SW

MISO[3]MOSI[3]

NCSb[3]SCLK[3]

J34HDR 2X2

1 23 4

RXD_SHTXD_MCU

CAN

RXD[3]

TXD_L[3]

TXD[3]

SPI

NCSb_MCUSCLK_MCUMOSI_MCUMISO_SH

RXD_L[3]

LIN




Figure 16. Switch SW3

4.3.2.2 Switch SW6

Figure 17. Switch SW6

4.3.3 MCU analog inputTo assure the complete isolation of analog signals connected from an external component to the MCU, remove input resistance as applicable for the following:

• VPRE tied to MCU through R82• VCORE tied to MCU through R89• VAUX tied to MCU through R90• VCCA tied to MCU through R82• CAN_5V tied to MCU through R80• MUX_OUT tied to MCU through R71• VDDIO tied to MCU through R70• VKAM tied to MCU through R79

Table 23. Switch SW6


1 RSTB Connection between RSTB from product to MCU



4 DBG Connection between DBG from product to MCU

IO_4[ 3]IO_5[ 3]

I O_0[3]

I O_2[3]I O_3[3]

SW3

SW_DIP-6_SM

123456

121110987

IO_SW_2

IO_SW_0

IO_SW_5IO_SW_4IO_SW_3

SW6

SW DI P-4/SM

1234

8765

R STb[3]FS0b[3]FS1b[3]D BG[3]

DBG_SWFS1b_SWFS0b_SWRSTb_SW



Software

5 SoftwareThe KITFS6522LAEEVM/KITFS6523CAEEVM/KITFS4503CAEEVM is bundled with software allowing the user to interact directly with the onboard MCU during the development process. The boards contain an MKL25Z Kinetis processor pre-loaded with firmware controlling communication with the FS45xx/FS65xx MCU. A graphical user interface installed on a PC serves as the user interface to the evaluation board. When connecting the evaluation board to a PC through a USB cable, the following data exchanges are available:

• SPI access (read and write) to FS45xx/FS65xx• ADC readout, connected to regulators

– VPRE– VCORE– VAUX– VCCA– CAN_5V– MUX_OUT– VDDIO– VKAM

• I/O readout, connected to IO_0 to IO_5• FS0B/FS1B readout• RSTB readout• CAN generated TX signal• LIN generated TX signal with loopback checking

Note that MCU connections to FS45XX/FS65XX can be fully isolated by removing related jumpers and switching off the related switch.

The software bundle also includes an XML file containing register descriptions for the FS45xx or FS65XX (depending on the evaluation board). This file must be installed for the GUI to work properly. In addition, an optional Excel file can be created to facilitate setting several registers at a click.

Figure 18. Software overview

5.1 Installing the FlexGUIThe FlexGUI graphical user interface provides a PC-based interface for accessing the evaluation board and exercising FS45xx/FS65xx functions. The GUI runs on any Windows 8, Windows 7, Vista, or XP-based operating system.

To install the FlexGUI software:

1. Go to the evaluation board tool summary page

2. Under Jump Start Your Design, click on the Get Started with the KITFS65xx link.

3. From the list of files that appear, click on the FlexGUI link. The software downloads to the PC and initiates the installation. An installation wizard guides the user through the process. Upon completion, the GUI executable (FlexGUI.exe), and the relevant register description XML file are installed on the system.

4. To simplify launching the FlexGUI, create a .bat file with the following commands:

C:\Program Files (x86)\FlexGUI\bin\FlexGUI.exe

C:\Program Files (x86)\FlexGUI\Sequences&Config\FSxxxx.xml

MKL25Z

Pre-loadedfirmware

KITxxx evaluation board

FS45xx/FS65xx FlexGUIFS45xx/FS65xx

Windows Laptop

FSxxxx.xml

MyRegs.xlsUSB



Software

5.2 Creating and using a register configuration fileCreating an Excel register configuration file allows the user to initialize the evaluation board MCU with a predefined set of register values. To create a register configuration file, do the following:

1. Open a new Excel spreadsheet file and label the first three columns in row 1 hex, registers and comment. Notice that the first two columns —hex and registers— are mandatory. The comment column is optional.

2. In the hex column (column A), enter the data or address to be assigned to each register. The address and data must be contained in two bytes and must be expressed as a hexadecimal value. Enter one row per register.

3. In the registers column (column B), enter the register name associated with the value in the hex column.

4. In the comments column (column C), enter any comments desired. Data in this column is not processed by the FlexGUI.

Figure 19 illustrates a typical register configuration file.

Figure 19. Register configuration Excel file

5. Launch FlexGUI. When FlexGUI opens, click the load sequence button to load the register configuration file (see Figure 20).

Figure 20. Loading the register configuration example file

Mandatory Optional

1 2



Software

6. Send the resister configuration file to the FS45xx/FS65xx by clicking the send sequence button (see Figure 20).

5.3 Using the FlexGUITo start the FlexGUI, do the following:

1. Configure the hardware as described in Section 3.1, Connecting the hardware.

2. To launch the FlexGUI, execute the .bat file created in Section 5.1, Installing the FlexGUI.

5.4 Use case exampleThis example assumes the user has configured the hardware as shown in Figure 9 and put the evaluation board into debug mode by placing a connector on jumper J15 (see Table 5). After launching the FlexGUI, the example configures registers to disable IO_23_FS safety mode, disable the watchdog and release the FSx pins.

1. Create an Excel file configured as shown in Table 24. For details on creating an Excel register configuration file, see Section 5.2, Creating and using a register configuration file.

2. To use the register configuration file, open FlexGUI, then load the register configuration file and send it to the evaluation board (see Figure 20).

Now read or write any bit from the FS45xx/FS65xx on-board MCU as shown in Table 21.

Figure 21. FlexGUI register window

Register values display in the register value window as shown in Figure 22.

Table 24. Use case register configuration Excel file example

HEX Registers Comment

C424 BIST ABIST2_VAUX enabled => Start VAUX ABIST

CB0C INIT_FSSM IO_23_FS Disabled

8900 INIT_INT Close main machine initialization sequence

D34D WD_refresh_0 1st Watchdog refresh answer

D29B WD_refresh_1 2nd Watchdog refresh answer

D237 WD_refresh_2 3rd Watchdog refresh answer

D26E WD_refresh_3 4th Watchdog refresh answer

D2DC WD_refresh_4 5th Watchdog refresh answer

D2B9 WD_refresh_5 6th Watchdog refresh answer

D372 WD_refresh_6 7th Watchdog refresh answer

D4A7 RELEASE_FSxB Release FS0B & FS1B pins



Software

Figure 22. FlexGUI register value window



Schematic

6 Schematic

Figure 23. Evaluation board schematic

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Vcca

Vaux

J18

DEEP FAIL SAFE mode select

Jumper

Regulator

DFS Disabled

DFS Enabled

1-2

CAN

LIN

Power Supply

DEBUG

SW5

Vcca/Vaux Voltages config.

SWITCH

53.3

1-8

2-7

3-6

4-5

3.3

5553.3

3.3

Vcca

2-3

Populated on product

with LIN Option only

Vbat

Vcor

e_se

nse

ON

OFF

J15-DEBUG MODE

DEBUG

NORMAL

1 - 2

3 - 4

Vcore = 1.23V

Vcore = 3.3V

J31

VcoreFB Drift

5 - 6

Vcore = 5V

Contact KEY

Vsup

3

��

Vsup

12

J2-Vpre mode

1-2 & 3-4

Jumpers off

Buck or Boost

Buck only

Vbat Jack

Product with Vcore DC/DC only

Product with Vcore LDO only

1 - 2

3 - 4

Vcore = 1.23V

Vcore = 3.3V

J13

Vcore

Test Points

I/O

LED Signalling

INGNITION

5 - 6

Vcore = 5.0V

1 - 2

3 - 4

Comp. Network 1

J7/J10

Comp. Network 2

Vaux

J11

J9 / J11

Vcca PNP Config.

Jumper

Int MOS

Ext PNP

1-2

ON

OFF

2-3

J9

LIN

Prod

uct

:-

R29

: Po

pula

ted

- R9

8 /

R108

/ C

24 D

NP-

R69

: DN

P-

R17

: Po

pula

ted

FS1b

Pro

duct

s :

- R2

9 :

DNP.

- R9

8 /

R108

/ C

24 :

Pop

ulat

ed-

R69

: Po

pula

ted

- R1

7 :

DNP

R105 for Vaux = 5V

R109 for Vaux = 3.3V

D57 & C93 as close

as possible to the IC

J5 - VDDIO Voltage Selection

FS0b

Vaux

_B

Vaux

_E

Vcca

_E

CAN

H

SELE

CT

LIN

MU

X_O

UT

DBG

MIS

O

SCLK

INTb

FS1b

VCC

A_B

FS0_

b

MO

SI

NC

Sb

RXD

_L

RXD

RST

b

TXD

_L

TXD

VSW

_Pre

FS0_

b

TXD

FCR

BM

FS_P

U

INTb

KEY

IO_0

Vsen

se

Vsup

Vsen

se

DBG

CAN

HC

ANL

Vkam

_IO

5

VCCAVCCA_BVCCA_EVAUX_EVAUX_BVAUX R

XD

TXD

L_Vp

uFS1

b

FB_C

ore

Boos

t_co

re

Com

p_co

re

FB_C

ore

INTb

VSW

_Cor

e

FCR

BM

SELE

CT

CAN

H

CAN

L

LIN

FS0b

MU

X_O

UT

RST

b

VSW

_Pre

IO_0

IO_4

IO_3

IO_5

RST

b

INTb

IO_4

Vkam

_IO

5

FS1b

FS_P

UTX

DL_

VpuF

S1b

IO_2

FCR

BMFB

_Cor

e

IO_5

LIN

FS1b

FB_c

ore

Boos

t_co

reVS

W_C

ore

Com

p_co

re

SELE

CT

VSW

_Cor

e

CAN

L

Vkam PG

ND

PGN

D

PGN

D

PGN

D

PGN

D

PGN

D

PGN

DPG

ND

PGN

D

PGN

DPG

ND

PGN

D

PGN

D

PGN

D

PGN

D

PGN

D

PGN

D

PGN

D

PGN

D

PGN

DPG

ND

PGN

D

PGN

D

PGN

DPG

ND

Vsup

3

Vsup

3Vb

at

Vsup

3

Vcor

e

CAN

_5V

Vpre

Vsup

3

VDD

IO

Vcca

VDD

IOVc

ore

P3V3

_KL2

5Z

VDD

IO

Vcor

e

CAN

_5V

CAN

_5V

CAN

_5V

Vpre

Vpre

Vcca

Vaux

Vcor

e

KEY

Vaux

Vpre

Vcca

Vcor

e

Vaux

Vaux

Vpre

Vcca

CAN

_5V

Vsup

3

Vcor

e

Vbat

VDD

IOVDD

IO

Vbat

Vcca

Vcor

e

VDD

IO

VDD

IO

VDD

IO

Vpre

Vpre

Vpre

Vpre

Vpre

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

D

GN

D

GN

D

GN

DG

ND

GN

D

GN

DG

ND

GN

D

GN

D

GN

DG

ND

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

DG

ND

GN

DG

ND

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D GN

D

GN

D

GN

DG

ND

GN

D

GN

D

GN

D

GN

D

Vpre

GN

D

Vcca

[4]

Vaux

[4]

MO

SI[4

]M

ISO

[4]

SCLK

[4]

NC

Sb[4

]

IO_0

[4]

IO_4

[4]

IO_2

[4]

IO_3

[4]

FS0b

[4]

Vpre

[4]

Vddi

o[4

]

CAN

_5V

[4]

RXD

_L[4

]

Vcor

e[4

]

RST

b[4

]

Vkam

[4]

DBG

[4]

RXD

[4]

TXD

[4]

TXD

_L[4

]

IO_5

[4]

FS1b

[3,4

]

FS1b

[3,4

]M

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___

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X

C20

1000

PF

R81

11.0

K

TP25

SW2

123

S1S2

TP12

J15

12

R6043K

R10

251

0K

Q2

NX3

008N

BK

1

23

TP17

C164.7uF

C55

10nF

DN

P

J39

12

R23

510K

C63

1000

PFD

NP

R97

510K

J12

12

34

R43

510K

L3MPZ

1608

S101

A

12

Q1

BUK9

832-

55A

1

324

TP5

C59

10nF

DN

P

C52

1000

PF

R10

15.

6K

SW1

1 2 3 4

8 7 6 5

R10

7 0D

NP

BH3

MTG

1

J22

123

TP18

TP31

SW4

500S

SP3S

1M6Q

EA

123

S1S2

R2

1.5K

J13

1234

6 5

Q51

PHPT

6060

3PY

4

1 523

D11

LED

/GR

N

AC

C3

680P

F

R94

5.1K

R93

10K

TP4

DN

P1

R10

50

R8

0

TP2

DN

P1

C91

0.47

UF

R30

1.5K

R7

0D

NP

1

J41

DN

P

TP21

R29

0

C124.7uF

R36

120

R6

510

J32

123

R10

60

R17

0

R55

30

R76

5.1K

D56

BZT5

2H-B

18

AC

R57

39K

TP16

R69

0D

NP

C51

0.22

uF

R66

5.1K

C21

2.2U

F

D2

SS24

T3G

AC

L42.

2uH

12

R10

816

.2K

R10

92.

4

TP26

J10

12

34

R95

5.1K

R51

15

J61 2

1

J42

DN

P

C5

22uF

C18

0.1U

F

C6

22uF

R96

10K

D12

1N41

48W

SA

C

BH1

MTG

1

R5843K

+ C1747uF

BH2

MTG

1

R28

0

J3

HD

R 1

X2

1 2

J9

12

TP3

TP30

J23

PLU

G_1

X2

1 2

J31

1234

6 5

C7

150p

F

C50

0.1U

F

D57

BZT5

2H-C

20

AC

D4

LED

/GR

NA

C

C4

220P

F

R98

10K

DN

P

R154.32K

R19

1.5K

J40

12

R11

051

0K

TP23

R10

310

K

L21u

H1

2

R52

15

Q3

BSS8

4LT1

1

32

R10

45.

1K

C26

10nF

DN

P

TP28

D17

LED

/GR

N

AC

TP13

J43

1 2

J81 2

C13

22uF

J36

12

34 6

5 78

910

C57

1uF

R3

560

C5410nFDNP

C1110nFDNP

D13

RED

A C

C28

10nF

J28

12

TP29

R37

560

R4

560

C1010nFDNP

D8

PMEG10030ELPA C

R14

10K

R56

18K

TP27

R24

2K

J16

12

J11

123

R9

8.06

K

D1

LED

/GR

NA

C

C29

1000

PF

TP6

DN

P1

U55

MC

33FS

6522

LAE

CAN

_5V

7

CAN

H8

IO_5

/VKA

M11

IO_4

10

GN

D_C

OM

6

CAN

L9

IO_0

12

LIN

5

VSU

P11

VSU

P22

VSEN

SE3

VSU

P34

FCRBM13

FS014

DEBUG15

AGND16

MUX_OUT17

IO_218

IO_319

TXD20

RXD21

TXDL22

RXDL23

RST24

MIS

O25

MO

SI26

SCLK

27C

S28

INT

29VD

DIO

30SE

LEC

T31

FB_C

OR

E32

CO

MP_

CO

RE

33VC

OR

E_SN

S34

SW_C

OR

E35

BOO

T_C

OR

E36

VPRE37 VAUX38 VAUX_B39 VAUX_E40 VCCA_E41 VCCA_B42 VCCA43 GATE_LS44 DGND45 BOOT_PRE46 SW_PRE247 SW_PRE148

EP49

R22

510K

R1

0

C25

0.22

UF

TP19

R75

5.1K

R40

5.0K

13

2

TP8

DN

P1

J18

123

R10

05.

6K

J25

12R

275.

1K

J30

PLU

G_1

X2

1 2

C56

4.7u

F

R63

51K

TP22

J37

12

34 6

5 78

910

1112

1314

1516

1718

1920

TP15

JP1

PLU

G_1

X10

1 2 3 4 5 6 7 8 9 10

R25

2K

C27

10nF

C53

4.7u

F

J2

1 2

3 4

C14

10nF

DN

P

R65

12K

D14

RED

A C

J5

123

D21

RED

A C

C9

10nF

TP11

J141

2

C8

470P

F

R10

200

D18

LED

/GR

N

AC

J27

12

R324.32K

TP7

C15

180P

F

R42

5.6K

R53

0

C1

10uF

J38 1

23

D20

RED

A C

D5

LED

/GR

NA

C

R26

5.1K

R5

1.5K

D6

SS24

T3G

AC

R20

1.2K

R16

5.1K

J21

123

D10

LED

/GR

N

A C

D7

PMEG

3030

BEP

AC

C58

10nF

DN

P

Q4

BSS8

4LT1

1

32

TP14

TP24

Q50

PHPT

6060

3PY

4

1 523

C93

0.47

UF

C2

10uF

TP10

DN

P1

R11

15

C24

3.3u

F

C19

0.1U

F

C92

10nF

DN

P

J26

12

C66

10nF

R50

0

L122

UH

12

Q53

NX3

008N

BK

1

23

R54

30

R1324.9K

SW5

1 2 3 4

8 7 6 5

R74

5.1K

TP9

R39

1.2K

R99

10K

J1

HD

R 1

X2

1 2

R3324.9K

J7

12

34

R12

15

R11

10

TP1

BH4

MTG

1

J4

1 23

R31

1.5K

R64

24K

J351

2

D55

BZT5

2H-B

18AC

D3

LED

/GR

NA

C

C69

1000

PF



Schematic

Figure 24. Evaluation board schematic

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

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Analog Inputs

Digital IOs

HIGH_to_LOW

Level Shifter

+�*,-

��!.��

��

!/��

��

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01+�*,-

��

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0��#

+�*,-

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FAST HIGH_to_LOW

Level Shifter

VREF

H

AN_I

N_1

AN_I

N_2

AN_I

N_3

AN_I

N_4

AN_I

N_5

AN_I

N_6

AN_I

N_7

GPI

O_0

GPI

O_1

GPI

O_2

GPI

O_3

GPI

O_4

IO_S

W_0

IO_S

W_2

IO_S

W_3

IO_S

W_4

IO_S

W_5

RXD

_L_M

CU

RXD

_L_M

CU

TXD

_L_M

CU

TC_U

SB_I

D_T

P

SHIELD_K20USB

USB

_CO

NN

_DN

USB

_CO

NN

_DP

P5V0

_USB

_CO

NN

_VBU

S

USB

_DM

USB

_DP

USB

_DM

USB

_DP

SWD

_DIO

SWD

_CLK

RST

_KL2

5Z

GPI

O_0

GPI

O_1

GPI

O_2

GPI

O_3

GPI

O_4

GPI

O_5

GPI

O_6

GPI

O_7

GPI

O_8

MIS

O_M

CU

MO

SI_M

CU

SCLK

_MC

U

IO_S

W_0

IO_S

W_2

IO_S

W_3

IO_S

W_4

IO_S

W_5

RST

b_SW

FS0b

_SW

FS1b

_SW

FS0b

_SW

FS1b

_SW

RST

b_SW

GPI

O_6

GPI

O_7

GPI

O_8

MO

SI_M

CU

SCLK

_MC

UN

CSb

_MC

U

MIS

O_S

H

RXD

_L_S

H

RXD

_L_S

H

SWD

_CLK

SWD

_DIO

NC

Sb_M

CU

TXD

_MC

UR

XD_S

H

RXD

_SH

RXD

_MC

U

TXD

_MC

U

RXD

_MC

U

AN_I

N_0

PTE2

9

TXD

_L_M

CU

TXD

_L_S

W

TXD

_L_S

W

GPI

O_5

DBG

_SW

DBG

_SW

AN_I

N_0

AN_I

N_1

AN_I

N_2

AN_I

N_3

AN_I

N_4

AN_I

N_5

AN_I

N_6

AN_I

N_7

MIS

O_S

HM

ISO

_MC

U

RST

_KL2

5Z

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

DG

ND

GN

DG

ND

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

DG

ND

GN

D

GN

D

GN

DG

ND

GN

D

P3V3

_KL2

5Z

P3V3

_KL2

5Z

P3V3

_KL2

5Z

P3V3

_KL2

5Z

P3V3

_KL2

5Z

P3V3

_KL2

5Z

P3V3

_KL2

5Z

P3V3

_KL2

5Z

P3V3

_KL2

5Z

P3V3

_KL2

5Z

P3V3

_KL2

5Z

P5V_

KL25

Z

P3V3

_KL2

5Z

P3V3

_KL2

5Z

P3V3

_KL2

5Z

P3V3

_KL2

5Z

P5V_

KL25

Z

VDD

IO

MU

X_O

UT

[3]

RST

b[3

] FS0b

[3] FS

1b[3

]

Vcor

e[3

] Vaux

[3] Vc

ca[3

] CAN

_5V

[3]

Vpre

[3]

MIS

O[3

]M

OSI

[3] N

CSb

[3]

SCLK

[3]

IO_4

[3] IO

_5[3

]

IO_0

[3] IO

_2[3

] IO_3

[3]

Vkam

[3]

RXD

_L[3

]RXD

[3]

DBG

[3] TX

D_L

[3]TX

D[3

]

Vddi

o[3

,4]

Vddi

o[3

,4]

Dra

win

g Ti

tle:

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

Page

Titl

e:

ICAP

Cla

ssifi

catio

n:C

P:IU

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PUBI

:

SCH

-292

25 P

DF:

SPF

-292

25A

KIT

FS65

22LA

EEVM

C

Wed

nesd

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pril

06, 2

016

INTE

RFAC

E

44

___

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Title

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Doc

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Rev

Dat

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of

Page

Titl

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ICAP

Cla

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catio

n:C

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:

SCH

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25 P

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SPF

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25A

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FS65

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EEVM

C

Wed

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pril

06, 2

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INTE

RFAC

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44

___

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Title

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Size

Doc

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Rev

Dat

e:Sh

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of

Page

Titl

e:

ICAP

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catio

n:C

P:IU

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:

SCH

-292

25 P

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SPF

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25A

KIT

FS65

22LA

EEVM

C

Wed

nesd

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pril

06, 2

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RFAC

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___

___

X

D53

PDZ3

6B

AC

U52 SN

74LV

C1T

45

VCC

A1

GN

D2

A3

B4

DIR

5

VCC

B6

R59

10K

-+U53

B

MC

P600

4-I/S

L

5 67

C82

1.0U

F

C31

2.2U

F

R21

10K

C60

0.1U

F

C85

1.0U

F

D54

PDZ3

6B

AC

R87

10K

C64

0.1U

F

C77

0.1U

F

C75

1.0U

F

R92

0

D51

PDZ3

6B

AC

C65

0.1U

F

D52

PDZ3

6B

AC

D50

PDZ3

6B

AC

SW3

SW_D

IP-6

_SM

1 2 3 4 5 6

12 11 10 9 8 7

J20

HD

R 2

X5

12

34 6

5 78

910

C80

0.1U

F

C68

1.0U

F

SW6

SW D

IP-4

/SM

1 2 3 4

8 7 6 5

R70

9.09

k

C32

0.1U

F

C90

0.1U

F

5V D- D+ ID G

CO

NN

USB

MIN

I-BJ3

3

1 2 3 4

S2

5

S1S3 S4

J34

HD

R 2

X2

12

34

R61

10K

R41

33

R85

11K

-+U50

B

MC

P600

4-I/S

L

5 67

-+U53

C

MC

P600

4-I/S

L

10 98

TP56

TP55

R86

11K

C76

1.0U

F

R90

9.09

k

F50

MFU

0805

FF00

500P

100

12

R73

11K

R91

1.0M

DN

P

R80

9.09

k

C74

0.1U

F

TP32

C73

0.1U

F

C67

0.1U

F

C72

0.1U

F

R34

10K

C89

0.1U

FC

830.

1UF

R38

33

R62

10K

D16

PDZ3

6B

AC

D9

PDZ3

6B

AC

-+U50

C

MC

P600

4-I/S

L

10 98

R35

560

-+U53

D

MC

P600

4-I/S

L

12 1314

TP57

TP54

C88

1.0U

F

74H

C40

50D

U51

1A3

2A5

3A7

4A9

5A11

6A14

1Y2

2Y4

3Y6

4Y10

5Y12

NC

_13

136Y

15

NC

_16

16

VCC1

GN

D

8

TP52

C78

0.1U

F

C87

1.0U

F

C30

0.1U

F

MKL

25Z1

28VF

T4

U54

PTE2

0/AD

C0_

DP0

/AD

C0_

SE0/

TPM

1_C

H0/

UAR

T0_T

X7

PTE2

1/AD

C0_

DM

0/AD

C0_

SE4A

/TPM

1_C

H1/

UAR

T0_R

X8

PTE3

0/D

AC0_

OU

T/AD

C0_

SE23

/CM

P0_I

N4/

TPM

0_C

H3/

TPM

_CLK

IN1

14

PTC

4/LL

WU

_P8/

SPI0

_PC

S0/U

ART1

_TX/

TPM

0_C

H3

37

PTC

5/LL

WU

_P9/

SPI0

_SC

K/LP

TMR

0_AL

T2/C

MP0

_OU

T38

PTC

6/LL

WU

_P10

/CM

P0_I

N0/

SPI0

_MO

SI/E

XTR

G_I

N/S

PI0_

MIS

O39

PTC

7/C

MP0

_IN

1/SP

I0_M

ISO

/SPI

0_M

OSI

40

VREFH10

VREFL11

VSSA12

PTE2

9/C

MP0

_IN

5/AD

C0_

SE4B

/TPM

0_C

H2/

TPM

_CLK

IN0

13

VDD11

VDDA9

VDD222

PTA0

/SW

D_C

LK/T

SI0_

CH

1/TP

M0_

CH

517

PTA1

/TSI

0_C

H2/

UAR

T0_R

X/TP

M2_

CH

018

PTA2

/TSI

0_C

H3/

UAR

T0_T

X/TP

M2_

CH

119

PTA3

/SW

D_D

IO/T

SI0_

CH

4/I2

C1_

SCL/

TPM

0_C

H0

20

PTA4

/NM

I/TSI

0_C

H5/

I2C

1_SD

A/TP

M0_

CH

121

PTA1

8/EX

TAL0

/UAR

T1_R

X/TP

M_C

LKIN

024

PTA1

9/XT

AL0/

UAR

T1_T

X/TP

M_C

LKIN

1/LP

TMR

0_AL

T125

PTA2

0/R

ESET

26

PTB0

/LLW

U_P

5/AD

C0_

SE8/

TSI0

_CH

0/I2

C0_

SCL/

TPM

1_C

H0

27

PTB1

/AD

C0_

SE9/

TSI0

_CH

6/I2

C0_

SDA/

TPM

1_C

H1

28

PTB2

/AD

C0_

SE12

/TSI

0_C

H7/

I2C

0_SC

L/TP

M2_

CH

029

PTB3

/AD

C0_

SE13

/TSI

0_C

H8/

I2C

0_SD

A/TP

M2_

CH

130

PTB1

6/TS

I0_C

H9/

SPI1

_MO

SI/U

ART0

_RX/

TPM

_CLK

IN0/

SPI1

_MIS

O31

PTB1

7/TS

I0_C

H10

/SPI

1_M

ISO

/UAR

T0_T

X/TP

M_C

LKIN

1/SP

I1_M

OSI

32

PTC

0/AD

C0_

SE14

/TSI

0_C

H13

/EXT

RG

_IN

/CM

P0_O

UT

33

PTC

1/LL

WU

_P6/

RTC

_CLK

IN/A

DC

0_SE

15/T

SI0_

CH

14/I2

C1_

SCL/

TPM

0_C

H0

34

PTC

2/AD

C0_

SE11

/TSI

0_C

H15

/I2C

1_SD

A/TP

M0_

CH

135

PTC

3/LL

WU

_P7/

UAR

T1_R

X/TP

M0_

CH

2/C

LKO

UT

36

PTD

0/SP

I0_P

CS0

/TPM

0_C

H0

41

PTD

1/AD

C0_

SE5B

/SPI

0_SC

K/TP

M0_

CH

142

PTD

2/SP

I0_M

OSI

/UAR

T2_R

X/TP

M0_

CH

2/SP

I0_M

ISO

43

PTD

3/SP

I0_M

ISO

/UAR

T2_T

X/TP

M0_

CH

3/SP

I0_M

OSI

44

PTD

4/LL

WU

_P14

/SPI

1_PC

S0/U

ART2

_RX/

TPM

0_C

H4

45

PTD

5/AD

C0_

SE6B

/SPI

1_SC

K/U

ART2

_TX/

TPM

0_C

H5

46

PTD

6/LL

WU

_P15

/AD

C0_

SE7B

/SPI

1_M

OSI

/UAR

T0_R

X/SP

I1_M

ISO

47

PTD

7/SP

I1_M

ISO

/UAR

T0_T

X/SP

I1_M

OSI

48U

SB0_

DP

3U

SB0_

DM

4

VOUT335

VREG

IN6

VSS12

VSS223

PTE2

4/TP

M0_

CH

0/I2

C0_

SCL

15

PTE2

5/TP

M0_

CH

1/I2

C0_

SDA

16

EX_PAD49

C70

1.0U

F

D19

1SM

B591

9BT3

G

AC

C61

0.1U

F

C23

1.0U

F

J29

HD

R 2

X2

12

34

R71

9.09

k

GN

D2

GN

D1

Y50 8M

HZ

123

4

L5 330

OH

M

12

-+VC

C

VEEU53

A

MC

P600

4-I/S

L

3 21

4 11

TP50

TP20

R79

9.09

k

R68

10K

R83

13.3

K

J24

HD

R_2

X4

12

34 6

5 78

C79

22PF

R72

11K

L50

330

OH

M

12

C81

0.1U

F

-+U50

D

MC

P600

4-I/S

L

12 1314

TP51

C84

1.0U

F

R77

11K

R88

11K

R67

10K

C62

0.1U

F

TP33

D15

LED

/GR

N

A C

R78

11K

R82

9.09

k

R89

9.09

k

U1

GSO

T05C

-GS0

8

1

23

-+VC

C

VEEU50

A

MC

P600

4-I/S

L

3 21

4 11

C71

0.1U

F

C86

22PF

R84

6.49

K



Board layout

7 Board layout

7.1 Assembly layer top

Figure 25. Assembly layer top



Board layout

7.2 Assembly layer bottom

Figure 26. Assembly layer bottom



Board bill of materials

8 Board bill of materialsBill of materials for KITFS6522LAEEVM, KITFS6523CAEEVM, and KITFS4503CAEEVM are available in the download section of the Tool Summary page at the following URLs: www.nxp.com/KITFS6522LAEEVM, www.nxp.com/KITFS6523CAEEVM, or www.nxp.com/KITFS4503CAEEVM.

9 Accessory item bill of materials

Table 25. Accessory Bill of Materials (3)

Item Qty Part number Description

1 1 10U2-03103BK USB cable A plug to USB mini B

2 1 1803659 10 ways PCB screw connector

3 3 1803578 2 ways PCB screw connector

Notes 3. NXP does not assume liability, endorse, or warrant components from external manufacturers are referenced in circuit drawings or tables. While

NXP offers component recommendations in this configuration, it is the customer’s responsibility to validate their application.






References

10 References

10.1 SupportVisit www.nxp.com/support for a list of phone numbers within your region.

10.2 WarrantyVisit www.nxp.com/warranty to submit a request for tool warranty.

Table 26. References

NXP.com Support Pages Description URL

FS6500-FS4500 Data sheet TBD

AN4661Designing the VCORE Compensation Network

http://www.nxp.com/AN4661.pdf

AN4388 Quad Flat Package (QFP) http://www.nxp.com/files/AN4388.pdf

Power dissipation tool (Excel file) TBD

VCORE compensation network simulation board (CNC) upon demand

Non ISO pulses report upon demand

FMEDA FS6500/FS4500 FMEDA upon demand

FS4500-FS6500SMUGFS4500-FS6500SMUG safety manual – User Guide

TBD

KITFS6522LAEEVM,KITFS6523CAEEVM,KITFS4503CAEEVM

Tool Summary Pagewww.nxp.com/KITFS6522LAEEVMwww.nxp.com/KITFS6523CAEEVMwww.nxp.com/KITFS4503CAEEVM

FS6500 Product summary page http://www.nxp.com/FS6500

FS4500 Product summary page http://www.nxp.com/FS4500

Analog home page http://www.nxp.com/analog


http://www.nxp.com/support

http://www.freescale.com/warranty

http://www.freescale.com/support

http://www.freescale.com/support

http://www.freescale.com/warranty

http://www.nxp.com/AN4661.pdf

http://www.nxp.com/FS6500

http://www.nxp.com/analog



http://www.nxp.com/FS4500



Revision history

11 Revision history

Revision Date Description of Changes

1.0 5/2016 • Initial release

Document Number: KTFS4500-FS6500UGRev. 1.0

5/2016

Information in this document is provided solely to enable system and software implementers to use NXP products. There

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the information in this document. NXP reserves the right to make changes without further notice to any products herein.

NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose,

nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims

any and all liability, including without limitation, consequential or incidental damages. "Typical" parameters that may be

provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may

vary over time. All operating parameters, including "typicals," must be validated for each customer application by the

customer's technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells

products pursuant to standard terms and conditions of sale, which can be found at the following address:

http://www.nxp.com/terms-of-use.html.

NXP, the NXP logo, Freescale, the Freescale logo and SMARTMOS are trademarks of NXP B.V. All other product or

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