kv30f sub-family reference manual - nxp …€¦ · core modules ... 69 3.3.11 watchdog...
TRANSCRIPT
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KV30F Sub-Family Reference ManualSupports: MKV30F128VLH10, MKV30F128VLF10,
MKV30F128VFM10, MKV30F64VLH10, MKV30F64VLF10,MKV30F64VFM10, MKV30F128VLF10P
Document Number: KV30P64M100SFARMRev. 2, 02/2016
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Contents
Section number Title Page
Chapter 1About This Document
1.1 Overview.......................................................................................................................................................................39
1.1.1 Purpose...........................................................................................................................................................39
1.1.2 Audience........................................................................................................................................................ 39
1.2 Conventions.................................................................................................................................................................. 39
1.2.1 Numbering systems........................................................................................................................................39
1.2.2 Typographic notation..................................................................................................................................... 40
1.2.3 Special terms.................................................................................................................................................. 40
Chapter 2Introduction
2.1 Overview.......................................................................................................................................................................41
2.2 Module Functional Categories......................................................................................................................................41
2.2.1 ARM Cortex-M4 Core Modules.............................................................................................................. 42
2.2.2 System Modules.............................................................................................................................................43
2.2.3 Memories and Memory Interfaces................................................................................................................. 44
2.2.4 Clocks.............................................................................................................................................................44
2.2.5 Security and Integrity modules...................................................................................................................... 44
2.2.6 Analog modules............................................................................................................................................. 45
2.2.7 Timer modules............................................................................................................................................... 45
2.2.8 Communication interfaces............................................................................................................................. 46
2.2.9 Human-machine interfaces............................................................................................................................ 46
2.2.10 Kinetis Motor Suite........................................................................................................................................47
2.3 Orderable part numbers.................................................................................................................................................47
Chapter 3Chip Configuration
3.1 Introduction...................................................................................................................................................................49
3.2 Core modules................................................................................................................................................................ 49
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3.2.1 ARM Cortex-M4 Core Configuration............................................................................................................49
3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration........................................................................51
3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration...........................................................57
3.2.4 FPU Configuration.........................................................................................................................................58
3.2.5 JTAG Controller Configuration..................................................................................................................... 58
3.3 System modules............................................................................................................................................................ 59
3.3.1 SIM Configuration......................................................................................................................................... 59
3.3.2 System Mode Controller (SMC) Configuration.............................................................................................60
3.3.3 PMC Configuration........................................................................................................................................60
3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration................................................................................... 61
3.3.5 MCM Configuration...................................................................................................................................... 62
3.3.6 Crossbar-Light Switch Configuration............................................................................................................63
3.3.7 Peripheral Bridge Configuration....................................................................................................................65
3.3.8 DMA request multiplexer configuration........................................................................................................66
3.3.9 DMA Controller Configuration..................................................................................................................... 68
3.3.10 External Watchdog Monitor (EWM) Configuration......................................................................................69
3.3.11 Watchdog Configuration................................................................................................................................71
3.4 Clock modules.............................................................................................................................................................. 72
3.4.1 MCG Configuration....................................................................................................................................... 72
3.4.2 OSC Configuration........................................................................................................................................ 74
3.5 Memories and memory interfaces.................................................................................................................................74
3.5.1 Flash Memory Configuration.........................................................................................................................74
3.5.2 Flash Memory Controller Configuration....................................................................................................... 77
3.5.3 SRAM Configuration.....................................................................................................................................78
3.6 Security......................................................................................................................................................................... 80
3.6.1 CRC Configuration........................................................................................................................................ 80
3.7 Analog...........................................................................................................................................................................81
3.7.1 16-bit SAR ADC Configuration.................................................................................................................... 81
3.7.2 CMP Configuration........................................................................................................................................88
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3.7.3 12-bit DAC Configuration............................................................................................................................. 90
3.7.4 VREF Configuration...................................................................................................................................... 91
3.8 Timers........................................................................................................................................................................... 92
3.8.1 PDB Configuration........................................................................................................................................ 92
3.8.2 FlexTimer Configuration............................................................................................................................... 95
3.8.3 PIT Configuration.......................................................................................................................................... 101
3.8.4 Low-power timer configuration..................................................................................................................... 102
3.9 Communication interfaces............................................................................................................................................ 104
3.9.1 SPI configuration........................................................................................................................................... 104
3.9.2 I2C Configuration.......................................................................................................................................... 107
3.9.3 UART Configuration..................................................................................................................................... 108
3.10 Human-machine interfaces........................................................................................................................................... 110
3.10.1 GPIO configuration........................................................................................................................................110
3.11 Kinetis Motor Suite Configuration............................................................................................................................... 111
3.11.1 KMS configuration........................................................................................................................................ 111
3.11.2 KMS Library.................................................................................................................................................. 112
3.11.3 Library Protection.......................................................................................................................................... 112
3.11.4 Flash protection..............................................................................................................................................113
Chapter 4Memory Map
4.1 Introduction...................................................................................................................................................................115
4.2 System memory map.....................................................................................................................................................115
4.2.1 Aliased bit-band regions................................................................................................................................ 116
4.2.2 Flash Access Control Introduction.................................................................................................................118
4.3 Flash Memory Map.......................................................................................................................................................118
4.3.1 Alternate Non-Volatile IRC User Trim Description......................................................................................119
4.4 SRAM memory map.....................................................................................................................................................119
4.5 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................120
4.5.1 Read-after-write sequence and required serialization of memory operations................................................120
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4.5.2 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map.......................................................................................... 120
4.6 Private Peripheral Bus (PPB) memory map..................................................................................................................124
Chapter 5Clock Distribution
5.1 Introduction...................................................................................................................................................................127
5.2 Programming model......................................................................................................................................................127
5.3 High-Level device clocking diagram............................................................................................................................127
5.4 Clock definitions...........................................................................................................................................................128
5.4.1 Device clock summary...................................................................................................................................129
5.5 Internal clocking requirements..................................................................................................................................... 131
5.5.1 Clock divider values after reset......................................................................................................................132
5.5.2 VLPR mode clocking.....................................................................................................................................132
5.6 Clock Gating................................................................................................................................................................. 133
5.7 Module clocks...............................................................................................................................................................133
5.7.1 PMC 1-kHz LPO clock.................................................................................................................................. 134
5.7.2 IRC 48MHz clock.......................................................................................................................................... 134
5.7.3 WDOG clocking............................................................................................................................................ 135
5.7.4 Debug trace clock...........................................................................................................................................135
5.7.5 PORT digital filter clocking...........................................................................................................................136
5.7.6 LPTMR clocking............................................................................................................................................136
5.7.7 CLKOUT32K clocking..................................................................................................................................137
5.7.8 UART clocking.............................................................................................................................................. 137
Chapter 6Reset and Boot
6.1 Introduction...................................................................................................................................................................139
6.2 Reset..............................................................................................................................................................................139
6.2.1 Power-on reset (POR).................................................................................................................................... 140
6.2.2 System reset sources...................................................................................................................................... 140
6.2.3 MCU Resets................................................................................................................................................... 143
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6.2.4 Reset Pin ....................................................................................................................................................... 145
6.2.5 Debug resets...................................................................................................................................................145
6.3 Boot...............................................................................................................................................................................146
6.3.1 Boot sources...................................................................................................................................................146
6.3.2 Boot options................................................................................................................................................... 146
6.3.3 FOPT boot options......................................................................................................................................... 147
6.3.4 Boot sequence................................................................................................................................................ 148
Chapter 7Power Management
7.1 Introduction...................................................................................................................................................................151
7.2 Clocking modes............................................................................................................................................................ 151
7.2.1 Partial Stop.....................................................................................................................................................151
7.2.2 DMA Wakeup................................................................................................................................................ 152
7.2.3 Compute Operation........................................................................................................................................ 153
7.2.4 Peripheral Doze..............................................................................................................................................154
7.2.5 Clock Gating.................................................................................................................................................. 155
7.3 Power Modes Description.............................................................................................................................................155
7.4 Entering and exiting power modes............................................................................................................................... 157
7.5 Power mode transitions.................................................................................................................................................158
7.6 Power modes shutdown sequencing............................................................................................................................. 159
7.7 Flash Program Restrictions...........................................................................................................................................160
7.8 Module Operation in Low Power Modes......................................................................................................................160
Chapter 8Security
8.1 Introduction...................................................................................................................................................................165
8.2 Flash Security............................................................................................................................................................... 165
8.3 Security Interactions with other Modules..................................................................................................................... 166
8.3.1 Security Interactions with Debug...................................................................................................................166
Chapter 9Debug
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9.1 Introduction...................................................................................................................................................................167
9.1.1 References......................................................................................................................................................169
9.2 The Debug Port.............................................................................................................................................................170
9.2.1 JTAG-to-SWD change sequence................................................................................................................... 170
9.2.2 JTAG-to-cJTAG change sequence.................................................................................................................171
9.3 Debug Port Pin Descriptions.........................................................................................................................................171
9.4 System TAP connection................................................................................................................................................171
9.4.1 IR Codes.........................................................................................................................................................172
9.5 JTAG status and control registers................................................................................................................................. 172
9.5.1 MDM-AP Control Register............................................................................................................................173
9.5.2 MDM-AP Status Register.............................................................................................................................. 175
9.6 Debug Resets................................................................................................................................................................ 176
9.7 AHB-AP........................................................................................................................................................................177
9.8 ITM............................................................................................................................................................................... 177
9.9 Core Trace Connectivity............................................................................................................................................... 178
9.10 TPIU..............................................................................................................................................................................178
9.11 DWT............................................................................................................................................................................. 178
9.12 Debug in Low Power Modes........................................................................................................................................ 179
9.12.1 Debug Module State in Low Power Modes................................................................................................... 179
9.13 Debug & Security......................................................................................................................................................... 180
Chapter 10Signal Multiplexing and Signal Descriptions
10.1 Introduction...................................................................................................................................................................181
10.2 Signal Multiplexing Integration....................................................................................................................................181
10.2.1 Port control and interrupt module features.................................................................................................... 182
10.2.2 Clock gating................................................................................................................................................... 183
10.2.3 Signal multiplexing constraints......................................................................................................................183
10.3 Pinout............................................................................................................................................................................ 183
10.3.1 KV30F Signal Multiplexing and Pin Assignments........................................................................................183
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10.3.2 KV30F Pinouts...............................................................................................................................................186
10.4 Module Signal Description Tables................................................................................................................................189
10.4.1 Core Modules.................................................................................................................................................189
10.4.2 System Modules.............................................................................................................................................190
10.4.3 Clock Modules............................................................................................................................................... 190
10.4.4 Analog............................................................................................................................................................191
10.4.5 Timer Modules...............................................................................................................................................192
10.4.6 Communication Interfaces............................................................................................................................. 193
10.4.7 Human-Machine Interfaces (HMI)................................................................................................................ 194
Chapter 11Port Control and Interrupts (PORT)
11.1 Introduction...................................................................................................................................................................195
11.2 Overview.......................................................................................................................................................................195
11.2.1 Features.......................................................................................................................................................... 195
11.2.2 Modes of operation........................................................................................................................................ 196
11.3 External signal description............................................................................................................................................197
11.4 Detailed signal description............................................................................................................................................197
11.5 Memory map and register definition.............................................................................................................................197
11.5.1 Pin Control Register n (PORTx_PCRn).........................................................................................................204
11.5.2 Global Pin Control Low Register (PORTx_GPCLR).................................................................................... 207
11.5.3 Global Pin Control High Register (PORTx_GPCHR)...................................................................................207
11.5.4 Interrupt Status Flag Register (PORTx_ISFR).............................................................................................. 208
11.5.5 Digital Filter Enable Register (PORTx_DFER).............................................................................................208
11.5.6 Digital Filter Clock Register (PORTx_DFCR)..............................................................................................209
11.5.7 Digital Filter Width Register (PORTx_DFWR)............................................................................................ 209
11.6 Functional description...................................................................................................................................................210
11.6.1 Pin control...................................................................................................................................................... 210
11.6.2 Global pin control.......................................................................................................................................... 211
11.6.3 External interrupts..........................................................................................................................................211
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11.6.4 Digital filter....................................................................................................................................................212
Chapter 12System Integration Module (SIM)
12.1 Introduction...................................................................................................................................................................215
12.1.1 Features.......................................................................................................................................................... 215
12.2 Memory map and register definition.............................................................................................................................216
12.2.1 System Options Register 1 (SIM_SOPT1).................................................................................................... 217
12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG)......................................................................................218
12.2.3 System Options Register 2 (SIM_SOPT2).................................................................................................... 219
12.2.4 System Options Register 4 (SIM_SOPT4).................................................................................................... 221
12.2.5 System Options Register 5 (SIM_SOPT5).................................................................................................... 223
12.2.6 System Options Register 7 (SIM_SOPT7).................................................................................................... 225
12.2.7 System Options Register 8 (SIM_SOPT8).................................................................................................... 227
12.2.8 System Device Identification Register (SIM_SDID).....................................................................................228
12.2.9 System Clock Gating Control Register 4 (SIM_SCGC4)..............................................................................230
12.2.10 System Clock Gating Control Register 5 (SIM_SCGC5)..............................................................................232
12.2.11 System Clock Gating Control Register 6 (SIM_SCGC6)..............................................................................233
12.2.12 System Clock Gating Control Register 7 (SIM_SCGC7)..............................................................................236
12.2.13 System Clock Divider Register 1 (SIM_CLKDIV1).....................................................................................237
12.2.14 Flash Configuration Register 1 (SIM_FCFG1)............................................................................................. 239
12.2.15 Flash Configuration Register 2 (SIM_FCFG2)............................................................................................. 240
12.2.16 Unique Identification Register High (SIM_UIDH)....................................................................................... 241
12.2.17 Unique Identification Register Mid-High (SIM_UIDMH)............................................................................241
12.2.18 Unique Identification Register Mid Low (SIM_UIDML)............................................................................. 242
12.2.19 Unique Identification Register Low (SIM_UIDL)........................................................................................ 242
12.3 Functional description...................................................................................................................................................242
Chapter 13Kinetis Flashloader
13.1 Chip-Specific Information............................................................................................................................................ 243
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13.2 Introduction...................................................................................................................................................................243
13.3 Functional Description..................................................................................................................................................245
13.3.1 Memory Maps................................................................................................................................................ 245
13.3.2 Start-up Process..............................................................................................................................................246
13.3.3 Clock Configuration.......................................................................................................................................247
13.3.4 Flashloader Protocol...................................................................................................................................... 248
13.3.5 Flashloader Packet Types...............................................................................................................................253
13.3.6 Flashloader Command API............................................................................................................................260
13.4 Peripherals Supported................................................................................................................................................... 279
13.4.1 I2C Peripheral................................................................................................................................................ 279
13.4.2 SPI Peripheral................................................................................................................................................ 281
13.4.3 UART Peripheral........................................................................................................................................... 283
13.5 Get/SetProperty Command Properties..........................................................................................................................286
13.5.1 Property Definitions.......................................................................................................................................287
13.6 Kinetis Flashloader Status Error Codes........................................................................................................................ 288
Chapter 14Reset Control Module (RCM)
14.1 Introduction...................................................................................................................................................................291
14.2 Reset memory map and register descriptions............................................................................................................... 291
14.2.1 System Reset Status Register 0 (RCM_SRS0).............................................................................................. 292
14.2.2 System Reset Status Register 1 (RCM_SRS1).............................................................................................. 293
14.2.3 Reset Pin Filter Control register (RCM_RPFC)............................................................................................ 295
14.2.4 Reset Pin Filter Width register (RCM_RPFW)............................................................................................. 296
14.2.5 Sticky System Reset Status Register 0 (RCM_SSRS0).................................................................................297
14.2.6 Sticky System Reset Status Register 1 (RCM_SSRS1).................................................................................298
Chapter 15System Mode Controller (SMC)
15.1 Introduction...................................................................................................................................................................301
15.2 Modes of operation....................................................................................................................................................... 301
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15.3 Memory map and register descriptions.........................................................................................................................303
15.3.1 Power Mode Protection register (SMC_PMPROT).......................................................................................304
15.3.2 Power Mode Control register (SMC_PMCTRL)...........................................................................................305
15.3.3 Stop Control Register (SMC_STOPCTRL)...................................................................................................307
15.3.4 Power Mode Status register (SMC_PMSTAT)............................................................................................. 308
15.4 Functional description...................................................................................................................................................309
15.4.1 Power mode transitions..................................................................................................................................309
15.4.2 Power mode entry/exit sequencing................................................................................................................ 312
15.4.3 Run modes......................................................................................................................................................314
15.4.4 Wait modes.................................................................................................................................................... 316
15.4.5 Stop modes.....................................................................................................................................................317
15.4.6 Debug in low power modes........................................................................................................................... 320
Chapter 16Power Management Controller (PMC)
16.1 Introduction...................................................................................................................................................................323
16.2 Features.........................................................................................................................................................................323
16.3 Low-voltage detect (LVD) system................................................................................................................................323
16.3.1 LVD reset operation.......................................................................................................................................324
16.3.2 LVD interrupt operation.................................................................................................................................324
16.3.3 Low-voltage warning (LVW) interrupt operation......................................................................................... 324
16.4 I/O retention..................................................................................................................................................................325
16.5 Memory map and register descriptions.........................................................................................................................325
16.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1).......................................................... 326
16.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2).......................................................... 327
16.5.3 Regulator Status And Control register (PMC_REGSC)................................................................................ 328
Chapter 17Low-Leakage Wakeup Unit (LLWU)
17.1 Introduction...................................................................................................................................................................331
17.1.1 Features.......................................................................................................................................................... 331
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17.1.2 Modes of operation........................................................................................................................................ 332
17.1.3 Block diagram................................................................................................................................................ 333
17.2 LLWU signal descriptions............................................................................................................................................ 334
17.3 Memory map/register definition................................................................................................................................... 334
17.3.1 LLWU Pin Enable 1 register (LLWU_PE1)..................................................................................................335
17.3.2 LLWU Pin Enable 2 register (LLWU_PE2)..................................................................................................336
17.3.3 LLWU Pin Enable 3 register (LLWU_PE3)..................................................................................................337
17.3.4 LLWU Pin Enable 4 register (LLWU_PE4)..................................................................................................338
17.3.5 LLWU Module Enable register (LLWU_ME).............................................................................................. 339
17.3.6 LLWU Flag 1 register (LLWU_F1)...............................................................................................................341
17.3.7 LLWU Flag 2 register (LLWU_F2)...............................................................................................................343
17.3.8 LLWU Flag 3 register (LLWU_F3)...............................................................................................................344
17.3.9 LLWU Pin Filter 1 register (LLWU_FILT1)................................................................................................ 346
17.3.10 LLWU Pin Filter 2 register (LLWU_FILT2)................................................................................................ 347
17.4 Functional description...................................................................................................................................................348
17.4.1 LLS mode.......................................................................................................................................................349
17.4.2 VLLS modes.................................................................................................................................................. 349
17.4.3 Initialization................................................................................................................................................... 349
Chapter 18Miscellaneous Control Module (MCM)
18.1 Introduction...................................................................................................................................................................351
18.1.1 Features.......................................................................................................................................................... 351
18.2 Memory map/register descriptions............................................................................................................................... 351
18.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)..................................................................352
18.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC).............................................................. 352
18.2.3 Crossbar Switch (AXBS) Control Register (MCM_PLACR)....................................................................... 353
18.2.4 Interrupt Status and Control Register (MCM_ISCR).................................................................................... 353
18.2.5 Compute Operation Control Register (MCM_CPO)..................................................................................... 356
18.3 Functional description...................................................................................................................................................357
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18.3.1 Interrupts........................................................................................................................................................ 357
Chapter 19Crossbar Switch Lite (AXBS-Lite)
19.1 Introduction...................................................................................................................................................................359
19.1.1 Features.......................................................................................................................................................... 359
19.2 Memory Map / Register Definition...............................................................................................................................360
19.3 Functional Description..................................................................................................................................................360
19.3.1 General operation...........................................................................................................................................360
19.3.2 Arbitration......................................................................................................................................................361
19.4 Initialization/application information........................................................................................................................... 362
Chapter 20Peripheral Bridge (AIPS-Lite)
20.1 Introduction...................................................................................................................................................................363
20.1.1 Features.......................................................................................................................................................... 363
20.1.2 General operation...........................................................................................................................................363
20.2 Memory map/register definition................................................................................................................................... 364
20.3 Functional description...................................................................................................................................................364
20.3.1 Access support............................................................................................................................................... 364
Chapter 21Direct Memory Access Multiplexer (DMAMUX)
21.1 Introduction...................................................................................................................................................................365
21.1.1 Overview........................................................................................................................................................365
21.1.2 Features.......................................................................................................................................................... 366
21.1.3 Modes of operation........................................................................................................................................ 366
21.2 External signal description............................................................................................................................................367
21.3 Memory map/register definition................................................................................................................................... 367
21.3.1 Channel Configuration register (DMAMUX_CHCFGn).............................................................................. 367
21.4 Functional description...................................................................................................................................................368
21.4.1 DMA channels with periodic triggering capability........................................................................................369
21.4.2 DMA channels with no triggering capability.................................................................................................371
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21.4.3 Always-enabled DMA sources...................................................................................................................... 371
21.5 Initialization/application information........................................................................................................................... 373
21.5.1 Reset...............................................................................................................................................................373
21.5.2 Enabling and configuring sources..................................................................................................................373
Chapter 22Enhanced Direct Memory Access (eDMA)
22.1 Introduction...................................................................................................................................................................377
22.1.1 eDMA system block diagram........................................................................................................................ 377
22.1.2 Block parts..................................................................................................................................................... 378
22.1.3 Features.......................................................................................................................................................... 379
22.2 Modes of operation....................................................................................................................................................... 380
22.3 Memory map/register definition................................................................................................................................... 381
22.3.1 TCD memory................................................................................................................................................. 381
22.3.2 TCD initialization.......................................................................................................................................... 381
22.3.3 TCD structure.................................................................................................................................................381
22.3.4 Reserved memory and bit fields.....................................................................................................................382
22.3.1 Control Register (DMA_CR).........................................................................................................................386
22.3.2 Error Status Register (DMA_ES).................................................................................................................. 389
22.3.3 Enable Request Register (DMA_ERQ)......................................................................................................... 391
22.3.4 Enable Error Interrupt Register (DMA_EEI).................................................................................................392
22.3.5 Clear Enable Error Interrupt Register (DMA_CEEI).................................................................................... 393
22.3.6 Set Enable Error Interrupt Register (DMA_SEEI)........................................................................................ 394
22.3.7 Clear Enable Request Register (DMA_CERQ)............................................................................................. 395
22.3.8 Set Enable Request Register (DMA_SERQ)................................................................................................. 396
22.3.9 Clear DONE Status Bit Register (DMA_CDNE).......................................................................................... 397
22.3.10 Set START Bit Register (DMA_SSRT)........................................................................................................ 398
22.3.11 Clear Error Register (DMA_CERR)..............................................................................................................399
22.3.12 Clear Interrupt Request Register (DMA_CINT)........................................................................................... 400
22.3.13 Interrupt Request Register (DMA_INT)........................................................................................................401
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22.3.14 Error Register (DMA_ERR).......................................................................................................................... 402
22.3.15 Hardware Request Status Register (DMA_HRS).......................................................................................... 403
22.3.16 Enable Asynchronous Request in Stop Register (DMA_EARS)...................................................................405
22.3.17 Channel n Priority Register (DMA_DCHPRIn)............................................................................................ 406
22.3.18 TCD Source Address (DMA_TCDn_SADDR).............................................................................................407
22.3.19 TCD Signed Source Address Offset (DMA_TCDn_SOFF)..........................................................................407
22.3.20 TCD Transfer Attributes (DMA_TCDn_ATTR)...........................................................................................408
22.3.21 TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCDn_NBYTES_MLNO)................... 409
22.3.22 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
(DMA_TCDn_NBYTES_MLOFFNO)......................................................................................................... 409
22.3.23 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
(DMA_TCDn_NBYTES_MLOFFYES)....................................................................................................... 411
22.3.24 TCD Last Source Address Adjustment (DMA_TCDn_SLAST)...................................................................412
22.3.25 TCD Destination Address (DMA_TCDn_DADDR).....................................................................................412
22.3.26 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)..................................................................413
22.3.27 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_CITER_ELINKYES).............................................................................................................413
22.3.28 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_CITER_ELINKNO).............................................................................................................. 415
22.3.29 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA)............ 416
22.3.30 TCD Control and Status (DMA_TCDn_CSR).............................................................................................. 416
22.3.31 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_BITER_ELINKYES).............................................................................................................419
22.3.32 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_BITER_ELINKNO).............................................................................................................. 420
22.4 Functional description...................................................................................................................................................421
22.4.1 eDMA basic data flow................................................................................................................................... 421
22.4.2 Fault reporting and handling.......................................................................................................................... 424
22.4.3 Channel preemption....................................................................................................................................... 426
22.4.4 Performance................................................................................................................................................... 426
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22.5 Initialization/application information........................................................................................................................... 431
22.5.1 eDMA initialization....................................................................................................................................... 431
22.5.2 Programming errors....................................................................................................................................... 433
22.5.3 Arbitration mode considerations....................................................................................................................433
22.5.4 Performing DMA transfers............................................................................................................................ 434
22.5.5 Monitoring transfer descriptor status............................................................................................................. 438
22.5.6 Channel Linking.............................................................................................................................................440
22.5.7 Dynamic programming.................................................................................................................................. 441
Chapter 23External Watchdog Monitor (EWM)
23.1 Introduction...................................................................................................................................................................445
23.1.1 Features.......................................................................................................................................................... 445
23.1.2 Modes of Operation....................................................................................................................................... 446
23.1.3 Block Diagram............................................................................................................................................... 447
23.2 EWM Signal Descriptions............................................................................................................................................ 448
23.3 Memory Map/Register Definition.................................................................................................................................448
23.3.1 Control Register (EWM_CTRL)................................................................................................................... 448
23.3.2 Service Register (EWM_SERV)....................................................................................................................449
23.3.3 Compare Low Register (EWM_CMPL)........................................................................................................ 449
23.3.4 Compare High Register (EWM_CMPH).......................................................................................................450
23.3.5 Clock Prescaler Register (EWM_CLKPRESCALER).................................................................................. 451
23.4 Functional Description..................................................................................................................................................451
23.4.1 The EWM_out Signal.................................................................................................................................... 451
23.4.2 The EWM_in Signal...................................................................................................................................... 452
23.4.3 EWM Counter................................................................................................................................................ 453
23.4.4 EWM Compare Registers.............................................................................................................................. 453
23.4.5 EWM Refresh Mechanism.............................................................................................................................453
23.4.6 EWM Interrupt...............................................................................................................................................454
23.4.7 Counter clock prescaler..................................................................................................................................454
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Chapter 24Watchdog Timer (WDOG)
24.1 Introduction...................................................................................................................................................................455
24.2 Features.........................................................................................................................................................................455
24.3 Functional overview......................................................................................................................................................456
24.3.1 Unlocking and updating the watchdog...........................................................................................................458
24.3.2 Watchdog configuration time (WCT)............................................................................................................ 459
24.3.3 Refreshing the watchdog................................................................................................................................460
24.3.4 Windowed mode of operation........................................................................................................................460
24.3.5 Watchdog disabled mode of operation...........................................................................................................460
24.3.6 Debug modes of operation............................................................................................................................. 460
24.4 Testing the watchdog.................................................................................................................................................... 461
24.4.1 Quick test....................................................................................................................................................... 462
24.4.2 Byte test..........................................................................................................................................................462
24.5 Backup reset generator..................................................................................................................................................463
24.6 Generated resets and interrupts.....................................................................................................................................464
24.7 Memory map and register definition.............................................................................................................................464
24.7.1 Watchdog Status and Control Register High (WDOG_STCTRLH)............................................................. 465
24.7.2 Watchdog Status and Control Register Low (WDOG_STCTRLL).............................................................. 467
24.7.3 Watchdog Time-out Value Register High (WDOG_TOVALH)...................................................................467
24.7.4 Watchdog Time-out Value Register Low (WDOG_TOVALL).................................................................... 468
24.7.5 Watchdog Window Register High (WDOG_WINH).................................................................................... 468
24.7.6 Watchdog Window Register Low (WDOG_WINL)..................................................................................... 469
24.7.7 Watchdog Refresh register (WDOG_REFRESH)......................................................................................... 469
24.7.8 Watchdog Unlock register (WDOG_UNLOCK)...........................................................................................469
24.7.9 Watchdog Timer Output Register High (WDOG_TMROUTH)................................................................... 470
24.7.10 Watchdog Timer Output Register Low (WDOG_TMROUTL).................................................................... 470
24.7.11 Watchdog Reset Count register (WDOG_RSTCNT).................................................................................... 471
24.7.12 Watchdog Prescaler register (WDOG_PRESC)............................................................................................ 471
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24.8 Watchdog operation with 8-bit access.......................................................................................................................... 471
24.8.1 General guideline........................................................................................................................................... 471
24.8.2 Refresh and unlock operations with 8-bit access........................................................................................... 472
24.9 Restrictions on watchdog operation..............................................................................................................................473
Chapter 25Multipurpose Clock Generator (MCG)
25.1 Introduction...................................................................................................................................................................475
25.1.1 Features.......................................................................................................................................................... 475
25.1.2 Modes of Operation....................................................................................................................................... 477
25.2 External Signal Description.......................................................................................................................................... 478
25.3 Memory Map/Register Definition.................................................................................................................................478
25.3.1 MCG Control 1 Register (MCG_C1).............................................................................................................479
25.3.2 MCG Control 2 Register (MCG_C2).............................................................................................................480
25.3.3 MCG Control 3 Register (MCG_C3).............................................................................................................481
25.3.4 MCG Control 4 Register (MCG_C4).............................................................................................................482
25.3.5 MCG Control 5 Register (MCG_C5).............................................................................................................483
25.3.5 MCG Control 6 Register (MCG_C6).............................................................................................................483
25.3.6 MCG Status Register (MCG_S).................................................................................................................... 484
25.3.7 MCG Status and Control Register (MCG_SC)..............................................................................................485
25.3.8 MCG Auto Trim Compare Value High Register (MCG_ATCVH).............................................................. 486
25.3.9 MCG Auto Trim Compare Value Low Register (MCG_ATCVL)................................................................487
25.3.10 MCG Control 7 Register (MCG_C7).............................................................................................................487
25.3.11 MCG Control 8 Register (MCG_C8).............................................................................................................488
25.3.12 MCG Control 12 Register (MCG_C12).........................................................................................................489
25.3.12 MCG Status 2 Register (MCG_S2)............................................................................................................... 489
25.3.12 MCG Test 3 Register (MCG_T3).................................................................................................................. 489
25.4 Functional description...................................................................................................................................................490
25.4.1 MCG mode state diagram.............................................................................................................................. 490
25.4.2 Low-power bit usage......................................................................................................................................493
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25.4.3 MCG Internal Reference Clocks....................................................................................................................493
25.4.4 External Reference Clock.............................................................................................................................. 493
25.4.5 MCG Fixed Frequency Clock ....................................................................................................................... 494
25.4.6 MCG Auto TRIM (ATM).............................................................................................................................. 494
25.5 Initialization / Application information........................................................................................................................ 496
25.5.1 MCG module initialization sequence.............................................................................................................496
25.5.2 Using a 32.768 kHz reference........................................................................................................................498
25.5.3 MCG mode switching.................................................................................................................................... 499
Chapter 26Oscillator (OSC)
26.1 Introduction...................................................................................................................................................................507
26.2 Features and Modes...................................................................................................................................................... 507
26.3 Block Diagram..............................................................................................................................................................508
26.4 OSC Signal Descriptions.............................................................................................................................................. 508
26.5 External Crystal / Resonator Connections.................................................................................................................... 509
26.6 External Clock Connections......................................................................................................................................... 510
26.7 Memory Map/Register Definitions...............................................................................................................................511
26.7.1 OSC Memory Map/Register Definition.........................................................................................................511
26.8 Functional Description..................................................................................................................................................513
26.8.1 OSC module states......................................................................................................................................... 513
26.8.2 OSC module modes....................................................................................................................................... 515
26.8.3 Counter...........................................................................................................................................................517
26.8.4 Reference clock pin requirements..................................................................................................................517
26.9 Reset..............................................................................................................................................................................517
26.10 Low power modes operation.........................................................................................................................................518
26.11 Interrupts.......................................................................................................................................................................518
Chapter 27Flash Memory Controller (FMC)
27.1 Introduction...................................................................................................................................................................519
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27.1.1 Overview........................................................................................................................................................519
27.1.2 Features.......................................................................................................................................................... 519
27.2 Modes of operation....................................................................................................................................................... 520
27.3 External signal description............................................................................................................................................520
27.4 Memory map and register descriptions.........................................................................................................................520
27.4.1 Flash Access Protection Register (FMC_PFAPR).........................................................................................524
27.4.2 Flash Bank 0 Control Register (FMC_PFB0CR).......................................................................................... 526
27.4.3 Reserved (FMC_Reserved)............................................................................................................................528
27.4.4 Cache Tag Storage (FMC_TAGVDW0Sn)................................................................................................... 529
27.4.5 Cache Tag Storage (FMC_TAGVDW1Sn)................................................................................................... 530
27.4.6 Cache Tag Storage (FMC_TAGVDW2Sn)................................................................................................... 531
27.4.7 Cache Tag Storage (FMC_TAGVDW3Sn)................................................................................................... 532
27.4.8 Cache Data Storage (upper word) (FMC_DATAW0SnU)............................................................................532
27.4.9 Cache Data Storage (lower word) (FMC_DATAW0SnL)............................................................................ 533
27.4.10 Cache Data Storage (upper word) (FMC_DATAW1SnU)............................................................................533
27.4.11 Cache Data Storage (lower word) (FMC_DATAW1SnL)............................................................................ 534
27.4.12 Cache Data Storage (upper word) (FMC_DATAW2SnU)............................................................................534
27.4.13 Cache Data Storage (lower word) (FMC_DATAW2SnL)............................................................................ 535
27.4.14 Cache Data Storage (upper word) (FMC_DATAW3SnU)............................................................................535
27.4.15 Cache Data Storage (lower word) (FMC_DATAW3SnL)............................................................................ 536
27.5 Functional description...................................................................................................................................................536
27.5.1 Default configuration..................................................................................................................................... 536
27.5.2 Configuration options.................................................................................................................................... 537
27.5.3 Speculative reads............................................................................................................................................537
27.5.4 Flash Access Control (FAC) Function...........................................................................................................538
27.6 Initialization and application information.....................................................................................................................547
Chapter 28Flash Memory Module (FTFA)
28.1 Introduction...................................................................................................................................................................549
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28.1.1 Features.......................................................................................................................................................... 550
28.1.2 Block Diagram............................................................................................................................................... 550
28.1.3 Glossary......................................................................................................................................................... 551
28.2 External Signal Description.......................................................................................................................................... 552
28.3 Memory Map and Registers..........................................................................................................................................552
28.3.1 Flash Configuration Field Description...........................................................................................................553
28.3.2 Program Flash IFR Map.................................................................................................................................553
28.3.3 Register Descriptions..................................................................................................................................... 554
28.4 Functional Description..................................................................................................................................................568
28.4.1 Flash Protection..............................................................................................................................................568
28.4.2 Flash Access Protection................................................................................................................................. 568
28.4.3 Interrupts........................................................................................................................................................ 570
28.4.4 Flash Operation in Low-Power Modes.......................................................................................................... 571
28.4.5 Functional Modes of Operation..................................................................................................................... 571
28.4.6 Flash Reads and Ignored Writes.................................................................................................................... 571
28.4.7 Read While Write (RWW).............................................................................................................................572
28.4.8 Flash Program and Erase................................................................................................................................572
28.4.9 Flash Command Operations...........................................................................................................................572
28.4.10 Margin Read Commands........................................................................