NASA-CR-16832619840012669

_ 30-GHz MONOLITHIC RECEIVEMODULE

First Annual Report for Period- November 3, 1982-October 31,1983

- Contract No. NAS3-23356

March 1984

L[_ItP_ItT.OOP7, i-,• '01984

LANGLEYRESEARCHCENTERLIBRARY,NASA

itr_[.i,'.}TO[j,_ylRGI_JI_

- ForNational Aeronautical and Space Administration

- Lewis Research CenterCommunication and PropulsionSection

Honeywell

Physical Sciences Center

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30GHz MonolithicReceiveModule

FirstAnnualReportforPeriod

-- November3, 1982-October31,1983ContractNo.NAS3-23356

PreparedBY

HoneywellPhysic_SciencesCenter

10701LyndaleAvenueSouth,81oomington,MN 55420V. Sokolov,J. Geddes,P. Bauhahn

_- Phone(612)887-4452

_ For

NASA-LewisResearchCenter

C_municationandPropulsionSection

21000BrookparkRoadCleveland,OH 44135

A1 Downey,TechnicalManager

MailStop54-5

V. Sokolov T.C. Lee

ProgramManager DepartmentManager

47119

1. Report No. 2. Government AccessionNo. 3. Recipient's Catalog No.

r_ASACR-1683264. Title and Subtitle - 5. Report Date

December1983

30 GHz MonolithicReceiveeModule FirstAnnual Report 6.PerformingOrganizationCodefor Period November3, 1982 - October 31, 1983

7. Author(s) 8. PerformingOrganizationReport No.

V. Sokolov, J. Geddes, P. Bauhahn10. Work Unit No.

9. PerformingOrganizationName and Address

11. Contract or Grant No.

HoneywellCorporateTechnologyCenter10701 LyndaleAvenue South,Bloomington,Minnesota55420 NAS3-23356

13. Typeof ReportandPeriodCovered

12. SponsoringAgency NameandAddress Annual, 11-3-82to 10-31-83

NationalAeronauticsand Space Administration 14.SponsoringAgencyCodeWashington,D.C. 25046

Supplementary Notes

ProjectManager,Alan N. Downey,Space CommunicationsDivision,NASALewis ResearchCenter,Cleveland,Ohio 44135

16. Abstract

This report describes the first year's progress on a four year program to develop a 30 GHzGaAsmonolithic receive module for spaceborne communication antenna feed array applications. Keyrequirements included on overall receive module noise figure of 5 dB, a 30 dB RF to IF gain withsix levels of intermediate gain control, a five-bit phase shifter, and a maximumpower consumptionof 250 mW.

RF designs for each of the four sub-modules(low noise amplifier,gain control,phase shifter,and RF to IF sub-module)are presented. Exceptfor the phase shifter,high frequency,low noiseFETs with sub-halfmicron gate lengthsare employedin the sub-modules. For the gain controlatwo stage dual gate FET amplifieris used. The phase shifteris of the passiveswitchedline typeand consistsof 5-bits. It uses relativelylarge gate width FETs (with zero drain to sourcebias)as the switchingelements. A 20 GHz localoscillatorbufferamplifier,a FET compatiblebalancedmixer, and a 5-8 GHz IF amplifierconstitutethe RF/IF sub-module.

A novel approachto the phase shifterfabricationusing ion implantationand a self-alignedgate techniqueis described. This method of phase shifterfabricationholds promise in reducingRF lossesat high frequencies. PreliminaryRF resultsobtainedon such phase shiftersarealso presented.

17. Key Words (Suggestedby Author(s)) 18. Distribution Statement

Ion Implantation 30/20 Communication_MM-WaveMonolithicCircuits SatelliteGaAs MonlithicCircuits Ka-BandReceiver Unclassified- UnlimitedLow Noise FETs MonolithicMixerPhase ShifterSelf-AlignedGate

19. St_ar_y _a_lf.(ofthisreport) j20. SecurityClassif.(ofthis _ge) 21. No. of Pages 22. Price*

Unclassified I Unclassified

* ForsalebytheNationalTechnicallnformationService,Springfield,Virginia22161

NASA-C-168 (Rev. 10-75)

NASA Annual Report

.-- Table of Contents

I. SUMMARY S-i

II. PROGRAM PROGRESS BY TASKS 1

1.0 ReceiveModule Design--TaskI 1

I.I CircuitDesignand TestPlan 11.1.1 Overall Receiver 2

1.1.2 Phase Shifter Design 5-- 1.1.3 Gain Control 10

1.1.4 RF/IF Submodule 121.1.5 30 GHz Low Noise Amplifier Submodule 15

1.2 Device Design 161.2.1 SAG FET for Phase Shifter 16

1.2.2 100 Micron Low Noise FET 18

2.0 Phase Shifter Fabrication and Evaluation -- Task II 31

2.1 Results for 180 ° SAG Phase Shifter Design Using Shunt FETs 32

2.2 Results From Second Mask Set Using SAG Series Switches 333.0 Gain Control Fabrication -- Task III 35

3.1 100 Micron FET 37

_- 3.2 Dual Gate Amplifier 37

4.0 RF/IF and LNA Submodule Fabrication and Evaluation -- Tasks IV and V 38

5.0 Submodule Integration and Receive Module Development -- Tasks VI and VII 38

'" 6.0 Product Assurance and Reporting -- Tasks IX and X 38

III. REFERENCES 70

oooIII

NASA Annual Report

List of Figures

Figure Page

S-1 Submodule Functions of Receive Module S-8

S-2 Block Diagram of Overall Monolithic Receiver S-8

S-3 Layout of 180° Bit Using Four Series FET Switches S-9

S-4 Photomicrographs of SAG Phase Shifter Circuits on a Processed Wafer S-10

S-5 Calculated and Measured Differential Phase Shift for 180° Phase Shifter S-11

S-6 CALMALayout for 100 Micron Gate Width Low Noise FET S-11

S-7 Low Noise FET Design S-12

S-8 Design for Monolithic Five-StageAmplifier S-12 -

S-9 CALMALayout for First Two Stages of Gain Control Amplifier S-13

S-10 Design for Monolithic 2-Stage Dual-Gate Amplifier S-13

1 Block Diagram of Overall Monolithic Receiver 39

2 Interconnected Receive Module and RF Test Fixture 39

3 Simplified Equivalent Circuits for ON and OFF FETs 40

4 Insertion Loss and Isolation versus Gate Width 40 -.

5 Chip Layout for 180 ° Bit 41

6 Layout of 180° Bit Using Four Series FET Switches 41

7 Computer Calculated Results for 180 ° Phase Bit Using Series Switches 42

8 Calculated Differential Insertion Phase for 3-Bit Phase Shifter(180°, 90°, 45° Bits) Using Series FET Switches 43

9 Calculated Insertion Loss "Envelope" for Eight States of 3-Bit _.Phase Shifter 44

10 Gain Control Design 44

11 Design for Monolithic 2-Stage Dual-Gate Amplifier 45 -

12 RF/IF Submodule with Rat Race Hybrid 45

13 Diode Structure for High MixerPerformanceand Fabrication Simplicity 46

14 Noise Figure and GainCirclesfor First Stage of 22 GHz Amplifier 47

iv

NASA AnnualReport

List of Figures (Continued)

Figure Page

15 Design for Monolithic 22 GHz Amplifier 48

16 Design for Monolithic Five-Stage Amplifier 48

17 Channel Sheet Resistance versus Gate-to-Channel Voltagefor Different Implant Energies 49

18 Source-Drain Resistance versusChannel Sheet Resistance 49

19 100 x 0.25 MicronLow Noise FET Design 50

20 Gain and Noise Circlesfor Low Noise FET Input Plane- No Cdg or Ls for Noise Circles 51

21 Gain and Noise Figure Circles for Low Noise FET Input PlaneIncluding Cdg and Ls 52

22 Gain Circles for Low Noise FET Output Plane 53

23 Effect of Gate Resistance on 29 GHz Gain and Noise Figure 54

24 Effect of Source Resistance on 29 GHz Gain and Noise Figure 54

25 Insertion Phase for 180 ° Phase Shifter (TR061A)As Measured on the Network Analyzer 55

26 Test Fixture and Measured Insertion Loss for the Two Statesof the 180 ° Phase Shifter 56

27 Calculated and Measured Differential Phase Shift for 180 ° PhaseShifter (TR061A) 57

28 Measured RF Results for SAG 180 ° 1-Bit Phase Shifter 58

29 Comparison of Measured and Calculated Insertion Loss for SAG Phase Shifter 59

30 Photomicrographs of SAG Phase Shifter Circuits on a Processed Wafer 60

31 Calculated and Measured Differential Phase Shift for 45° Phase Shifter 61

32 Calculated and Measured Differential Phase Shift for 90° Phase Shifter 61

33 Calculated and Measured Differential Phase Shift for 180° Phase Shifter 62

34 180° Phase Shifter 63

35 45° Bit Insertion Loss 63

36 45° Bit Return Loss 63

NASA AnnualReport

List of Figures (Concluded)

Figure Page

37 CALMA Layout for 100 Micron Gate WidthLow Noise FET 64 -

38 CALMA Layout for First Two Stages of Gain Control Amplifier 64 -

39 Profile of Ion Implant 65

• List of Tables

Table Page

S-1 NASA's Key Performance Goals S-7

1 NASA's Key Performance Goals 66

2 Proposed Initial Low-Noise FET Design 66

3 Calculated Parameters for FET Design 67 --

4a S Parameters with No Cdg or Ls 68

4b S Parameters with No Cdg, But with Ls 68

5 S Parameters for Complete Model, Including Ls and Cdg 69

vi

I.SUMMARY

The objectiveof the four year programis to developa 30 GHz monolithic

-- receivemodulefor communicationantennafeed arrayapplications,and to

deliversubmodulesand 30 GHz monolithicreceivemodulesfor experimental

evaluation.Key requirementsincludean overallreceivemodule noisefigure

__ of 5 dB, a 30 dB RF to IF gainwith sixlevelsof intermediategaincontrol,a

5 bitphaseshifter,and a maximumpowerconsumptionof 250roW. In addition,

_ themonolithicreceivemoduledesignaddressesa costgoalof lessthan $i,000

(1980dollars)per receivemodule in unit buys of 5,000 or more, and a

mechanicalconfigurationthat is applicableto a space-bornephasedarray

. system. Theserequirementsare summarizedas performancegoalsin TableS-I.

o- The designof the monolithicmodule (TaskI) includesa partioningof the

receiverintofoursubmodulefunctions:the low noise amplifier(LNA),the

5-bit phase shifter (PS), gain control (GC) and the RF/IF frequency

down-conversionfunctionas shownin FigureS-I. The PS, GC, RF/IF and LNA

functionsembodiedin the monolithicreceivemoduleare alsodevelopedas

_ individualsubmodules,each fabricatedon a separate chip (Tasks II-V

respectively),anddesignedso as to permittheirinterconnectionto formthe

interconnectedreceivemodule(TaskVI).

p,

Duringthe firstyear of the programwork has concentratedon deviceand

circuitdesign (TaskI) and the fabricationand evaluationof the phase

shifter(TaskII)as wellas the initialdevelopmentof thegaincontrol(Task

_ III)submodules.Consequently,SectionII of thisreportdiscusses,for the

61

most part, the details of the progressmade on the first three tasks.

Nevertheless,sincemanyof the taskshaveoverlap,especiallyin the design

area, the work accomplishedin the first year is also applicableto the

developmentof theothertwo submodules.Forexample,in the caseof thegain

controlamplifier,thefirstmask set includesi00microngatewidthlownoise

FETs which are also requiredfor both the RF/IF and the LNA submodules.

Highlightsof specificaccomplishmentsduringthe firstyearare outlinedin

the following..

OverallMonolithicReceiveModuleDesian- FigureS-2 showsthe functional

configurationfor the monolithicreceivemoduleandalso indicatesnominal

gains, noise figures,dc power consumption,and overallnoise and gain

performancefor each su_noduleelementand the completereceivemodule. The

lownoiseamplifierprovidessufficientlyhigh gain (32 dB) and low noise

operationto be themajordeterminingfactorin establishingthe required5 dB

noisefigurefor theoverallreceiver.To achievethistypeof performanceit

is expectedthatsub-halfmicrongatelengthFETswith i00microngatewidths

willbe required.

The phase shifteris a 5-bit passivedeviceand utilizesself-alignedgate

(SAG)switchingFETsto achievelowinsertionloss. Theswitchesare used to

switchbetweentransmissionlinesof differentelectricallengthsto achieve

true time delayphaseshiftingforthelargerphaseshifts(180o,90° and 45°

bits),and to switchin reactiveloadingon the lines to accomplishthe

smallerphaseshifts(22° and iio bits). A SAGFETapproachutilizingseries

switcheshas been chosenas the base line approachto the phase shifter

_2

development.

Gain control is accomplishedby a dualgateamplifierin conjunctionwitha

passiveswitchedattenuator.The formerutilizes100 micron low noise dual

gate FETs,while the switchedattenuatorusesthe switchingFET technology

developedin theswitchedlinephaseshifter.

• Finally,the RF/IFsubmoduleincorporatesSchottkydiodesin a balancedmixer

configurationto accomplishthefrequencytranslationto IF (5.5- 8 GHz).

Again,a low noiseamplifieris usedto providea suitableLO signalat 22 GHz

to drivethe balancedmixer. A uniquefeatureof the design is that the

Schottky diodes are FET compatible in that fabrication of the diodes as well

as the FETs in the LO and IF amplifiers can be done on the same chip.

To address the cost goal for the monolithic receive module the basic

fabrication approach is ion implantation into semi-insulating GaAs.

Design and Init_l Fabrication of the Multi-Sit Phase Shifter - Figure S-3

_ showsa representativedesignof a 180obit usingseries,400microngatewidth

FET switches.The seriesswitchdesignreducestherequiredGaAsareaoveran

equivalentshuntdesign (testedearlyin theprogram)by nearlya factorof

two. It also introducesless parasiticreactancedue to a more compact

layout.FigureS-4 showstheactual4-bitphaseshifterfabricatedby theSAG

techniqueon the 0.15mm thickGaAswafer. Thefirstthreebits (180o, 90°,

45o) are switchedlinephaseshiftersand the lastbit (22o) isa loadedline

- phaseshifter.

FigureS-5 showsthemeasureddifferentialinsertionphaseforthe two states

of the 180Obit across a 5 GHz band (27.5-32.5GHz). Exceptfor a constant

offsetof about7o, (whichcanbe easilycompensatedfor in the finaldesign)

the measured curve follows exceptionally well the ideal time delay

characteristiccorrespondingto 6.3O/GHz.The insertionlossmeasuredon this

firstrunof SAGphaseshiftersusingseriesFETsis about3.5-4dB (excluding

fixtureloss). Thisis about1 dBworsethanthebestSAG resultsobtainedon

earlierversionsof the 180obit usingshuntFET switches.

Similarresultswere obtainedon the 90o and 45° bits. It is expected,

however,thatwithan optimizedSAG process,an insertionlossof about 1.5 -

2 dB per bitwillbe achieved.

Designof a 100 MicronGate-Width,Sub-Half-MicronGate Length FET - To

achieve the requirednoiseperformanceof the 30 GHzLNA,a FETwitha noise

figureof notgreaterthan4 dB andwithan associatedgain of at least 6 dB

must be developed. Based on extensive device design and circuit

considerations,a 100microngate-width,and sub-half-microngate lengthFET

has been designed.FigureS-6 showsthe computergeneratedlayoutof the100

micronFET. The gateconsistsof two 50micronfingers,each having a gate

length of about 0.25 microns. Thisconfigurationwas determinedto be best

suitedforachievinglownoiseandhighgainoperationat 30 GHz and yet be

consistentwith impedancematchingschemeswhicharerealizablein monolithic

form.

8-4

From an analysisof the specificfabricationrelateddesignparameters,an

equivalentcircuitshownin FigureS-7was derivedfor the i00micronFET. As

shown in the figure,thepredictedperformanceof theFET,as calculatedfrom

theequivalentcircuit,includesa maximomavailablegainof 8 dB and a noise

figureminimumof 2.5 dB at 32 GHz.

_- With the equivalentcircuitestablished,a preliminarydesignof a fivestage

LNAwas completedusingthe100micronFETsina single-endedcascadeas shown

in FigureS-8. The computeroptimizedamplifierdesignpredictsa gainof

about32.5d8 from27-31GHz.

_ Designand InitialFabricationof the Gain ControlSubmodule- The gain

control (GC) is accomplishedby incorporatinga two-stagedual gate FET

°.4 amplifierand controllingthe secondgate voltageto vary the RF gain. A

passiveswitchedline attenuatorfollowsthe amplifierto addan additional

attenuationbit. To date,workhas beeninitiatedon the developmentof the

dualgateFETamplifier.

.i FigureS-9 showsthe initiallayoutof thetwo-stagegaincontrolamplifier,

as generatedby theCALMAcomputerizedlayoutsystem. The dualgateFETshave

i00micronwideby 0.3micronlonggatestripes,andare basedon the design

and fabricationof thesinglegatei00micronFETsusedin thefront-endLNA.

On-chipsiliconnitridecapacitorsare usedto RF groundthe secondgateof

eachdualgateFET,yet permitapplicationof a DC controlvoltage for the

gain control function. All DC bias distributionand filteringis also

- includedon thechiplayout.

Finally,FigureS-10showsthe computedresponseof the two-stagegaincontrol -

amplifierin itsmaximumgainstate. The insetalsoshowsthedetailsof the

circuitschematicwhosecorrespondinglayoutis shownin the previousFigure,

S-9. Overthebandof interestthecomputedgainis 20.3+ .2dB.

Clearly, the designs developed during the first year are either starting

points (as in the gain controlsubmodule)or interimdesigns (as in the case

of the phase shiftersubmodule)which will be updatedas the experimentaldata

base is obtained. Nevertheless,the resultsof the theoretical and computer

calculations discussed above serve as guidelines for further device and

circuitdevelopment which will lead to the final designs of the receiver

submodulesand the monolithicreceivemodule.

The followingSectionII presentsthedetailsof theprogressmade during the

firstyearof the programby tasknumbers.

Table S-1. NASA's Key Performance Goals

-- Design Parameter PerformanceGoal

RF Band 27.5- 30 GHzIF Center Frequency Between 4-8 GHzNoise Figure at Room Temperature <_5 dBRF/IF Gain _-30 dB at highest level of gain controlGain Control . At least six levels; 30, 27, 24, 20, 17 dB

and Off.Phase Control 5 bits;each bit +_3° at bandcenterModule PowerConsumption 250 mWin all states except OFF. In OFF

state, 25 mW.Phase and Gain Control Operate on digital input.Mechanical Design Fully monolithic construction; compatible

with 30 GHz spaceborne phased arrayapplications.

"_- Unit Cost Less than $1000 (1980 dollars) in unit buysof 5000 or more

DIGITALCONTROLLINES(TrL)

¢ \/ \

/ \

/ \ ---

/ \\

z \

/ %

I_.,. ! I- - "_-- I I...... I -I i i I II '_,, ,,. I I I I I |RF ..J LNA" , PS i = GC ' _ IF-I .'" i I = I i RF IF I

IN i .-" , I I I I OUTIIIIII

L_ •REFPHASEINPUTAT LO FREQUENCY

Figure S-1. Submodule Functions of Receive Module

TIL LOGIC SIGNALSIFOR DIGITAL CONTROLI

11 iDtGITAL CONTROL

,.f'--AI 22 GHe SIGNAL

r ,r - - -',II LOwNOISEAMPLIFIliR II II P. SeSHlteR I I GAINCONTROLI "1v_ /LO AMP IFAMP III i I I I ' i L +6dBm I

INPUT I [>1[ [r _>,4 __ l l [_ II (_)____> ' ouTPutz75:3o l I l I l 1 5.58.0GHi t .J L J L_ .... / L j c.H_

LO OlOOE_OR 6STAGE FET AMP PS LOSS DUAL GAT.,_._E, AM..__P MIXER If AMP

NF qdBI 4 4 4 6 47 _ 14 _ IO 5 6 4

GAIN (de1 6 6 6 _7 l -<_ -I _ 12 24 --6 5

VOLTAGE IVl :I 3 3 _1 3 4 3 3

CURRENT ImAI 4 4 4 4 4 I 5 26 8

SURMOOULE F = o0 (JB F..,= 14048 +f w` - IF _ F_m m 10 dBNOISE FIGURE f_, . 1OdUB Gm

F II 48dBMONOEIIHI(: HFC|IVI MOI}ULIr

[DIAl I)l: POW[R 250 mW IINCLUDING H illW FOR DIGiTAl CONTROLIOVERALL NOISE FIGURE 4 9 dB IMAX GAINI 5 0 dB IMIN GAINIRf III (:ONV| RSION GAIN 35 lIB I,II_l. _l._lb, 2:1 dH IMIN GAINIMINIMUM D[ I [ C |AH| | SIGNAL IO dl:b.DYNAMI( HANG[ :10 dR IMAX GAINI 4:.111bl IMIN (;AIN,

Figure S-2. Block Diagram of Overall Monolithic Receiver

S-8

f_

L

_o .//---400 MicronFETs

- GatePad--

l 1IN OUT

Figure S-3. Layout of 180° Bit Using Four Series FET Switches

--. S-9

(a)

J --.(b)

FigureS-4.PhotomicrographsofSAG PhaseShifterCircuitson aProcessedWafera) The fourbitphaseshifter(45°,90°,180o,22o)usingseries

FET switchesb) Enlargedviewof180°bit

S-IO

,---- 15o I I I I I i I27 28 29 30 31 32 33

Frequency (GHz)

" Figure S-5. Calculated and Measured Differential Phase Shift for 180° Phase Shifter

s0u Ej[i 91 "i-'i_'i'i'i'i'i.i..91.9

50UREE

Figure S-6. CALMALayout for 100 Micron Gate Width Low Noise FET

__ S-ll

a b 2.7 .01 11.3 : -

,,. I° -•, t Jl"2 -_ ,_[_ . N • b

• BUFFER '5.4 Units

Gate length Lg = 0.25 microns gm = 16.9e'J'"_mS _ -Unit gate width w = 50 microns _ = 2.5 ps pFChannelthickness a = 0.15 microns _=0.07 nH

Dopingdensity N = 2.5 x 1017

Totalqate width Z = 100 microns _[ _Gate-sourcespacing Lsg = .75 microns

Gate metalthickness h = 0.5 microns I 9.3dB @ 27 GHzSpecificcontactresistance rc _-i0"6 ohm.cm2 MAG = 78dB@ 33GHzaI = 0.22

a2 = O.15

N1 = 2.5 x 1017

N2 = 2.5 x 1017

Calculated n(wse figure = 2.5 dB at 32 GHz

Figure S-7. Low Noise FET Design

50t3 46 ° 79 ° . 63 ° 46 ° 79 ° 63 ° 40 ° 57°

=" Stage 1 2 "=- 3 4 "-- 5 = _

TRL's have 7_o= 909Reference Frequency = 29 GHzAllBlocking Cap's = 1PF J-'

34 All FETs 100#m Gate WidthChip Layout ~ 1.58 x 1.25 mm2

_, 33

._R 32

31

3O

29

I I I I I I I25 26 27 28 29 30 31 32

Frequency (GHz)

Figure S-8. Design for Monolithic Five-Stage Amplifier _.

S-12

0.65 mm

< 1.9 mm >

- Figure S-9. CALMALayout for First Two Stages of Gain Control Amplifier

50t2 52° 87.5 ° 47.3 ° 1PF 1.5 nH

22 - AUTRLshaveZ.= 90t2,:, ReferenceFrequency = 29 GHz

21 _ AllFETs = 100 #m GateW_th

20- f • :/_ 18o

17

16-

15 . I I I I I I26 27 28 29 30 31 32

Frequency(GHz)

Figure S-IO. Design for Monolithic 2-Stage Dual-Gate Amplifier

----- S-13The reverse of this page is blank.

If. PROGRAMPROGRESSBYTASKS

The objectiveof the 4 yearprogramis to developa 30 GHz monolithicreceive

moduleforcommunicationantenna feed arrayapplications,and to deliver

submodulesand 30 GHzmonolithicreceivemodulesforexperimentalevaluation.

Key performanceand designgoalsareshownin TableI.

1.0 ReceiveModule Design - TaskI

A major portionof the firstyear'swork was directedtowardsdeviceand

circuitdesign. Thisincludesthe detaileddesignof a 30 GHz monolithic

receivemoduleand foursubmodules.The submodulesare a lownoiseamplifier

(LNA),a phaseshifter(PS),a gaincontrol(GC),andan RF/IFsubmodule.The

submodulesare designedto functioneitherindependentlyor interconnectedto

forma completefunctioningreceivemodule. Accomplishmentsincludethe

design of low noise 30 GHz FETs, switching FETs for phase shifter

applications,amplifierandmixerdesignsas well as the designof switched

line multi-bitphase shifters. To addressthe costgoalof lessthan$i000

permonolithicreceivemodule,ion implantationis the baselinematerials

technologyapproach.

i.iCircuitDesianandTestPlan

The circuitdesign effortaddressedthe designof eachsubmoduleincluding

interfacespecifications,as wellas theoverallreceivemodule. Since the

phase shiftersubmodulesare the firstto be scheduledfor deliveryin the

secondyearof theprogram,a more comprehensivedesignwas completedforthis

submodule than, for example,for the RF/IF or LNA submoduleswhich are

scheduledfordeliverytowardstheend of thethirdyear of the program. In

fact, two fabricationiterationsof the phase shifterdevelopmentWere

completedand evaluatedduringthe firstyear. In addition,a test plan for

testingeachof the submodulesas wellas thereceivemodulein accordancewith

thedesignparameterswas alsocompletedand approvedby the NASA Technical

Manager.

The followingsubsectionsdeal with the specificcircuit designdetails

completedforTask I of theprogram.

i.i.i OverallReceiver

The functionalconfigurationfor the monolithicreceivemoduleis shownin

Figure1 which also indicatesnominal gains, noise figures, dc power

consumption,and overallnoiseand gainperformancefor eachsubmoduleelement

and the completereceivemodule.

The firstmodule functionto be performedis low noise RF amplification,

followedby RF phaseshiftingand gain controlusingsubmicronGaAs FETs.

Frequencydown-conversionand amplificationat the IF is performedwith a

balancedmixer,whichconsistsof a pairof monolithicallyintegratedSchottky

barrier diodesand a GaAs FET IFamplifier.The localoscillatorsignalis

suppliedby the LO amplifier,whichraisesthe reference22 GHz LO signal to

+6 dBm. This LO power is sufficientto drivethepairof mixerdiodes. To

maintaina lowlevelof LO noise,the LO amplifieris designedfor a 5 dB

noisefigure.

The phaseshifteris a passivedeviceandmakesuseof Self-alignedgate (SAG)

FETsto reduceresistivelossesin the channels.Sinceeachsubmodulemustbe

capableof individualcharacterizationandmust thereforefunctionas a

separateunit,thegaincontrolfunctionis implementedat RF (incontrastto

an approachthatwouldrealizepartof thegaincontrolfunctionat IF).

The LNA consistsof five FET stages with an overall noise figure of

approximately4.8 dB and a gain of 32 dB. TheLNA gainis highenoughthat

itsnoisefiguredeterminesto within0.2 dB the noise figureof the total

receive module. This is necessarydue to the lossesand noise figures

associatedwith thephaseshifter,gaincontrolandRF/IFfunctions.

The gain controlfunctionfollowsthe phaseshifterbecauseit is expected

thatthenoisecontributionof thegaincontrolduringminimumgain setting

will be greaterthan that of the phase shifter. Specifically,thephase

shifteris budgetedfor 8 dB loss while the gain controlamplifierduring

minimumgainsettingshas a 1 dB lossanda 14 dB noisefigure. Thisapproach

r_ is verifiedby Friis'formula(aswell as common engineeringsense),which

shows that the overallnoise figureof the two functionsis lowestif the

phaseshifteris placedaheadof thegaincontrol. Itmay be noted that the

higher noisein thegaincontrolis dueprimarilyto thenoisydual-gateFETs

duringthelowerlevelsof amplification.

o

The local oscillatorfrequencyis at 22 GHz,with a resultant5.5 to 8.0 GHz

IF. Withthischoiceof LO frequencytheimagebandis in the rangefrom14.0

to 16.5 GHz. Good image rejectionis achievedbecausethe imagebandis

locatedbelow the cutoff frequencyof the WR-28 waveguide(fcutoff= 21.1

GHz). In the caseof a WR-28waveguideinputto theLNA (asduringsubmodule

RF testing),the imageband will be automaticallycutoffby thewaveguide.

Furthermore,the imagebandis sufficientlyremovedfremthe passbandof the

LNA thata 30 d8 or greaterrejectionwillbe accomplisheddue to the passband

characteristics.

Submodule Intearationand Cb_p LayoutDesig_ - The four submodulesare

interconnectedon a single3 x 9 mm2 carrierplateto formthe interconnected

receivemodule,as depictedin Figure2. Connectionsbetweenthe four chips

aremadewithbeamleadsand thermocompression,or ultrasonicbonding.

Formoduleand suhmoduletestingthe rf inputinterfaceis a WR-28 waveguide

(26.5-40GHz),whiletheLO inputinterfaceis a WR-42waveguide(18-26GHz).

Fin-linewaveguide-to-microstriptransitionsare used at both the RF and LO

interfaces. The IF outputis takenoff the chipby a 50 ohmmicrostripline

to an SMAoutputconnector.BiasandTTL signalsare routedfremthe chip to

externalconnectorsvia appropriateprintedcircuitboards.

An importantfeatureof the testfixtureis that the chip is enclosedin a

waveguide below cutoff. This providesinherentrf shieldingand good

isolationcharacteristicsbetweentheinputandoutputas well as imageband

rejection.

_ The ultimate goal of the program is to achieve a fully monolithic 30 GHz

receiver chip. This approach, if practical, will be implemented towards the

4 end of the programandwillbe basedon the designsand resultsof the inter-

connectedmodule.

1.1.2 PhaseShifterDesi_

_I The phase shiftersubmodulemakesuseof switchedtransmissionlinelengths

and passiveFET switches.Two phaseshiftercircuitdesigns(aswell as two

fabricationapproaches- discussedin SectionII-l.2and II-2.0)weretested.

Initiallya test circuitincorporatingFET switches in shunt with the

transmissionlineswere used. Thisdesignwas employedat firstbecauseit

was considered a more conservative approach and served as an experimental

basis for the following design iterations. The second approach uses FET

switchesin serieswiththe transmissionlines. It has two advantagesover

the former designin that top-sideRF groundingcan be avoidedand the

microstripcircuitlayoutrequireslessGaAsarea.

2_ - An important designconsiderationis the dissipativeloss

r associatedwith the switchesand the microstriplines. As shown in the

following,the dominantlossesoccurin thepassiveFETs.

Microstrip-lineloss is calculatedto be about0.15dB perwavelengthat 30

GHz basedon metallossesonlyanda goldthicknessof 1.5_m for a 50 _ line

on 0.2n_nthicksemi-insulatingGaAs [4].

For theswitchingFETs,however,RF lossesaremuchgreaterand are primarily

associatedwith the parasiticresistancesof the device. Figure3 shows

simplifiedequivalentcircuitsforan ON and OFF FET,namelya singleresistor

for the ON (low impedance)stateand a seriesresistor-capacitorcombination

for the OFF (highimpedance)state [2-5]. The capacitorCoff is the total

pinchoffcapacitancebetween sourceand drain,and the resistorrs is the

totalseriesresidualresistanceat pinchoff(undepletedchannelresistance

plus sourceand drain contactresistance).To increasetheRF impedanceof

theOFF state,an inductorL parallelresonatestheRC combination.For this

case, the effective RF OFF resistance at resonance,Roff,is closely

approximatedby Roff = Q2crs= (_rsC)-2rs = (C)-2rs-I. NotethattheratioA

Roff/Ron is to firstorder,justthe figureof meritQ as definedby Kurokawa

and Schlosserfor a switchingdeviceswitchingbetweentwo impedancestatesZ1

and Z2.

It can be shownthat

_(Ronrs)-i(_C)-2= Roff/Ron [2,3]

It is clearthatthe figureof meritdegradeswithfrequencyand has smaller

valuesat millimeter-wavefrequenciesthanat lowermicrowavefrequencies.To

maintainthe figureof merithigh it is essentialto reduceRon and rs (andC

if possible).

A specificexampleof an idealRF switchincorporatingconventionalpowerFETs

I

fortheswitchingdevicescanillustratethelossesincurredat 30GHz. Fora

typical 300 #m power FET, Ron = ii-14_ and with C = 0.07 pF and rs = 5_,

Rof f is about I000_ at 30 GHz. By choosing these ON and OFF resistance

-" valuesand usingthemin an idealSPDTswitchconfigurationas shown in the

inset of Figure4, we can calculatethe idealinsertionlossand isolationof

a singleswitchat centerfrequency.Furthermore,by scalingRon, rs,andC

for other gate widths, an estimate can be made of the best compromise between

isolation and insertion loss. Note that this leaves the figure of merit Q

_- invariant. These considerations are summarized in Figure 4 where the

insertion loss and isolation at 30 GHz are calculated as a function of gate

width for two different Q values. Note that for the dashed curves which

represent a reduction in Ron and rs (14_ to 4.7_ and 5_ to 2.4_,

respectively), the loss is reduced by 0.6 dB at a gate width of 300 #m, for a

single SPDT switch. For a four-bit switched line phase shifter this amounts

to nearly 5 dB less insertion loss. As shown in Section II-l.2.1 such

reductionsin the parasiticresistanceare possibleusingthe self-aligned

fabricationprocess.

First Desiqn:180° - 1 Bit PhaseShifter(ShuntFETs)- Figure5 sh_s the

chip layoutfor the 180° bit. Four switchingFETs are used to RF switch

betweentwomicrostriplineswhosedifferentialelectricallengthis equalto

180oat centerfrequency.TheFETsarepassiveinthesensethatno dcbias

is appliedto thedrainandonlya switchingvoltage (0,-6V)is used at the

gate [4-6]. The circuitutilizesa pairof SPDTswitchesrealizedby four,o

300_m gatewidthFETsin shuntacrossthe50_ transmissionlineswith each

FET located at a distance of _g/4 (0.8 mm at 30 GHz on GaAs) from either the

7

inputor outputT-junction.

The circuitlayoutis conservativein thatthe arearequired(chipdimensions

are 3 x 2.67x 0.2mm3)hasnot beenminimized.Thiswas doneto ensurethat

the couplingbetweenadjacentsectionsof transmission lines would be

negligibletherebyfacilitatingevaluationof initialRF performanceresults.

The 0.2ma substratethicknesswas chosenas a compromisebetweenincreased

microstrip transmissionline loss and extraneouscapacitiveparasitics

(thinnersubstrate),and increasedcircuitlayout dimensions (thicker

substrate). Pads are providedat the edgeof the chipfor grounding.For

thesetests,groundconnectionis accomplishedby a seriesresonantcircuit

consistingof an external0.ipF capacitor(bottomplatesolderedto ground)o4

and a mesh wire inductorconnectingfrom the capacitortop plate to the

groundingpad on the chip. To increasethehighimpedancestate(V=-6V),a

shortsectionof lineprintedon the chip is used to resonatethe pinchoff

capacitance betweendrainand source (C_ 0.07 pF) for each FET. High

impedanceto the gateterminalis providedby bendingwireinductance.

SecondDesign:Multi-BitPhaseShifter(SeriesFETs)- To improvetheexpected

performance of our multi-bitphase shifter,a series switchdesignwas

implemented. A representativelayoutfor a 180° bit is shownin Figure6.

Four,400microngatewidthunbiasedFETswith five80 micronfingersper FET,

are used in the seriesconfiguration.The areaper bit is almosthalvedfrom

thatof a shuntdesign. Figure7 shows the calculateddifferentialphase.

Over a 4 GHz band the differentialphasecharacteristicis within2° of the

idealcurve. Foran assumedON resistanceof 9_ anda pinch-offresidual

8

series resistanceand capacitanceof 4.5_ and .09pF respectively,the

lossis about2.3 dB per bit.

The designof a 3-bit phase shifterusingseriesFETswitchesis similarto

the 180o bit exceptthatdifferentiallinelengthsof 450,90°, and 180° arep

used. To improveinsertionlossandphasetrackingaccuracyover the band,

-- impedancematchingelements (a shortsectionof high impedancelineand a

shuntstub)are usedfor the45° and 90° bits. All threebitsuseexclusively

seriesswitches.Thelayoutfor all 3-bitsis realizedin an area of 2.5 x

4.1ram2.

Figure8 showsthe calculateddifferentialinsertionphaseresultsforall

eightstatesoverthe 25 to 33 GHz frequencyband. The calculatedvalues

(shownas discretepoints)are shownrelativeto the idealcharacteristics,

i.e.,timedelayscorrespondingto thevariousphasestates.The resultsshow

thatoverthe bandof interestthecalculatedvaluesarewithin2 or 3 degrees

of the idealcurve. For thesecalculationsthecomputerprogramCDMPACT was

used. The circuit model included 12 switching FETs, interconnecting

°- transmissionlinesandmatchingnetworks.For theOFF state,the FETswitches

were representedby a 4.5_ resistorin serieswitha pinch-offcapacitance

-- of .09 pF, and the combination parallel resonated by a high impedance 90

transmission line. The ON states were modeled by a simple series resistance

of 9_ (and the 90_ transmission line in parallel).

Figure9 shows the "envelope"for the insertionlossforall eightstates.

All lossesin the switchingFETsand lossesin the transmissionlineswere

9

includedin the calculations.Overthe bandof interestthe insertionlossis

about6.5 to 7 dB,witha spreadof about0.5to .75dB.

1.1.3 _

_e gaincontrolsubmoduleis requiredto providefivelevelsof RF to IFgain

(30,27, 24,20 and 17 dB)and an off state. To maintainthe noisefigure of

the receivemoduleat 5 dB, theworstcasenoisefigurefor the gaincontrol

submoduleis budgetedat 14 dB.

Two criticalrequirementsof this submoduledictateto a largeextentits

design:the requireaentfor a 1 dB attenuationstatewitha noisefigureof 14

d8 or better,and a +12 d8 gainstatewithan allowableinsertionphasechange

of no more than +5o over the full 13 dB gain range. Also,the uppergain

level is limitedto a maximum of +12 dB to ensurea 30 dB dynamicrangefor

theoverallreceiver.Highergainsand subsequenthigherdrive levelswould

resultin overdrivingthemixer,thusreducingthe 1 dB gaincompressionpoint

of the receivemodule.

The requirementscitedabovewill be met with dual-gateFETamplifiersby

controllingthe secondgatevoltage.Tne dualgateFETwitha 0.5microngate

length is expectedto providea maximum gainof aboutI0 dB at 30 GHz. By

controllingthesecondgatevoltage,thegaincanbe adjustedat least over a

20 dB dynamicrangeto an attenuationstateof -i0 dB.

10

Two problemsarisein usingonlyone dual-gatedevicefor gaincontrol:noise

_ and phase shift. Liechti [7] and othershaveshownthatthenoisefigure,

althoughnotmuch degradedfrom a singlegate deviceduringmaximumgain,

_ degradesdrasticallyas the deviceis driventowardan attenuationstate. For

example,at I0 GHz,Liechti showsan ii d8 degradationfroma 4.1 dB noise

figureat an associatedgainof 12.8d8, to a 15 dB noisefigureat a gainof

2 dB. The insertionphaseshift,as a functionof the secondgate voltage,

also variesconsiderablyas the dual-gateFETis broughtfroma gainstateto

-- an attenuationstate. Thus,a singleamplifier,althoughhavingconsiderably

greaterthan13 dB dynamicrangein gain,is inadequatefroma noiseand phase

shiftpointof view.

To overcomethesedeficiencies,a two-stagedual-gateFETamplifier,followed

by a variablepassiveattenuator,is usedforthegaincontrolsubmodule,as

shown in FigureI0. Thefirststagehas gainstatesof 3 and 6 dB, whilethe

- secondstageamplifierhas threegainstatesof 2, 5 and 8 dB. These states

are achievedby applyingproper controlvoltagesto the secondgate. The

switchedattenuatormakesuseof thepassiveSPDTswitch(describedin earlier

sections)to form two switchablepathsof unequalloss. Themajorityof the

lossin thepathof minimumattenuation(-2 dB path) residesin the series

_ unbiased FETs. In the secondpath, a 4 dB increasein attenuationis

required.Thiscanbe realizedeasilyby incorporatingeithera thin film

seriesresistorevaporatedonto the substratefor a sectionof the50 ohm

line,or highresistivityselectiveion implantscanbe incorporatedbeneath

the microstriplineto forma lossysectionof line. Notethatthe tolerance

of the lossis notverycritical,i.e.,on theorderof 1 dB, sincechangesof°

this magnitudecanbe compensatedby thedualgateamplifiers.Someunwanted

phase shift in the dual gate amplifiers can likewise be compensated for by the

switched attenuation, by altering the length of one of the paths.

Preliminary Design - For initial development, a two-stage dual-gate FET

amplifier design is employed. The design is based on the i00 micron gate

width FET discussed in Section II-1.2.2. A cascode connection of two such

FETs are used for the equivalent circuit of a dual gate FET. (Common source

firststage,comaongatesecondstage[7]).

Figure ii shows the circuit schematicand the computeroptimizedgain

characteristicfor the twostagedualgateamplifier.From 27 to 30 GHz the

gain is 20.4 + 0.i dB. The inputand interstagenetworksare on-chipwhile

the output impedance matching network includes a bond wire inductor. This

last feature is incorporated to facilitate initial rf circuit evaluation.

Developmentand testingof thepassiveswitchedattenuatorport_onof the gain -

controlis beingdonein parallelwith theinitialphaseshifterdevelopment

discussedearlier.Subsequentiterationsof thegaincontrolwill includethe

passiveattenuatoron thesamechip. 4

1.1.4 RF/IF Submod_le

TheRF/IFsubmodulehas threefunctions:

o Convertthe 27.5 to 30 GHz inputRF signalto the IF (5.5GHz) in a

mixer.

o Amplify an external reference signal to provide a local oscillator

12

input(22GHz) to themixer.

-- o Amplifyand bufferthemixerIFoutputto drivethe IF amplifiers.

The technicalapproachesforachievingthesefunctionsare discussedbelow.

BalancedSchottkvDiodeMixer- Our baselinemixerdesignapproachwill be the

balancedSchottkydiodemixerwitha rat racehybridwhichis shownintegrated

with the other elementsof the RF/IF submodulein Figure 12. The input

signal,insertedon the rightsideof thechip,is shiftedin phaseby 90° to

one mixer diode, and 2700 to the other. The diodes are connected 180° out of

phase to suppress noise from the local oscillator amplifier and reference

signal, while combining the IF signals in phase. The diodes are connected to

IF frequency and dc ground by vias through the substrate; open circuited stubs

are used to ensure a high quality ground for the signal and local oscillator.

The mixer employs a pair of surface oriented Schottky barrier diodes so that

°- fabricationis compatiblewith that o_ the FETs. Effortsto developsuch

diodeshavebeensuccessfulin thepast. Thebestdiodes,usingthickactive

layers,have cutoff frequenciesgreaterthan200GHz [8,9]. Recentresults

[9]wereobtainedusingmany smalldiodes in parallelto lower the overallF.

seriesresistance.The diodesto be usedin thisprogramwillbe an extension

- of thesetechniquesas indicatedin Figure13. By decreasingthecapacitance

of the individualdiodeswhilemaintainingan approximatelyconstantvalueof

seriesresistancethesemethodsshouldbe usefulat 30 GHz.

22 GHz LO _mplifier- The requirementsforthe 22 GHz localoscillatorinclude

a gain of 24 dB and a noise figure of 5 ds. Other than frequency,the

requirementsare similarto theRF low noise amplifierused for the "front

end" of the receiver. Consequently the i00 micron gate width FETs discussed

in Section II-1.2.2 which are designed for the RF LNA are also used for the LO

amplifier.

m

To assess the noise figure and gain trade-offs for the i00 micron FET at 22

GHz, the noise figure and gain circles were calculated and plotted on the

Smith Chart as shown in Figure 14. The 3 stage amplifier shown in Figure 1

and 15 is designed to achieve the required 24 dB total gain and yet realize

the source impedance (e.g., z s = .6 + j 1.2) as seen by the first stage

especially, to be in the region of minimum noise using Figure 14 as a

guideline.

The theoreticalcalculationof the total gain over the frequencyrange from 20

GHz to 24 GHz is sh(_n in Figure15, and is about 26 dB. The overall gain

flatnessis within 0.3 dB, and the layoutestimatedarea about 2.44 x .53ram2. -

-Tne IF amplifier is primarily needed to buffer the mixer output

to drive lower impedance transmission lines. The requirements include 5 dB

gain from 5.5 to 8 GHz. A preliminary design using a 150 micron FET

equivalent circuit in a single stage common source configuration was

developed. The circuit design makes use of the so-called "lossy" match

technique, i.e., frequency dependent resistive loss is used to obtain flat

gain over a 60% fractional bandwidth. A gain of about 6 dB is achieved from 5

to 9 GHz.

14

1.1.5 _0 GHz Low NoiseAmplifierSubmodule

Five stagesof GaAs FET amplificationare usedin theLNA. The firstthree

stagesare designedfora noisefigureof 4 d8 and an associatedgainof 6 dB,

while the last two stagesare budgetedfor slightlyhighergainsand noise

figuresas was shownpreviouslyin Figurei. The numberof LNA stagesis

chosenlarge enoughto achievesufficientfront end gain to minimizethe

effectsof noise figurecontributionsand lossesof followingsubmodule

-- componentson the totalnoisefigureof thereceivemodule,whichis to be 5

dS.

Because of thelow dc powerconsumptionbudget(3Vand20 mA for the complete

LNA)and the theoreticallypredictedimprovementof devicenoise figurewith

smallergatewidths,theFETsusedin theLNA havegatewidthsof i00microns

(andsub-half-microngatelengthsas discussedin SectionII-1.2.2).Although

pk even smallergate widths are desirablefroman efficiencyandnoisefigure

point of view, a lowerlimit on gate width exists becauseof impedanceL

matchingconsiderations.In particular,too smalla gatewidthresultsin

high impedancelevelswhichare difficultto matchto 50 ohms (especiallyfor

the FET outputcircuit). This is due to designconstraintsimposedby the

.... physicallimitationsof monolithicallyfabricatedreactivecircuitelements.

The most direct consequenceof thisdifficultyisbandwidthreductiondue to

-- largeimpedancetransformationratios.

An initialdesignfor thefivestageamplifieris shownin Figure16. TheFET

equivalentcircuitdiscussedin SectionII-1.2.2is usedforthe FET devices.

15

As shown in the figure the gain is the required32 d8 _+.5dB from27 to 31

GHz. Inputimpedancematchingtakes into accountthe gain/noisefigure

trade-off(seeSectionII-1.2.2)especiallyfor thefirststage. As shown in

the figurethe designutilizessimilarcircuitelementswhichare relatively

easyto realizemonolithicallyon a 0.15rsnthicksubstrate.

It shouldbe noted thatthe designactivityandresultingcircuitschematics

presentedabove are strictlystartingpointsfor the developmentof the

various receiverfunctions.Theyserveto definethedesignmethodologyfor

subsequentdesigniterations.As experimentaldata is obtainedthe various

equivalent circuits will be up-dated and revised for final design

implementation.

1.2

Duringthe first year devicedesigncenteredaroundthelow noisei00micron -

gatewidthFET,and the 400micronswitchingFET for implementationin the

passive phase shifters. For theswitchingFET the primarygoalis to reduce

thechannelresistanceand resistiveparasiticsof the deviceto minimizethe--4

insertionloss of the 30 GHz SPDT switchesusedin the switchedlinephase

shifters.For the100micronFETsthegoalis to achievea deviceperformance

of at least 4 dB noisefigurewith an associatedgainof 6 dB at 30 GHz. As

shownin thissectionit is expectedthatsub-half-microngatelengthswillbe

required.

1.2.1 SAGFET forPhaseShifter

16

By usinga n+ implantself-alignedFET [i0]switchin the phaseshifterstwo

objectivescanbe achieved:First,realizationof a lowvalueof ON resistance

for minimizing insertion loss, and second,low power consumptionfor

minimizingtheoverallDC powerconsumptionof thereceivemodule. The latter

objectiveis met becausethe switchingFETsare basically"unbiased"FETs,

whereonlya controlvoltageis appliedto thegateelectrodes.

The principlefactor limitingthe reductionof the "ON"resistanceof the

self-alignedstructureis thesheetresistanceof thechannel.The calculated

sheetresistanceunderthe gateas a functionof gate-to-channelvoltagefora

relativelyheavyimplantof 5 x 1012siliconatc_s/cm2is shownin Figure17.

Thiscalculationincludestheeffectof thevaryingdepletiondepthunder the

gate. The maximum electricfield in the device for completedepletion

(pinchoff)is approximately480Kv/cm,assuminga Gaussiandopingprofile.

The sheet resistanceshownwas calculatedusinga mobilityof 4000cm2/v-sec

independentof doping. Increasingthe implantenergydecreasesthe channel

_ sheet resistanceat the price of a largerpinchoffvoltage.Somereduction

canbe achievedby forwardbiasingthegatebut the sheet resistancevalves

-- shownin Figure17 are probablycloseto thebestwhichcanbe achieved.

_r

Combiningthechannelresistancewith ohmic contacts (lineresistance)and

self-alignedn+ regionthe source-drainresistanceshownin Figure18 is

calculated. The resistancegivenin thisfigureis conservativein thatn+

sheetresistancesof 100 ohms/squareand lineresistanceslessthan0.iohm-_m

17

are expectedto be achievedin an optim_-nSAGprocess.For example,witha 5

source-drainresistance(theON state)it is expectedthatthe insertionloss

per bitshouldbe between1.5 and 2 dS.

1.2.2 i00MicronLow NoiseF_T

The I00microngatewidth.25microngatelengthlow noiseFET is thecritical

elementin the low noise receiverfrontend. This sectiondescribesthe

design of the i00 micron gate width FET. The description of the FET design is

separated into three subsections: I) Rationale for Low Nois_ FET EW$i_n which

describes the basic reasoning used to determine the requirement for a .25

micron gate length and i00 micron gate width, 2) Low Noise FET Equivalent

which describes the calculations used to arrive at an equivalent

circuitfor theFETand 3) GainandNoiseCircleCalculat_on_whichdescribes

the calculationof tradeoffsin circuitmatchingforgainand noisefigure

basedon theequivalentcircuitmodel.

RationaleforLow NoiseFETDesign- The FET requiredfor use in the lownoise

amplifiermust have a 4.0 dB noise figurewith a 6 dB associatedgainper

stageto achieveoverallreceivemodulenoisefigureof 5 dB.

The devicedesignmustconsidermaterialand geometricparametersthatimpact

thefollowingrequirements:

o Low noisefigure

o Highfrequencygain

o Low powerconsumption

18

Devicedesign requirementsfor a low noise figurecan be identifiedfrom

-- Fukui'snoiseequation[ii,12]which is known to give a good relationship

betweendeviceparametersandan experimentallymeasurednoisefigure.

r i0oi011E3- w- o. w2hL i12 (I)

1.8Ls- /0.18r_ 1/211/2

where

F = noisefigure(dB)

L = gatelength(microns)

k = noisecoefficientdependenton material(typically0.033to 0.040)

Lsg = gateto sourcespacing(microns)

rc = specificcontactresistance(10-6 ohm-om2)r-

P = gatemetalresistivity(10-6ohm-ore2)

- w = unitgatewidth(nm0

a = channelthicknessbeneaththe gate (microns)

- aI = channelthicknessbeneaththesource(microns)

a2 = channelthicknessin region2 (microns)

N = carrierconcentrationin theactivechannel(1016cm-3)

_ N1 = effectivecarrierconcentrationbeneaththesource(1016cm-3)

N2 = effectivecarrierconcentrationin region2 (1016cm-3)

h = gatemetalthickness(microns)

19

f = frequency (GHz)

The various thickness regions (aI, a2) , identified in Figure 19 are due to

recessetching.Surfacedepletionmustbe takenintoaccountwhen determining

a2. The firsttwo termsin bracketsin equation(i)are dueto thegatemetal

resistance.The firsttermis thedc gateresistance;thesecondterm is due

to skin effect. Term three is due to the material resistance in region two.

The fourth term is the contact resistance. Equation (i) can also be written

F = i0 lOgl0 [i + C(Rs + Rg)I/2] (2)

where Rs is the source resistance, Rg is the gate resistance, and C is a

constant dependent on material, frequency, gate length, doping density, and

channel layer thickness.

Examiningequation (i) shows that the devicerequirementsfora low noise -

figureare:

o Gate lengthshouldbe as shortas possible.

o Gate metal resistanceshouldbe low so Rg <.Rs. Thisimplieslow

metalresistivityandthickgatemetal.

o Source resistance should be as low as possible. This implies low

contact resistance and increased doping density and thickness in the

regions between the source and gate.

Requirements for high gain can be identified from the equation for the

unilateral gain, Gu, of a FET [13].

20

Gu= [gm/(2zrCgs)] 2 1(2f)2 _ds(Rg+Rs)+2zrftRgCdg] (3)

where

gm = transconductance

Cgs = gate-sourcecapacitance

Cdg= drain-gatecapacitance

Gds = outputconductance

ft = unitycurrentgainfrequencygm/(2_ Cgs)

Tne transconductanceandgate-sourcecapacitancecanbe expressedin terms of

materialand geometricparameters.

So that

gm Vs

2_Cgs 2"_"L"

where

vs = saturationvelocityof electronsin the channel

and

Gu = s . 1 . (4)

_. 16zr2L2 ds(Rg+Rs) RgCdg

Equation (4) indicatesthat some of the requirementsforhighgainare the

same as for a low noise figure,i.e.,gate length shouldbe as shortas

possibleandgate and sourceresistancesshouldbelow. In addition,bothGds

and Cdg shouldbe madeas low as possible.

21

Powerconsumptionis another considerationin the FET design for this

application. The power consumptionis given by the productof the drain

sourcevoltageand the draincurrent.A reasonablevaluefor thedrainsource

voltageis 3 volts. If the draincurrentis 4 milliamps,the Idss of theFET

will be I0 timesthe low noise bias value, or 40 milliamps. _e Idss is

related to material and geometric parameters by

Idss! q N vs Z(a-d)

whenthe FEToperatesin thevelocitysaturatedmode.

where

d = zerobiasdepletionwidth= 0.067micron

a = channel thickness = 0.15 microns -

vs = 107 cm/sec

N = 2.5 x 1017 cm-3

So the total gate width Z must be:

Z S 120 microns

Since 120 microns is too long for a unit gate width, the gate will be broken

up into two sections. We use a i00 micron total gate width, with a unit gate

width of 50 microns. This gate widthwill givea reasonableimpedancefor

22

matching networks.

Combining the requirements for low noise, high gain and low power consumption

gives the FET constraints that impact the final design. Tne gain is increased

and the noise figure is reduced by minimizing the gate length.

The factorswhichlimittheamountof gatelengthreductionare:

o E-beamlithographyprocessinglimitsforreproducibility.

o Channel thickness and doping control implied by channel dimensions for

best performance.

Consideration of these factors with present processing technology makes a 0.25

micron gate,a channellayer 0.15 micronthick,and 2.5x 1017cm-3 doping

reasonablechoicesfor thedevicestructure.

Gain and noise figureare also enhancedby minimizingthegateand source

resistance.The gate resistancecan be reducedby using increasedmetal

thickness and low resistancemetalsto fabricatethe gate. The source

resistanceismost stronglyaffectedby the dopingbetweenthe sourceand

_ gate, the geometryof this regionandohmiccontactquality. Initially,we

will usea source-gatespacingof 1 micronto easealignmentrequirements,but

-- it is expectedthat advancesin technologywill permit reductionof this

dimension.Othertechniqueswhichwill be employedto minimizethe source

resistanceare (i)recessedgate, (2) optimizeddopingprofilesand (3)n+

surfacelayerswithadvancedcontactingmetallurgyforoptimumohmic contact

characteristics.

FET designparametersanda calculatednoisefigurebasedon thisdiscussion

are givenin Table2.

A final design considerationis the output conductanceand drain gate

capacitanceof the FET. Althougha formulafor the output conductancewas

developedby Pucel,Haus,andStatz[14],it predictsa Gds muchlowerthanis

actuallymeasuredon FETs. It is believedthisis dueto substrateconduction

[15, 16] near the high field region. In an ion implantedFET,the output

conductanceis undoubtedlyinfluencedby implant distribution and the

substratequality,althoughthe outputconductancecan be decreasedby theuse

of an AlxGal_xAsbufferlayer[16]or an insulatingregionbetweenthechannel

layerand substrate[17]. We do not believe the increasein processing

complexityis warranted.

FET performanceis influencedby a complexrelationshipbetweenequivalent

circuitelementvalues that are affected by materials and processing -

limitations. Therefore,the final FET designwill be achievedthrough

experimentalmeasurementsand computeraidedmodeling.

Low Noise FET EquivalentCirCuit- As discussedin the preceedingsection,a

i00 micron gate width FET with a .25 micron gate length is required to meet

the gain and noise figure goals for the rf receiver. To design the multistage

amplifier an equivalent circuit model for the FET is needed. This section

will describe the equivalent circuit model for the FET and the procedure used

to arrive at the element values used in the model.

24

The equivalent circuit model for the FET is shown in Figure 19b. Some of the

-- element values are calculated from theory while others are determined by

measurement or scaling. The FET gate width is chosen to be I00 microns to

ease input matching requirements and minimize the effects of phase shift of

the 30 GHz input signal along the gate.

_ The circuitelementsthatcanbe calculatedfrommaterialparametersand

device geometryare: the gate resistanceRg, the inputcapacitanceCgs,the

-- transconductancegm, the sourceresistanceRs, thedrainresistanceRc, and

thephaseshiftfactorr . These elementvalueswere calculatedfrom the

followingequations:

pW --

Rg = _- 2. 7fl

.- Rs = Rc + Rsg = 5.4-fZ

Rc = _= 1.8_Z

- Ps2Lsg - 3.6_2Rsg - Z

25

PS1 = sheetresistanceof semiconductormaterialbeneaththe ohmic

m

_ I = 325ohmsper squareNq_aI

q = electroncharge= 1.6x 10-19coulcmbs

= electronmobility= 3500cm/v-sec

p_ = sheetresistanceof materialin source-gateopeningexcluding _1

- - 476ohmsper squaresurfacedepletedregion Nq#a2

Rd = Rc + Rdg = 11.3ohms

Rc=_Pc_ 1.8ohmsz

Ps2LdgRdg= Z =9.5ohms

Ldg = 2 microns

(,o,,qN 1/2

eo = 8.854x 10-14 fd/cm

26

€r = 12.5

#hi= builtin potential= .8V

_ Vg = appliedgatevoltage= 0V

_ L = Leff = effectivegatelength= physicalgatelengthplus

activelayerthicknessto correctfor fringingcapacitance=

0.4microns

gm = VsZ qNe°er']= 16.9mmho_2(q_bi-Vg)J

VS = Saturationvelocity= 107 cm/sec

L_"=--=2.5psec

_ V s

The remainingequivalentcircuitelements:thedrain-gatecapacitanceCdg, the

drain-sourcecapacitanceCds, the resistanceRi andthe outputresistanceRo

cannotbe accuratelymodeled.Our approachis to useexistingpublicationson

quarter micron gate FETs [18-20]togetherwith COMPACTanalysisof the

equivalentcircuitto estimatevaluesfortheseelements.For theseelements

we havechosenthevalues:

Ro = 700 ohns

27

qg-.01pf-.04

Ri= 6 ohms

The complete equivalent circuittogetherwith a tableof criticalFET

parametersare givenin Figure19. The calculatedmaximumavailablegainis 8

dB at 32 GHz. Fukui'snoise equationpredictsa noisefigureof 2.5dB for

the FETmodel. All designequationsarebasedon a uniformdopingmodelwhich

is typicalfor FETsmadewithVPE material.The useof ionimplantedmaterial

shouldnot significantlychangethesevalues.

Gain and Noise Circle CalculatioDs- UsingCOMPACTtheS parametersfor the

FET equivalentcircuitwere calculatedas givenin Table3. Noiseparameters

for the FETcan be calculatedaccordingto a paperby Fukui[21,22] using:

Fmin = 1 + .016f Cgs _g+ Rs

• gm

Rn = 0.8/gm

Xop = 160/(f Cgs)

Rop = 2.2 [4-_m+Rg+RsJ

where

f = frequencyinGHz

28

Cgs = capacitancein pf

gm = transconductancein ohms

Rg = gateresistancein ohms

Rs = sourceresistancein ohms

Fukui'smodel, on which thesecalculationsare based,doesnot considerthe

effectof sourceinductanceor gatedraincapacitanceon highfrequencynoise

figure. The effectof the feedbackelementson noisewere calculatedusinga

programfor theHP41Cwritten by Suter [23]. Gain circlesare calculated

usinganotherHP41Cprogram,GCIR.

Using these HP41Cprogramsthe gainand noisecirclesfor the FETinputand

outputplanescanbe calculated.For theFukuinoiseanalysisthe equivalent

circuit does not includeCdgor Ls. By usingtheS parametersfor themodel

with no Cdg or 5s (Table4a) with no CdgbutwithLs, (Table4b),andwith

both Ls and Cdg (Table5), the noise circlesfor the input plane can be

calculatedas shown in Figures20 and 21. These figures illustratethe

tradeoffbetweengain and noisefigure. Thenoisefigurereductionfor the

- case includingCdg andLs may be in errorsincethecalculationmodelassumes

Cdg is connectedin shuntfromthe inputterminalto the outputterminal.In

-- any case,the modellinggivesa good indicationof the gain-noisefigure

tradeoffsince there is not a lar°gechangein the gain and noise figure

circles. In a similarway the gain circlesfor the FET outputplane are

calculatedandthe resultsare shownin Figure22.

A finalitemof interestthatcanbe calculatedis thevariationof gain and

noise figure with changesin sourceand gate resistance. This type of

calculation has been used by Yamasaki and Schellenberg [24] to show that the

gate resistance has a stronger influence on high frequency gain that the

source resistance. Since the maximumavailablegain Gmax is affectedby

stabilityconsiderationstheyuse theunilateralgain,Gu, forcomparison.We

havecalculatedthe effectof gateand sourceresistanceon maximumavailable

gain and noise figureandplottedthe resultsas shownin Figures23 and 24.

Themaximumavailablegainwas calculatedusingCDMPACTand the noise figure

using Fukui's noise equation. These graphs indicate that both source and gate

resistances have a significant affect on gain and noise figure. High source

resistance can cause the FET to become unstable. In summary, these

calculations of gain and noise circles based on a model for a .25 micron gate

length, i00 micron gate width, GaAs FET indicates that the noise figure and

gain requirements for the front end of the NASA low noise receiver can be met

with reasonable matching networks.

30

2.0 l_aseShifterFabricationand Evaluation- TaskII

During the first year results were obtained on two phase shifter mask set

designs; the single 180o bit phase shifter using shunt FETs and a more

comprehensive mask set that includes multi-bit phase shifters using series FET

switches. Two fabrication approaches were also tested; one uses standard

-- power FET fabrication and a second approach employs a new self-aligned gate

(SAG) fabrication technique for reduced parasitic resistive losses in the

switching FETs. Much of the work, which is still incomplete, has been to

develop a reproducible and reliable SAG fabrication process. Nevertheless,

preliminary RF results have been obtained on SAG phase shifters which have

_ been sufficiently encouraging to commit our final design and fabrication

approach to the SAG technique.

To put theSAG resultsin perspectivewe presenttypicalphaseshifterresults

for the 180o bit using conventionallyfabricateddevices. For one run,

typicalFET ON resistance,Ro'n, as measuredon the curve tracer,ranged

between 12.5 and 15.5 ohms on dc good phase shifterchips. For Circuit

_ modelinga value of Ron = 14_ , a residualseriesresistance,r = 7_ ,

and a pinch-offcapacitanceof .07pF was usedto comparewith the measured

-- results [2]. Figures25,26aand 26b showthemeasuredinsertionphase,the

rf testfixture(coverremoved),and themeasuredinsertionloss (including

1.4 dB fixtureloss)respectivelyforone of the phaseshifterchips.

The RF test fixturehas in-lineWR-28 waveguideinput and outputports.

Antipodelfinlinetransitionsfabricatedon 0.25 mm thick RT/duroidare

employed to transition from waveguide to microstrip. The 1.4 d8 fixture loss

includes mismatch loss ( .4-.6 dB) as well as dissipative loss in the total

circuit comprising the transitions and interfaces to the GaAs chip. Figure 27

shows the phase data plotted together with the calculated results. Note the --

calculated results are in closer agreement with the measurements when a 0.i pF

shunt capacitance is included for each of the four FETs in the circuit model

(see reference [2] for details). This parasitic capacitance is associated

with the layout metallization of the FETs and can be decreased as will be

shown below in the series FET switch design.

2.1 Results for 180o SAG Phase Shifter Using Shunt FET_

Figure 28a shows the encouraging results obtained for the insertion loss for

the two phase states across the 27.5 to 32.5 GHz band. As seen from the CRT

traces, the insertion loss including test fixture loss is between 4 and 5 dB

in the band of interest, 27.5 to 30 GHz. This is in contrast to 6 to 8 dB

loss for the corresponding measurements made on the conventional phase shifter

chip as was shown above. Figure 29 shows the comparison between the

calculated and measured results including the 1.4 d8 test fixture correction.

As shown in the figure the calculated values are based on the values of the

FET parameters measured off test FETs on the SAG wafer. The reasonable

agreement obtained justifies the use of our simple equivalent circuit model

used for the ON and OFF FETs. Additionally, it should be noted that this

wafer demonstrated a limited amount of surface conduction (conversion) which

could account for some of the discrepency between measured and calculated

values as the circuit model does not include such effects.

Finally,Figure28b shows the measureddifferentialinsertionphasefor the

SAG phase shifter,from 27.5 to 30 GHz. Overthisbandthephaseis within

20o of the calculatedcurve. Note,again,the tendencyfor thedifferential

phaseto decreasetowardstheupperhalfof theband.

-- 2.2 Results From Second Mask Set Using SAG Series Switches

A comprehensivemask set has been developedthat includesmulti-bitphase

shifters.Figure30 showsphotomicrographsof someof the circuitpatternson

the finishedwafers. Figure 30a shows the four bit phaseshifternetwork

_ (45o,90°, 180°, 22°) while Figure30b is an enlargedviewof the 90 bit.

These phase shiftersemploy 400 microngate width series FETs for the

switchingdevices.The 180°, 90° and 45° bitsare switchedlinetypes,while

the 22° bit is of the loadedlinetype. To date,one SAG fabricationrunhas

beencompleted.As seenin thefollowing,theRF insertionphaseresultsfor

the individualbits (180o, 90° and 45o)supportthepredictedadvantageof the

seriesswitchcircuitdesign. Unfortunatelyour firstrun had low yield and

_ did not attainthe low resistancevalues (<8_)we were hopingfordue to

severalfabricationrelatedproblems.Thesearepresentlybeingcorrectedfor

"- the secondrun. Nevertheless,phase shiftdataobtainedon the individual

bitsis quiteencouraging.

Figures 31-33 show the measured differential phase for the three bits across

the 27.5-32.5 GHz band and the comparison with the ideal time delay

characteristics. The measured data is taken with the H.P. network analyzer

usingthe 26-40GHzwaveguidereflection-transmissiontest set. Although

displaceddownwardsby about70,themeasureddatafollowscloselythedesired

slopeof thecharacteristic.Notetheimprovementfrompreviousphasedata

using the shunt design. This improvementis primarilydue to the more

optimizedlayoutand the reductionin reactiveparasitics.Figures34 through

36 showthe actualmeasureddatafor theinsertiondifferentialphase,the

insertion loss, and the return loss respectively from 27.5 to 32.5 GHz for the

180 ° and 45o bits. In Figure 35 the insertion loss includes the fixture loss

of about 1.4 dB and is better than the results obtained with conventionally

fabricated FETs but worse than the best SAG result obtained on the 180o bit

using shunt FETs.

34

3.0 Gain Control Fabrication - Task III

The maskdesignfor thefirstiterationof thegaincontrolis complete. The

layoutcontainsthe followingcircuitsand devices:

o i00microngatewidthlownoiseFET.

o Low noiseFETwithstubinputmatching.

-- o Low noiseFETwith capacitormatching

o Dualgate100microngatewidthFET.

o DualgateFETwith capacitormatching.

o Two stagedualgateamplifierforgaincontrol.

o Testpatternsfor in-processtesting.

Eachdeviceor circuitis expandedintoan arrayor reticleof devicesin the

" actual layout. For example,the i00microngatewidthFETdeviceis expanded

into a 4.87 by 4.87 mm arraycontaining198 FETs and 1 test pattern for

in-processtesting. EachFETdie is 300_m by300#m. The layoutfor the

_-- singlegateFETis shownin Figure 37. A secondexample is the two-sta°ge

amplifier.

The two-stageamplifierreticleoccupiesthe sameareaas the the100micron

FETreticle.The two-stageamplifierreticlecontainsonly twelvetwo-stage

amplifiersandone in-processtestpattern.The two-stageamplifiershownin

Figure38,has a 1.9_nx .65ramchipsize. Thesingleand dualgate FETs with

Capacitormatchingare combinedin a singlereticleso thereis a totalof

fiveseparatereticles.Two of the reticles,thei00micronFET and the 100

- micron FET with stub inputmatching,do not requirenitrideor airbridge

-- 35

processing.The remainingthreereticlesall requirenitrideand air bridge

processing. Since the processingwithout nitrideor air bridgesrequires

fewerstepsit makessenseto separatethesereticlesintotwo groups; i) the

100 micron FET group,and 2) the two-stageamplifiergroup. For the100

micronFETgroup all layersexcept the finalpad metal layer are done by

e-beam lithography. The two-stageamplifiergroup requiresfouroptical

levelsaftere-beamprocessing:I) thecircuitmetallevel,2) the dielectric

patterninglevel,3) the secondlevelmetaland 4) the airbridgelevel. The

opticalmasksfor theselevelswillbe madeon theCambridgee-beamsystem.

i-

3.1 i00 Micron FET

The first fabricationruns will includeonlythei00micronFETgroup. The

100microndeviceswill be testedto check the validityof the FET model

discussedin Section II-1.2.2. The initialrun will be fabricatedon ionr

implantedLEC substratematerial. Thematerialhas beenimplantedwith5 x

-- 1012ions/cm2of siliconat 120Kevand annealedfor 30 minutesat 850ocin an

arsenicoverpressure.The measuredsheet resistanceof the implantedand

annealedmaterialis 600 ohms per squarecomparedto a calculatedsheet

resistanceof 538ohmsper square. This indicatesthat the activationis

high, on the order of 90 percent. However,CV profiling (SeeFigureo39)

indicatesthatthepeakcarrierconcentrationis lower than the theoretical

valueand thereis somespreadingof the implantdistribution.

3.2 DualGateAmplifier

Thelayoutforthe dualgateFETamplifierhas beencompletedaccordingto the

designdiscussedin Section1.1.3. Fabricationof the dual gate amplifier

_ willbeginaftercompletionof thefirsti00micronFET runs.

4.0 RP/IFandIRASuhmoduleFabricationandEvaluation- TasksIVandV

TasksIV andV are scheduledto beginin the secondyearof theprogram.

Developmentof thelownoiseamplifierhasactuallystartedduringthe first

yearwith thedesignandinitialfabricationof theI00microngatewidthFET

includedin the gaincontrolmaskset (discussedin SectionII-1.2.2and

II-3.1).

5.0 SubmoduleIntegrationandReceiveModuleDevelopment- TasksVI andVII

Tasks VI and VII are scheduled to begin in the third and fourth year of the

program. The designs for both the integrated module and the monolithic module

was discussed in Section II-l.l.l.

6.0 ProductAssuranceandReporting- TasksIXandX

A product assurance program has been implemented in accordance with the

requirements of Section 3.4 of the RFP. Log books concerning device and

circuit fabrication and development have been utilized from the outset of the

program.

Reports have included an updated work plan, monthly technical progress

reports, as well as monthly and quarterly financial and management reports

(533M, 533Q, 533P) as required under the contract.

38

IlL LOGIC SIGNALS

tFOR DIGITAL CONTROLI

- " I I 01GITAL CONTROL iI - 18 d_ PHASE REFERENCE SIGNAL__'-AI 22 GHt

,r !. V ,,, rG,,,NCON,,oLV,,VLO." ,,..,,I LOW NOISE AMPLIFIER I I PHASE SHIF I I --

" I I I I I L ._6d13m I

'"++ 't>"_"_"_oI I I I ss 8.0GH! I,--. ,.J " 1-- .... .J L _j GH,

--" LO DIODE

5OR 6$TAGE FET AMP PS LOSS DUAL GATE AM__P MIXER IJFAMP

NF 4d81 4 4 4 6 _ _ 14 _ IO 5 6 4

GAIN ICiBJ 6 6 6 7 ; "4_ -I _ 12 24 -6 S

VOLYAGE IVl 3 3 3 3 3 4 3 3

CUqREN! ImAI 4 4 4 4 4 I S 26 8

_" SUfMODULE F _ _I.B f_.. 14Od6 .fo" I_-- f _ f_ _m 10dlB

NOISE FIGURE F_, m 10dB Gm

:_= 48d6MONOt I ! HIC Hff C| IV[ MODUt t

rO|AI I IC POW£R 250 mw IINCtUIIING g mW I-UH DI(;IIAL CONIHOLI

_" OVERALL NOISE FIGURE 4 9 dB IMAX GAINI _) 0 d_ IMIN GAINI

NFIIF CONVENSION GAIN 3_ tJtl Ifl_ll _l_ll ;)3 _ lldl|N GAINI

MINIMUM DE IEC | ABt E NIGNAL /0 lll_t_

OYNAMI(: RANGE 30 _IH IMAX (_AINI 43 (ll_ IMIN (;AIN,

Figure1.BlockDiagramofOverallMonolithicReceiver

LO WAVEGUIDE (WR-.42)"_ INPUT

IFIF OUTPUT OUTPUT

_ . (SMA) LO INPUT

TTLINPUT RF/IFCONNECTOR

,,...-.

IAS DISTR.

METAL.... DC BIAS CARRIER

GAIN PLATERF INPUT CONTROL

RF WAVEGUIDE (WR-28)INPUT LNA

PHASESHIFTER

RF TEST FIXTURE INTERCONNECTED RECEIVE MODULE

-- Figure2.InterconnectedReceiveModuleandRF TestFixture

39

' ON =ET OFF FET

Near Resonance

_ = C=r,Qc= (_r,C:,)-'_o = Center Band RadianFrequencyL - (_0_,)-'. = External Inductor

Switch Figureof Merit, (_;

ROFF Example:(_I10GH,= 738--__--[(oaCoFF)2rsRo.]-' --

Ro. (_l_., = 82

Figure 3. Simplified Equivalent Circuits for ON and OFF FETs

F_ = 4.7t_ 1

_o r, = 2.49 _'.... _°

C = .07pF| For300 Micron)- FET and ScaJed

"_ --_-R° f f 1RL: R° '_/ or'R"= 14H"_==59 _,_' _ forOtherGatewidths -_ _ _._ .O7pI-J J

_.......-.--,

mm ._---_ ----_ 30

"o_ 0.5 - 4-_-_ _ _''_ .... _ _ _ _ _ _ -25 U_o

O / _ --"- O.J 1.0 I / _ --20 :

.9 __--_-----_ "_•:: 1.5 - _ --15 m

= 2.0-- i

-- 10

r2. 5 I I I I I I I I 5150 300 450 600 750 900 1050 1200

FETGateWidth (Microns)

(_-.g/4 = 855 Microns for 50_ Line at 30 GHz)

Figure 4. Insertion Loss and Isolation versus Gate Width

4O

-- Figure 5. Chip Layout for 180 ° Bit

400 Micron FETs

Gate Pad

- IN [ ] OUT

r

0 005"

-- Figure 6. Layout of 180 ° Bit Using Four Series FET Switches

190 -

180 _ Calculate

I

170 -- l / / " "

_ / //__Tdeal curve for 180o bit160 /

/

150 -

,140 I I I I I I I I26 27 28 29 30 31 32 33 34

Frequency (GHz)

Figure 7. Computer Calculated Results for 180 ° Phase Bit Using Series Switches

1 ', I ,' , I ' ) ( / ( , I

...1I"

..... Ideal Characteristic _.._ "• CalculatedPoints ,.,,- "

...." -- 180 °

_} 160 .

a [40 135° -----

C !.20 ----_".£

---

-- 1.oo 90° --J'---

,-,--- .__._

60

450 __l.- .......

40q, "--

I I I I I I ' i'5 "_, ? 1 2R 29 "_J 31. _2 3_

Frequency (GHz)

f360 /

//

.//.

,/

315 ° .../_" 32o

O / / /300 --" /"

a,, //" I /

" " 2_'o / 270o. I"._o

_60 / _ j_

/I( _

• ' 240 _ _"

i5 225 ° _. f "te"

• 220 . _

200 - "

Frequency (GHz)

Figure 8. Calculated Differential Insertion Phase for 3-Bit Phase Shifter(180°, 90°, 45° Bits) UsingSeriesFET Switches

-- 4.3

0 AssumedValues R= = 99forSwitching Co.= .09pFFET Parameters r, = 4.5fl

2

I I I I I I I -25 26 27 28 29 30 31 32 33

Frequency (GHz)

Figure 9. Calculated Insertion Loss "Envelope" for Eight States of 3-Bit PhaseShifter

UNBIASED ,Ser,'t sGATE 2 CONTROL VOLTAGES FETS

CORRESPONDINGOVERALL RECEIVER

GAIN STATES (dB) RF/IF GAIN (riB)

q, 3+2-6= -1 17IN OUT (_ 3 + 5 - 6 = +2 20

(3) 3 + 5 - 2 = +6 24(4) 6+5-2= +9 27

-2dB ('_ 6 + 8 - 2 = +12 30GATE GATE _ ~15 -15 - 6 =FET FET - 36 OFF

GAIN STATES (G) (G2) WORSI CASE NOISE FIGURE (STATE (1))(dB) 3,_ 2,5,8

F2-1 L=-IASSOCIATED FMAX = F1 + + - 13.6dB

G1 GIG 2 ---NOISE FIGURE (F1) (F2)14,10,10

(dB) 10,9 BEST CASE NOISE FIGURE (STATE (_)

VOLTAGE(V) 4 4 FMIN = 10.1

MAX. CURRE'NT(mA) 8

Figure 10. Gain Control Design

44

509 52° 87.5 ° 47.3 ° 1 PF 1.5 nH

TF; o ;°°AllTRLshave_ = 90922 -ReferenceFrequency = 29 GHz

_. 21 AllFETs = 1O0/.EnGateWidth

_ _ 19,

18-

17 -

16-

- 15 I I I I I I26 27 28 29 30 31 32

Frequency(GHz)

Figure 11. Design for Monolithic 2-Stage Dual-Gate Amplifier

I _., 2.7mm ..._1

,-- I- {] -I

, ' lI LO REFAMP I

_" "1 I I , _.1AMP I I I viA"7

I I I t"_" L._. 2.1me

IF MIXER DIODESFILTER

I _1 SIGNAL INPUT./VIA

F -

RAT RACEMIXER

-- Figure 12. RF/IF Submodule with Rat Race Hybrid

45

ws

OHMICCONTACTLEAD

x,..SCHOTTKY CONTACTLEAD _

SCHOTTKYCONTACT _-

DIELECTRIC

OHMIC ""CONTACT,

o- n-GaA:

J ;aAsOHMIC ;.I. GaAs

DEPLETIONSCHOTTKY REGIONCONTACTTHROUGH

DIELECTRIC OF SELECTIVEIMPLANT _

SCHOTTKY LEAD ON TOFOF DIELECTRIC

Figure 13. Diode Structure for High Mixer Performance and Fabrication Simplicity . _

46

! _ k! T _ _ _ _ ! _ J 1 / _ l \

-- NoiseFigure SourceimpedanceZ,-- - Gain

Figure 14. Noise Figure and Gain Circlesfor First Stage of 22 GHz Amplifier

62.4 ° 51.6 ° 1PF • 73.1 ° 60.7 ° 1PF 51.2 °8zo __

7., AllTRUshaveZ,, = 909Reference Frequency = 22 GHz

28 AllFETs = 100#m Gate Widths

A 27

26 _ ,

c....-

25-

I I I I

20 21 22 23 24

Frequency(GHz)

Figure 15. Design for Monolithic 22 GHz Amplifier

--- Stage 2 ---- 3 4 --- 5 _ __L.

AllTRL'shave 7--0= 909Reference Frequency = 29 GHzAllBlockingCap's = 1PF

34 AllFETs 100#m Gate Width

_" 33 Chip Layout - 1.58 x 1.25 mm2

32 --

31

30

29

I I I I I I I25 26 27 28 29 30 31 32

Frequency(GHz)

Figure 16. Design for Monolithic Five-Stage Amplifier _ _

8

40.0 Dose 5xl 0'_Activation70°0

"- 200 /

.i- 10.0 /

/- d 5.0. , {,_

c /-_- 4.0•_ /i¢1

._ 2.0m

&.°;-/1.0 ///

J/

f

0.5 I I I0 -2 -4 -6 -8 -10

. Figure17. ChannelSheetResistanceversusGate-to-ChannelVoltage for Different Implant Energies

7

- - Une Resistance.2 £--mmn. SheetResistance 200 L)sGate Width400_

E Source--Drain_ o Spacing4/.{

6ue-

I 5

4500 600 700 800 900 1000

-- Figure 18. Source-DrainResistance versus Channel Sheet Resistance

49

a b 2.7 .01 11.3

o:: t,a2 _ _'--F'" N

• BUFFER _'_ .4 Uni ts

Gate length Lg = 0.25 microns gm = 16.9 e'J_mS _ fi _

Unit gate width w = 50 microns I = 2.5 ps pF

Channel thickness a = 0.15 microns 0.07 nH

Doping density N = 2.5 x 1017

Total qate width Z = 100 microns

Gate-source spacing Lsg = .75 microns

Gate metal thickness h = 0.5 microns _9.3dB @ 27GHzSpecific contact resistance rc = 10-6 ohm.cm2 MAG = (7.8dB @ 33GHz

aI = 0.22

a2 = 0.15

NI = 2.5 x 1017

N2 = 2.5 x 1017

Calculatednoise figure = 2.5 dB at 32 GHz

Figure 19. 100 x 0.25 Micron Low Noise FET Designa) Device parametersb) Equivalent Circuit

50

012 _I$Ost

0._II ,',. 5t

Conjugatematch '°8.6 dB gainat 29 GHz

8 dB7 dB6 dB

._ 5dB

NoiseFigureMinimumF = 2.25 dB .."Rn= 47.34 ohms£,:_t= .63 < 50.53

/Figure 20. Gain and Noise Circlesfor Low Noise FET Input Plane

- No Cdg orLs forNoiseCircles

012 0.15O_t

Conjugatematch °" °"8.6 dB gainat 29 GHz

8dB7 dB

.._".<: 6dB5dB

2.5 dB

NoiseFigureMinimumF = 2.06 dB

Rn = 33 ohmsropt= .58 < 64.43

;_,,/-t,,7-,_./ -7-4__iFigure 21. GainandNoise Figure Circlesfor Low Noise FET Input Plane

Including Cdg and Ls

! !

O.IZ C.15o J4

ConjugateMatch °" o.,. ....8.6 dBGain '0 LowNoiseat 29 GHz * ConjugateMatch

-t . 0 !I

R, = 5.4t'1 - 3.5F = 29 GHz "-

10.-

3.0

,,, £"o 9. --

0 2.5

8. m

2.0

7. --

I I I 1.52. 3. 4. 5. --

R, (_3)

Figure 23. Effect of Gate Resistance on 29 GHz Gain and Noise Figure

o Max.AvailableGain11.-

Rg= 2.7[2

F = 29 GHz o10.

O- 3.0

-rl

9. _ o.O3

2.5

8.

_ - 2.0

7. _

I I I I I I I I 1.52.5 3.0 4.0 5.0 6. 7. 8. 9. 10.

R, ([2)

Figure 24. Effect of Source Resistance on 29 GHz Gain and Noise Figure

54

\

State 1

State 2

27.5 (GHz) 30

Vertical: 450 IdivHorizontal: 500 MHzldiv

30 (GHz) 32.5

Figure 25. Insertion Phase for 1800 Phase Shiftet(TR061A)As Measured on the Network Analyzer

•• RT/duroidI Substrate

Part of~Fin-Line

Transition

Insertion Loss

Vertical: 5 dB/divHorizontal: 26.5 - 37 GHzReference: Center Line

(Test Fixture and Chip)

Figure 26. Test Fixture and Measured Insertion Loss for theTwo States of the 1800 Phase Shifter

J J J J J J J J 1 j

. . , . . . ,

/ IdealJ

f

J

200 / NoShuntCapacitance

190

°- _ lqO"o

O.1 pg ShuntCapacitance(4 plcs)- _. 170

160a) _ Calculated

_ Experiment

I I I I I I I I_ 26 27 28 29 30 31 32 33 34

Frequency (GHz)

Figure 27. CalculatedandMeasuredDifferentialPhase Shift- for 180°Phase Shifter (TR061A)

57

0100

Insertion Loss

Vertical: 5 dB/divReference: Center UneHorizontal: 500 MHz/div: 27.5 - 32.5 GHz

Differential Insertion Phase

Vertical: 45°/divHorizontal: 250 MHz/div; 27.5 - 30 GHz

Figure 28. Measured RF Results for SAG 1800 1-Bit Phase Shifter

) 1 ) } J 1 / ) f

I

0

Ron : 7.8_ Circuit _iodelFET Parameters

_- I - rs = 3.9_ (TR-O8-2ASAG)

2 _ ' C°ff = .07pF

A 3 • m_1mm"D •

.- _ 4 - State28.._ 5 . •

-6 Experiment*

- _ Calculated

m

*Corrected for 1.4 dB fixtureloss.

f

, I I I I I I I26 27 28 29 30 31 32 33

Frequency(GHz)

Figure 29. Comparison of Measuredand Calculated Insertion Lossfor SAG Phase Shifter

- 59

(a)

(b)

Figure 30. Photomicrographsof SAG Phase Shifter Circuitson a Processed Wafera) The four bit phaseshifter (45 °, 90°, 180°, 22°)b) Enlargedview of 90° bit

6O

f

6O

---- Ideal- _ 50

• 1.56°/GHz

_ 30-

-_ I I I I I I27 28 29 30 31 32 33

Frequency(GHz)

Figure 31. Calculated andMeasuredDifferential Phase Shift for 45° Phase Shifter

°__

Ideal100

3.13°/GHz

,. ](N 80 I"e-

_ .=_ ]_Q

zo [60 I I I I I I

27 28 29 30 31 32 33

Frequency(GHz)

- Figure 32. Calculatedand Measured Differential Phase Shift for 90° PhaseShifter

61

Ideal

200 -

J _t 6.26°/GHz

190

_) 180

._ 17o

i5 _

16O

150 I I ! I I _ I27 28 29 30 31 32 33

Frequency(GHz)

Figure 33. Calculated and Measured Differential Phase Shift for 180 ° Phase Shifter

62

Figure 34. 180° Phase Shifter Vertical -- 45°/div.Horizontal-- 27.5 ° 32.5 GHz, 500 MHz/div.

Figure 35. 45° Bit Insertion LossVertical = 5 dB/div.Horizontal = 27.5 - 32.5 GHzReference -- Center line

Figure 36. 45° Bit Return LossVertical = 10 dB/div.Horizontal -- 27.5 - 32.5 GHzReference -- Center line

63

SOUREE

DR AI N _

• !! iii;iiliiiii;i

SOUaCE x_ I _

Figure 37. CALMALayout for 100 Micron Gate Width Low Noise FET

,< 1.9 mm >

Figure 38. CALMALayout for First Two Stages of Gain Control Amplifier _.

64

4-.

3-

2 - Measured_ 850°C 30 min.E As

€-- ._o Si Implant

•,- 0_7 5xl 0_2--120KeV" lxl -r-O 8 -o Calculated--90%activationim '-2

L_L_

m

B

f

2 l I I I I0 0.5 .10 .15 .20 .25 .30

Depth_microns

Figure 39. Profile of Ion Implant

65

Table 1. NASA's Key PerformanceGoals

DesignParameter PerformanceGoal

RF Band 27.5-30GHz --IFCenterFrequency Between4-8GHzNoiseFigureatRoom Temperature <5 dBRF/IF Gain __30 dB at highest level of gain controlGain Control At least six levels; 30, 27, 24, 20, 17 dB

and Off.Phase Control 5 bits; each bit +3° at band centerModulePowerConsumption 250mW inallstatesexceptOFF. InOFF

state,25roW.PhaseandGainControl Operateondigitalinput.Mechanical Design Fully monolithic construction; compatible _

with 30 GHz spaceborne phased arrayapplications.

Unit Cost Less than $1000 (1980 dollars) in unit buysof 5000 or more

Table 2. Proposed Initial Low-NoiseFET Design

GATELENGTH L= 0,25MICRONS --

UNITGATEWIDTH w = 50MICRONS

CHANNELTHICKNESS A = 0,15MICRONS --

DOPINGDENSITY N = 2,5x 1017

TOTALGATEWIDTH Z = 100MICRONS --

GATE-SOURCESPACING LsG = 0,75 MICRONS

GATEMETALRESISTIVITY p = 4 x 10-60HM-CM _

SPECIFICCONTACTRESISTANCE Rc = 10-60HM-CM2

A1 : 0,22MICRONS

A2 : 0,15MICRONS

SEEFIGURE19 N1 = 2,5x 1017

N2 = 2,5 x 1017

CALCULATEDNOISEFIGURE= 2,3DBAT32GHz

66

r Table 3. Calculated Parametersfor FET Design

SParameters(29GHz)r

S,, = .75 /-- - 70°S,== 1.06/- 79.8 °S_ = .086 z_.79.7 °S= = .73/--- - 45°

NoiseParameters(29 GHz)F=_= 2.6 dBR, = 48 ohms

-- ]'o = .64/_ 43.9 °r, = .67/_ 51.1°G,= 5dB

GainParameters(29 GHz)K = 1.14G_= = 8.63 dBr. = .87 z..80°r,_ = .87 z..57°

67

Table 4a. S Parameters with No Cdg or Ls

POLAR S-PRRAI_ETER$ IN 50.0 OHM :SYSTEMFREQ. _ II ._21 ::_12. :'-'22 $2 t K

(MRGM_.RMGL) (MRGN<AtIGL) ( MAGM<:AI'IGL>(MRL;M<'RMGL) DB FACT.

:_1500.00 .95< -46 1.25< 116.0 .020< 120.2 .87< -2.8 1.95 -.0323000.00 .94< -49 1.23< I11.8 .022< 118.2 .87( -30 1.80 .0124500.00 .93< -52 1.21{ 1"07.7 .025< 116.3 .87< -:32 1.64 .05•:'600,).01) .93< -54 1.1:3<: 10:3.7 .02,":'< 114.3 .86( -2.4. 1.47 .10::'.50¢'.00 .9;'< -57 1.16< 99.? .0:30< 112.3 .:36-': -36 1.3,) .15:'--"31JO,).Oi) ....91( -60 1 14( 95.8 0:3_( 110.2. 86 !,. -38 1. I 1 .2.*'|:3051)|).00 .9,)( -63 I. If< 92.0 .035< 108.._ .85< -40 .'._ .25:3_.000.00 .90.( -65 1.1:i9< :38.3 .037< 1136.2 ::35:: -42 .73 . :31:'::_500. I)l'.l .8'_( -68 1.06<: _4.6 .040( I('4.2 .:_5<: -44 .5:._ .:37

POLAR COORDIr'IATE_ OF :._IMULTAMEOU:::COM_iUL;RTEMATCH

Table 4b. S Parameters with No Cdg, But with Ls

POLAR :_-PAF'Ar'IETER-._IM 50.0 OHM :_.'r':_TEMFF'Et_. _:11 :_21 :_.12 "=-22 :"::='1 K

(.I'IA|3;'t(AI'tGL> (MAL_N-:.':Ar4i3L) ( MA6N.:.;AHGL:, _MRGM<AMGL..', DB FAC:T.

:'-'l_l:li'.l. i_il:l . :3:_.( --45 1 • _4::_ i I I • 5 . 1"140{i 174.5 . :34:{ -26 1• :35 -. 06•:':3':!1)0. 00 .:37< -4:3 1.2.2.{ 1*:iT.4 .04," .'.: 174.0 . :34<." -27 1.70 -. 07::'4500.00 .86:. -50 1.20'::: 10"_.5 .055<. 173.2. .84.( -29 1.55 -.0;_•"-"601)0. OI) ._5.( -5:3 I. 1_( '_'_.6 • 06:3< 17_..:_ • 8:3::: -:31 1.40 -. U.c'•:'7500._)i) .83_: -56 I. 15< '.:'5.'_. 073< 171.3 .8:3< -3:3 I._.5 --.09:_9000.00 .821 -59 1.1:3< 92..2. .08:3<. 170.1 .83": -:34 1.0;3 -.10:':1:'500. O0 .:31( -61 1.11( 88.7 .0'.:'4 :: 16:3.7 .:33< -:36 ._2 -.1032000.00 • :3':i'( -64 1.09_. .'3:5.2. . 106,: 167..3 . :32"( -::::3 .75 -. 10:3:::51)0.00.79< -67 1.07{ :31.8 .I19{ 165._3 .'_32<:-4.') .57 -. 10

POLAR COOFeDII'IATE_::OF :'_"IMULTA/_EOU'_COM JUGATE MATCH

68

Table 5. S Parameters for Complete Model, Including Ls and Cdg

POLAR _-PARAMETER._ Ill 50.0 rIHM SY._TEMFREQ. _II _21 S12 $22 _21 K

(MIaGN<F_MGL) (MR_SN<RMGL) (MRGN<_MGL) (MR6H<FIMGL) DB FRCT.

21500.00 .:._2< -55 1.17< 99.9 .080< 68.9 .77< -35 1.39 .90_:3000.00 .80< -58 1.15< 95.6 .081< 70.0 .76< -37 1.22 .9624500.00 .79< -61 1.13< 91.4 .082< 71.7 .75< -39 1.05 1.0126000.00 .77< -64. 1.11< 87.4 .08:3< 73.9 .74< -41 .87 1.0627500.00 .76< -67 1.08< 83.5 .084< 76.5 .74< -43 .69 1.11_9000.00 .75< -70 1.06( 79.8 .086< 79.7 .73< -45 .51 1.1430500.00 .73< -73 1.0,$< 76.2 .088. 83.2 .72< -47 .33 1.1732000.00 .72: -76 1.02< 72.8 .091< 87.0 .72< -49 .15 1.1733500.00 .71< -79 1.00{ 69.4. .095< 90.9 .71< -51 -.04 1.16

POLF_R I:(](]RDIMFtTE_OF :_IMULTF_NEnU_ COMJUGFtTE MF_TCH

F :_OURCE REFL. COEFF. LO_D _EFL. ¢OEFF. GMR×MHZ MRGr'I.<RNL_LE MRGM..':RML_LE DB

•SUO.') 1.11a_rlIl'lL_:POTErtTIFtLLYUM'::TRBLECIRCUIT21500.0 .:-::6( 67 .82< 52 11.67

• 000.0 I,:AF;'tIr4L_: POTEMTIFtLLY ur'I:.'..TFIBLECIR,:UITr ,_30n0.0 .91<: 70 .89< 53 II.52

.-'4500.0 .96 _ 73 .97 54 10.69•%900.0 .91< 75 .90< 54 9.69

- _.750,).0 .88< 78 .87< 55 9.09:-"._,),:sO.0 .87< 80 .86 < 57 8.633,)500.0 .86:: :_:3 .86< 58 8.'_.732000.0 .86": :_6 .86<: 59 7.'.:'8_500.0 .:_6" :-38 .86< 61 7.76

FILE rtFtrtE. T_,:.:[MFO • ' r_'LIrtE'; • .LRrtL_E", 'r4Etd' OG, "_'_U[T"

-_ 69

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February 1981. --

5. Y. Ayasli, A. Platzker, J. Vorhaus, and L.D. Reynolds,Jr., "A

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r

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71

15. P.G. Borden, "Substrate Conduction in GaAs MESFETs", Electronics Letter,

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16. L.F. Eastmanand M.S. Shur, "SubstrateCurrentin GaAsMESFETs",IEEE --

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pp. 680-683. --_

19. P.W. Chye and C. Huang, "QuarterMicronLow NoiseGaAs FETs",IEEE

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72

=

24. H. Yamasakiand J.M. Schellenberg,"Designof Millimeter-WaveFETs",

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73Thereverseof this pageis blank.

FF-