L0 processor for NA62

Marian Krivda 1) , Cristina Lazzeroni 1) , Roman Lietava 1)2)

1) University of Birmingham, UK2) Comenius University, Bratislava, Slovakia

28/10/2009 1

Content

• Requirements• Block diagram• Board layout and front panel• Trigger message from each sub-detector• L0 processor implementation• T0 time definition• T0 timeout• Summary

28/10/2009 2

Requirements

• 8 triggering detectors• Trigger input signals are asynchronous messages

(send over gigabit Ethernet)• From each triggering detector - timestamp (BC/256)

+ 8-bits for type of trigger• Trigger data for TTC must be synchronous • Burst input• Warning ejection – WE, WWE inputs • BUSY/ERROR input from each LTU

28/10/2009 3

Block diagram

28/10/2009 4

L0 processor

LTU+

TTCex

LTU+

TTCex

LTU+

TTCex

LTU+

TTCex

40 MHz clock

source

. . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . TTCrx TTCrx TTCrx TTCrx

Trigger inputs

QPLL QPLL QPLL QPLL

FEE FEE FEE FEE

BUSY/ERROR

Triggers

Clock +Triggers

Possible solution for L0 processor

28/10/2009 5

6U VME cards – L0 processor, BUSY fan-in

…………….

Burst

clock 40 MHz

clock source

Fan-in unitBUSY FI

BUSY WE

16 x LVDS flat cables to LTUs

LTU1

LTU2

LTU3

LTU16

6U VME crate

28/10/2009

6

VM

E M

aste

r

1 2 3 4 5 6 7 8 9 10 11 12 13 15 16 1714 18 19 20 21

LT

U 1

LT

U 2

LT

U 3

LT

U 4

LT

U 5

LT

U 6

LT

U 7

LT

U 8

TT

Cex

1

TT

Cex

2

TT

Cex

3

TT

Cex

4

TT

Cex

5

TT

Cex

6

TT

Cex

7

TT

Cex

8

L0

proc

esso

r

BU

SY F

AN

-IN

Board layout (6U VME)

28/10/2009 7

FPGA

VME connectors

8 x Ethernetfrom triggeringdetectors

8 x BUSY

Burst, WE, WWE

16 x LVDS – flat cable to LTUs

RAM

Trigger message from triggering detector

FE send trigger message asynchronously (GigaBitEthernet) in following format:

• fine time: 8 bit• timestamp (40MHz): 32 bit• trigger type (L0): 8 bit

28/10/2009 8

L0 processor (LOP)

L0 processor receives FE trigger messages and:• according to timestamp identifies messages

from same interaction• not later then given time T0• evaluates programmable logical combinations

of trigger types• sends synchronously readout trigger strobe

and messages (40MHz) via TTC

28/10/2009 9

L0 processor implementation

• Data from triggering detectors are stored in memory position following the time stamp

• After T0 time (timeout for receiving trigger data) L0 processor will make decision and can rewrite this position in memory with new data if they are already available

• Zero suppression is maybe also possible

28/10/2009 10

T0 time

• When “start of burst” => T0 counter reset• Then it counts with 40 MHz clock

• T0 time/timeout manages that trigger data are sent to LTUs/TTC synchronously

28/10/2009 11

T0 timeout

• It is maximum time difference between arrivals of trigger messages from the same interaction to L0P.

• It is determined by:– FE (< 100 ns)– topology of detectors (max < 100m*4 ns/m=400ns)– Ethernet protocol (???)

28/10/2009 12

Summary– Completely new L0 processor board is probably

better solution then reuse some old card with new mezzanine cards. A cost for 6U VME board should be lower than in example TELL1 + new mezzanine cards

– We need 2 x 6U VME crates for TTC + L0 processor– We can start a test with Altera Stratix III Evaluation

board, where is Ethernet and memory

28/10/2009 13

Back-up

28/10/2009 14

TDAQ trigger design1.) TTC distributes a clock (BC)2.) Fine time: FEE runs BC, and also clock 40Mhz/2563.) Time stamp : # counts of BC from start of burst - BC stamp Readout time information: # of fine clocks from timestamp4.) Trigger input signals are asynchronous messages (send over gigabit Ethernet). They contain timestamp (BC) of event which produced trigger.5.) CTP: runs BC, receives messages, decode them and if condition fulfilled CTP sends readout trigger over TTC (triggers are send synch., trigger

message is sent asynch.)6.) FEE receives trigger and reads events corresponding to the all BC period

(25ns) or more. Events are then composed offline (or in daq) analyzing time information

(fine time and time stamp)

28/10/2009 15

Algorithms for generating trigger

28/10/2009 16

Algorithm: •save incoming triggers in memory position wrt to its time stamp • at time T0 take all triggers at same memory position (= time stamp) and evaluate them for trigger conditions• send readout triggers via TTC at fixed time wrt to interaction

Timeout T0 :It is maximum time difference between arrivals of trigger messages from the same interaction to L0P.It is determined by:- FE - topology of detectors - Ethernet protocol