lab 2: adding ip to a hardware design lab - materias fce · • add additional ip to a hardware...

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Lab 2: Adding IP to a Hardware

Design Lab

Targeting MicroBlaze™ on the Spartan™-3E Kit

Adding IP to a Hardware Design Lab: www.xilinx.com/university 2-3 MicroBlaze Processor [email protected]

Lab 2: Adding IP to a Hardware Design Lab

Introduction

This lab guides you through the process of adding additional IP to an existing processor system by using Xilinx Platform Studio (XPS). You will add GPIO peripheral from the IP Catalog tab to interface to the push buttons and DIP switches on the Spartan-3E Starter Kit. At the end of the lab, you will generate the bitstream and test the peripherals in hardware.

Objectives

After completing this lab, you will be able to:

• Add additional IP to a hardware design

• Update ucf file to support external ports of the added IP

• Setup some of the compiler settings

Procedure

The purpose of this lab exercise is to extend the hardware design (Figure 2-1) created in Lab 1according to the following procedure

1. Open the project 2. Add and connect GPIO peripherals in the system 3. Configure the GPIO peripherals 4. Make external GPIO connections 5. Analyze the MHS file 6. Add the software application and compile 7. Verify the design in hardware


Figure 2-1. Extend the System from the previous lab

For each procedure within a primary step, there are general instructions (indicated by the symbol). These general instructions only provide a broad outline for performing the procedure. Below these general instructions, you will find accompanying step-by-step directions and illustrated figures that provide more detail for performing the procedure. If you feel confident about completing a procedure, you can skip the step-by-step directions and move on to the next general instruction.

DDR MPMC

CNTLR


Open the Project Step 1

Create a lab2 folder and copy the contents of the lab1 folder into the lab2 folder, or copy the content of the labsolution\lab1 folder into the lab2 folder. Launch Xilinx Platform Studio (XPS) and open the project file.

� Create a lab2 folder in the c:\xup\embedded\labs directory and copy the contents from lab1 to lab2

� Open XPS by selecting Start → All Programs → Xilinx ISE Design Suite 12 → Platform

Studio → Xilinx Platform Studio

� Select Open a recent project, Click OK and browse to C:\xup\embedded\labs\lab2

� Click system.xmp to open the project

Add and Connect GPIO Peripherals to the System Step 2

Add two instances of an XPS GPIO Peripheral from the IP catalog to the processor system via the System Assembly View.

XPS provides two methods for adding peripherals to an existing project. You will use the first method, the System Assembly View panel, to add most of the additional IP and connect them. The second method is to manually edit MHS file.

� Select the IP Catalog tab in the left window and click on plus sign next to General Purpose

IO entry to view the available cores under it (Figure 2-2)

Figure 2-2. IP Catalog


� Double-click on the XPS General Purpose IO core twice to add two instances to the System Assembly View, each time clicking OK to accept the default configuration (you can make changes to configuration settings, but we will do it later)

� Change the instance names of the peripherals to dip and push, by clicking once in the name column, typing the new name for the peripheral followed by pressing Enter key

At this point, the System Assembly View should look like the following (Figure 2-3):

Figure 2-3. System Assembly View After Adding Peripherals

� Click once in Bus Connection column for the push and dip instances to connect them as slave devices to the PLB.

At this point, the Bus Connections tab should look like the following (Figure 2-4):


Figure 2-4. Bus Interfaces Tab showing Bus Connections to the Added Peripherals

� Select the Addresses filter

Note that there are few instances which are not assigned addresses

You can manually assign the base address and size of your peripherals or have XPS generate the addresses for you.

� Click Generate Addresses (located on the right most end of the tabs) to automatically generate the base and high addresses for the peripherals in the system. The base address and high addresses will change as shown in Figure 2-5.


Figure 2-5. Peripherals Memory Map

Configure the GPIO Peripherals Step 3

There are four push buttons and four DIP switches on the Spartan-3E starter kit. You will first configure the push and dip instances according to their sizes and direction, and then make external pin connections.

� Select the Ports filter in the toolbar of the System Assembly View

� Double-click on the push instance to access the configuration window

Notice that the peripheral can be configured for two channels, but, since we want to use only one channel without interrupt, leave the GPIO Supports Interrupts and Enable Channel 2 unchecked.

The settings for the Common parameters should be set according to Figure 2-6 below.

Figure 2-6. Configurable Common Parameters of GPIO Instance for Push Buttons

� Next click Channel 1, click on the GPIO Data Bus Width down arrow and set it to 4, you will use 4 push buttons on the Spartan-3E starter kit . Set Channel 1 is input Only to True (Figure 2-7):


Figure 2-7. Setting Configurable Parameters for Push Buttons

� Set the same parameters for the dip instance, as performed for the push buttons.

Make External GPIO Peripheral Connections Step 4

You will connect the push and dip instances to the push buttons and DIP switches on the Spartan-3E starter kit. In order to do this, you must establish the GPIO data ports as external FPGA pins and then assign them to the proper locations on the FPGA via the UCF file. The location constraints are provided for you in this section. Normally, one would consult the Spartan-3E starter kit user manual to find this information.

� In the Net field of the GPIO_IO_I port of the push instance, make the GPIO_IO_I port as external by selecting Make External. You should see a new external net connection (Figure 2-8).


Figure 2-8. GPIO_in Port Connection Added to push Instance

� Similarly, make the GPIO_IO_I port of dip as external in the net field of the GPIO_IO_I port of the dip instance.

The GPIO_IO_I ports of both dip and push are now connected externally on the FPGA (Figure 2-9).


Figure 2-9. Push and DIP Instances External Ports

� Click on the system.ucf file under the Project tab and add the following code to assign pins to push buttons (The constraints are provided in lab2.ucf file in c:\xup\embedded\sources directory. Copy it from there and paste it in your ucf file)

Figure 2-10. UCF file (pin assignments).

� Save the system.ucf and close it


Analyze the MHS file Step 5

Open the system.mhs file, study its contents, and answer the following questions.

� Double-click the system.mhs file to open it if it is not already open

Study the external ports sections and answer the following questions

1. Complete the following:

Number of external ports: Number of external ports that are output: Number of external ports that are input: Number of external ports that are bidirectional:

� Review the entire MHS file

2. List the instances to which the dcm_clk_s is connected:

________________________________________________________________

________________________________________________________________

List the instances connected to the mb_plb bus:

________________________________________________________________

________________________________________________________________

� Review the memory map in the Addresses tab of the System Assembly View

3. Draw the address map of the system, providing instance names

$0000_0000

$FFFF_FFFF

?

?

?


Add Software Application and Compile Step 6

Add an existing c program to implement the functionality of push button and LEDs. Compile the program.

� Click on Applications tab and under Sources, right-click on TestApp_Memory.c file in TestApp_Memory_microblaze_0 and select Remove.

� Right click on Sources and add lab2.c file from c:\xup\embedded\sources folder

� A snippet of the source code is shown in Figure 2-11

Figure 2-11. Snippet of source code.


� In the Application tab, double-click on compiler options to open the Compiler Options dialogue box.

� In the Environment tab, select the option Use Default Linker Script.

Figure 2-12. Setting the Default Linker Script

� In the Debug and Optimization tab, set the optimization to No Optimization.

This will ensure that the for loop (used for software delay) in the source code is not optimized away.


Figure 2-13. Setting the Optimization level

� Click on to compile the source code. Make sure that it compiles error free

Note: This will automatically run LibGen to generate the required libraries if it has not been done already.


Verify the Design in Hardware Step 7

Download the bitstream to the Spartan-3s500e device.

� Start a HyperTerminal session � Baud rate: 115200 � Data bits: 8 � Parity: none � Stop bits: 1 � Flow control: none

� Connect and power up the Spartan-3E starter kit.

� Select Device Configuration �� Update Bitstream

This may take a few minutes to synthesize, implement, and generate the bitstream.

� Download the bitstream by selecting Device Configuration �� Download Bitstream

Note: Once the bitstream is downloaded, you should see the DONE LED ON and a message displayed in HyperTerminal as shown in Figure 2-14

Figure 2-14. Screen Shot after the BitStream Downloading

� After pressing the buttons and toggling the switches, and you should see the corresponding values being displayed on the HyperTerminal (Figure 2-15)

Figure 2-15. Push button and DIP switch status displayed on hyperterminal

� Disconnect and close the HyperTerminal window, and also close XPS


Conclusion

GPIO peripherals were added from the IP catalog and connected to a MicroBlaze system that was created in the first lab. The peripherals were configured and external FPGA connections were established. Pin location constraints were made in the UCF file to connect the peripherals to push buttons and DIP switches on the Spartan-3E starter kit.

In future labs in this course, you will learn how to add user cores, add software to the system, debug the software, and verify the functionality of the completed design by using a Spartan-3E Starter Kit.


Answers

1. Complete the following:

Number of external ports: 20 Number of external ports that are output: 12 Number of external ports that are input: 5 Number of external ports that are bidirectional: 3

2. List the instances to which the dcm_clk_s is connected:

clock_generator_0

List the instances connected to the mb_plb bus:

microblaze_0, DDR_SDRAM, mdm_0, LEDs_8Bit, push, dip and RS232_DCE

3. Draw the address map of the system, providing instance names. You can sort the peripheral addresses by base address from the Addresses tab of the Add/Edit Cores (dialog) box.

0x00000000–0x00001fff dlmb, llmb

unused

0x81400000– 0x8140ffff push

0x81420000– 0x8142ffff dip

0x81440000– 0x8144ffff LEDs_8Bit

0x84000000– 0x8400ffff RS232_DCE

0x84400000– 0x8440ffff mdm_0

0x8C000000– 0x8fffffff DDR_SDRAM

A


Completed MHS File

# ############################################################################## # Created by Base System Builder Wizard for Xilinx EDK 12.2 Build EDK_MS2.63c # Tue Jul 20 10:08:16 2010 # Target Board: Xilinx Spartan-3E Starter Board Rev D # Family: spartan3e # Device: XC3S500e # Package: FG320 # Speed Grade: -4 # Processor number: 1 # Processor 1: microblaze_0 # System clock frequency: 50.0 # Debug Interface: On-Chip HW Debug Module # ############################################################################## PARAMETER VERSION = 2.1.0 PORT fpga_0_RS232_DCE_RX_pin = fpga_0_RS232_DCE_RX_pin, DIR = I PORT fpga_0_RS232_DCE_TX_pin = fpga_0_RS232_DCE_TX_pin, DIR = O PORT fpga_0_LEDs_8Bit_GPIO_IO_O_pin = fpga_0_LEDs_8Bit_GPIO_IO_O_pin, DIR = O, VEC = [0:7] PORT fpga_0_DDR_SDRAM_DDR_Clk_pin = fpga_0_DDR_SDRAM_DDR_Clk_pin, DIR = O PORT fpga_0_DDR_SDRAM_DDR_Clk_n_pin = fpga_0_DDR_SDRAM_DDR_Clk_n_pin, DIR = O PORT fpga_0_DDR_SDRAM_DDR_CE_pin = fpga_0_DDR_SDRAM_DDR_CE_pin, DIR = O PORT fpga_0_DDR_SDRAM_DDR_CS_n_pin = fpga_0_DDR_SDRAM_DDR_CS_n_pin, DIR = O PORT fpga_0_DDR_SDRAM_DDR_RAS_n_pin = fpga_0_DDR_SDRAM_DDR_RAS_n_pin, DIR = O PORT fpga_0_DDR_SDRAM_DDR_CAS_n_pin = fpga_0_DDR_SDRAM_DDR_CAS_n_pin, DIR = O PORT fpga_0_DDR_SDRAM_DDR_WE_n_pin = fpga_0_DDR_SDRAM_DDR_WE_n_pin, DIR = O PORT fpga_0_DDR_SDRAM_DDR_BankAddr_pin = fpga_0_DDR_SDRAM_DDR_BankAddr_pin, DIR = O, VEC = [1:0] PORT fpga_0_DDR_SDRAM_DDR_Addr_pin = fpga_0_DDR_SDRAM_DDR_Addr_pin, DIR = O, VEC = [12:0] PORT fpga_0_DDR_SDRAM_DDR_DQ_pin = fpga_0_DDR_SDRAM_DDR_DQ_pin, DIR = IO, VEC = [15:0] PORT fpga_0_DDR_SDRAM_DDR_DM_pin = fpga_0_DDR_SDRAM_DDR_DM_pin, DIR = O, VEC = [1:0] PORT fpga_0_DDR_SDRAM_DDR_DQS_pin = fpga_0_DDR_SDRAM_DDR_DQS_pin, DIR = IO, VEC = [1:0] PORT fpga_0_DDR_SDRAM_ddr_dqs_div_io_pin = fpga_0_DDR_SDRAM_ddr_dqs_div_io_pin, DIR = IO PORT fpga_0_clk_1_sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000 PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1 PORT push_GPIO_IO_I_pin = push_GPIO_IO_I, DIR = I, VEC = [0:3] PORT dip_GPIO_IO_I_pin = dip_GPIO_IO_I, DIR = I, VEC = [0:3] BEGIN microblaze PARAMETER INSTANCE = microblaze_0 PARAMETER C_AREA_OPTIMIZED = 1 PARAMETER C_DEBUG_ENABLED = 1 PARAMETER HW_VER = 7.30.b BUS_INTERFACE DLMB = dlmb


BUS_INTERFACE ILMB = ilmb BUS_INTERFACE DPLB = mb_plb BUS_INTERFACE IPLB = mb_plb BUS_INTERFACE DEBUG = microblaze_0_mdm_bus PORT MB_RESET = mb_reset END BEGIN plb_v46 PARAMETER INSTANCE = mb_plb PARAMETER HW_VER = 1.04.a PORT PLB_Clk = clk_50_0000MHz PORT SYS_Rst = sys_bus_reset END BEGIN lmb_v10 PARAMETER INSTANCE = ilmb PARAMETER HW_VER = 1.00.a PORT LMB_Clk = clk_50_0000MHz PORT SYS_Rst = sys_bus_reset END BEGIN lmb_v10 PARAMETER INSTANCE = dlmb PARAMETER HW_VER = 1.00.a PORT LMB_Clk = clk_50_0000MHz PORT SYS_Rst = sys_bus_reset END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = dlmb_cntlr PARAMETER HW_VER = 2.10.b PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00001fff BUS_INTERFACE SLMB = dlmb BUS_INTERFACE BRAM_PORT = dlmb_port END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = ilmb_cntlr PARAMETER HW_VER = 2.10.b PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00001fff BUS_INTERFACE SLMB = ilmb BUS_INTERFACE BRAM_PORT = ilmb_port END BEGIN bram_block PARAMETER INSTANCE = lmb_bram PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = ilmb_port BUS_INTERFACE PORTB = dlmb_port END BEGIN xps_uartlite PARAMETER INSTANCE = RS232_DCE PARAMETER C_BAUDRATE = 115200


PARAMETER C_DATA_BITS = 8 PARAMETER C_USE_PARITY = 0 PARAMETER C_ODD_PARITY = 0 PARAMETER HW_VER = 1.01.a PARAMETER C_BASEADDR = 0x84000000 PARAMETER C_HIGHADDR = 0x8400ffff BUS_INTERFACE SPLB = mb_plb PORT RX = fpga_0_RS232_DCE_RX_pin PORT TX = fpga_0_RS232_DCE_TX_pin END BEGIN xps_gpio PARAMETER INSTANCE = LEDs_8Bit PARAMETER C_ALL_INPUTS = 0 PARAMETER C_GPIO_WIDTH = 8 PARAMETER C_INTERRUPT_PRESENT = 0 PARAMETER C_IS_DUAL = 0 PARAMETER HW_VER = 2.00.a PARAMETER C_BASEADDR = 0x81440000 PARAMETER C_HIGHADDR = 0x8144ffff BUS_INTERFACE SPLB = mb_plb PORT GPIO_IO_O = fpga_0_LEDs_8Bit_GPIO_IO_O_pin END BEGIN mpmc PARAMETER INSTANCE = DDR_SDRAM PARAMETER C_NUM_PORTS = 1 PARAMETER C_SPECIAL_BOARD = S3E_STKIT PARAMETER C_MEM_TYPE = DDR PARAMETER C_MEM_PARTNO = MT46V32M16-6 PARAMETER C_MEM_DATA_WIDTH = 16 PARAMETER C_PIM0_BASETYPE = 2 PARAMETER HW_VER = 6.01.a PARAMETER C_MPMC_BASEADDR = 0x8c000000 PARAMETER C_MPMC_HIGHADDR = 0x8fffffff BUS_INTERFACE SPLB0 = mb_plb PORT MPMC_Clk0 = clk_100_0000MHzDCM0 PORT MPMC_Clk90 = clk_100_0000MHz90DCM0 PORT MPMC_Rst = sys_periph_reset PORT DDR_Clk = fpga_0_DDR_SDRAM_DDR_Clk_pin PORT DDR_Clk_n = fpga_0_DDR_SDRAM_DDR_Clk_n_pin PORT DDR_CE = fpga_0_DDR_SDRAM_DDR_CE_pin PORT DDR_CS_n = fpga_0_DDR_SDRAM_DDR_CS_n_pin PORT DDR_RAS_n = fpga_0_DDR_SDRAM_DDR_RAS_n_pin PORT DDR_CAS_n = fpga_0_DDR_SDRAM_DDR_CAS_n_pin PORT DDR_WE_n = fpga_0_DDR_SDRAM_DDR_WE_n_pin PORT DDR_BankAddr = fpga_0_DDR_SDRAM_DDR_BankAddr_pin PORT DDR_Addr = fpga_0_DDR_SDRAM_DDR_Addr_pin PORT DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ_pin PORT DDR_DM = fpga_0_DDR_SDRAM_DDR_DM_pin PORT DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS_pin PORT DDR_DQS_Div_O = fpga_0_DDR_SDRAM_ddr_dqs_div_io_pin PORT DDR_DQS_Div_I = fpga_0_DDR_SDRAM_ddr_dqs_div_io_pin END BEGIN clock_generator


PARAMETER INSTANCE = clock_generator_0 PARAMETER C_CLKIN_FREQ = 50000000 PARAMETER C_CLKOUT0_FREQ = 100000000 PARAMETER C_CLKOUT0_PHASE = 90 PARAMETER C_CLKOUT0_GROUP = DCM0 PARAMETER C_CLKOUT0_BUF = TRUE PARAMETER C_CLKOUT1_FREQ = 100000000 PARAMETER C_CLKOUT1_PHASE = 0 PARAMETER C_CLKOUT1_GROUP = DCM0 PARAMETER C_CLKOUT1_BUF = TRUE PARAMETER C_CLKOUT2_FREQ = 50000000 PARAMETER C_CLKOUT2_PHASE = 0 PARAMETER C_CLKOUT2_GROUP = NONE PARAMETER C_CLKOUT2_BUF = TRUE PARAMETER C_EXT_RESET_HIGH = 1 PARAMETER HW_VER = 4.00.a PORT CLKIN = dcm_clk_s PORT CLKOUT0 = clk_100_0000MHz90DCM0 PORT CLKOUT1 = clk_100_0000MHzDCM0 PORT CLKOUT2 = clk_50_0000MHz PORT RST = sys_rst_s PORT LOCKED = Dcm_all_locked END BEGIN mdm PARAMETER INSTANCE = mdm_0 PARAMETER C_MB_DBG_PORTS = 1 PARAMETER C_USE_UART = 1 PARAMETER C_UART_WIDTH = 8 PARAMETER HW_VER = 1.00.g PARAMETER C_BASEADDR = 0x84400000 PARAMETER C_HIGHADDR = 0x8440ffff BUS_INTERFACE SPLB = mb_plb BUS_INTERFACE MBDEBUG_0 = microblaze_0_mdm_bus PORT Debug_SYS_Rst = Debug_SYS_Rst END BEGIN proc_sys_reset PARAMETER INSTANCE = proc_sys_reset_0 PARAMETER C_EXT_RESET_HIGH = 1 PARAMETER HW_VER = 2.00.a PORT Slowest_sync_clk = clk_50_0000MHz PORT Ext_Reset_In = sys_rst_s PORT MB_Debug_Sys_Rst = Debug_SYS_Rst PORT Dcm_locked = Dcm_all_locked PORT MB_Reset = mb_reset PORT Bus_Struct_Reset = sys_bus_reset PORT Peripheral_Reset = sys_periph_reset END BEGIN xps_gpio PARAMETER INSTANCE = dip PARAMETER HW_VER = 2.00.a PARAMETER C_BASEADDR = 0x81420000 PARAMETER C_HIGHADDR = 0x8142ffff PARAMETER C_GPIO_WIDTH = 4


PARAMETER C_ALL_INPUTS = 1 BUS_INTERFACE SPLB = mb_plb PORT GPIO_IO_I = dip_GPIO_IO_I END BEGIN xps_gpio PARAMETER INSTANCE = push PARAMETER HW_VER = 2.00.a PARAMETER C_BASEADDR = 0x81400000 PARAMETER C_HIGHADDR = 0x8140ffff PARAMETER C_GPIO_WIDTH = 4 PARAMETER C_ALL_INPUTS = 1 BUS_INTERFACE SPLB = mb_plb PORT GPIO_IO_I = push_GPIO_IO_I END

lab 2: adding ip to a hardware design lab - materias fce · • add additional ip to a hardware...

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