Pre-Lab 8: Introduction to Sequential LogicKatherine MoralesECEN 248 506TA: Kartic BhargavDate: March 31, 2015

Objective:In this lab, I will become more familiar with the FPGA circuits as well as Verilog. I will learn more about latches and flip-flops and how to code them using Verilog and simulate them using ISE. I will also familiarize myself with how to show delays using the ISE.

Design:On separate engineering paper.