lab1 layout training -...

ACCESS IC LAB

Graduate Institute of Electronics Engineering, NTU

Lab1 Layout trainingLab1 Layout training

Speaker AeagAdvisor: Professor Wu.

2003/03/21(Fri.)

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

pp. 22002/9/17

OutlineOutlineIntroduction & Environment settingSchematic EntryStarting cadenceLayout editor training


pp. 32002/9/17

Full_custom design flowFull_custom design flow


pp. 42002/9/17

Object in Lab 1Object in Lab 1Learning how to use layout editorFit the design rule check with your layout circuit and schematic circuit


pp. 52002/9/17

Environment settingEnvironment settingCreate cds.lib in your working directory(LAB1)Add the description INCLUDE /usr/cadence/ic446/share/cdssetup/cds.lib

into cds.libCopy these files into working directory035.tf display.drf divaDRC.ruldivaEXT.rul divaLVS.rul 1p4m(dir.)


pp. 62002/9/17

Environment setting cont.Environment setting cont.cds.lib:a file containing the library path or definition035.tf:technology filedisplay.drf:a file containing layer display informationdivaDRC.rul , divaERC.rul , divaEXT.rul :all design rules for DIVA tools


pp. 72002/9/17

CIWCIW(command interpreter window)(command interpreter window)

下command處 Mouse提示功能處

Skill format, display user command及system response


pp. 82002/9/17

Library managerLibrary manager

顯示的library為cds.liib中所定義,這些library可被expand成cell與cellview,並且可被read或edit

Tool=> Library manager


pp. 92002/9/17

Ex:add 1p4m libraryEx:add 1p4m library

Tool=> Library Path Editor


pp. 102002/9/17

SchematicSchematic


pp. 112002/9/17

Create libraryCreate libraryFirst you need to create a new library, and it will have three option<>Compile a new techfile ,means you can get a techfile from the file,ex:035.tf<>Attach to an existing techfile ,means your techfile may be in the other library directory<>Don’t need a techfile


pp. 122002/9/17

Create library cont.Create library cont.File => New =>Library

Your library name

The location of Tech. file


pp. 132002/9/17

Create library cont.Create library cont.

After creating a new library directory,you still need to copy some files below in the library directory:divaDRC.rul divaLVS.ruldivaEXT.rul divaERC.ruldisplay.drf


pp. 142002/9/17

Construct schematic viewConstruct schematic view

Choose

File->New->Cellview


pp. 152002/9/17

Add componentAdd component利用軟體中預設的library (analogLib與basic)已定義好的元件完成schematic viewChoose: Add->Component就會看到下頁的對話window,再選取Browse中之analogLib之pmos4,即可同理,Add->Pin,but must define input terminal and output terminal pin.最後用Add->wire做接線的動作即可


pp. 162002/9/17

Add componentAdd component


pp. 172002/9/17


pp. 182002/9/17

Add component cont.Add component cont.當接線及電路元件都兜完後,Choose: Design->Check and Save觀察CIW上的messageCheck過後會將schematic電路提取成netlist


pp. 192002/9/17

Create symbol viewCreate symbol viewDesign->Create->From Cellview建立相關的symbol view


pp. 202002/9/17

Symbol generation formSymbol generation form


pp. 212002/9/17

Symbol view editorSymbol view editor


pp. 222002/9/17

Cross view checkCross view checkChoose:Cross->Cross View Check在選save,即完成了inverter的schematic view與symbol view


pp. 232002/9/17

CadenceCadence


pp. 242002/9/17

Create library cont.Create library cont. (skip)(skip)File => New =>Library

Your library name

The location of Tech. file


pp. 252002/9/17

Create library cont.Create library cont. (skip)(skip)

After creating a new library directory,you still need to copy some files below in the library directory:divaDRC.rul divaLVS.ruldivaEXT.rul divaERC.ruldisplay.drf


pp. 262002/9/17

Create a New CellCreate a New CellFile=> New => Cell

Your library name

Specify your cell name

Choose Virtuso for layout view,

Schematic for schematic view


pp. 272002/9/17

Start to use Layout EditorStart to use Layout EditorFile =>

Open …

Choose Library

Choose Layout view

Choose Cell


pp. 282002/9/17

Layout editorLayout editor


pp. 292002/9/17

Physical Layout TechniquesPhysical Layout TechniquesOnce a circuit design is complete, it becomes necessary to provide an area-efficient layout of the circuit to generate the masks necessary for fabrication.We must define the following: ”NWELL”, “PWELL”, “THIN”, “GPOLY”, “CONT”, “METAL1”, “METAL2”, “METAL3”, “VIA1”, “VIA2”, “NPIMP”, “PPIMP” in the layout database for 0.35μm TSMC process of CIC.


pp. 302002/9/17

佈局層次佈局層次


pp. 312002/9/17

Physical Layout Techniques cont.Physical Layout Techniques cont.


pp. 322002/9/17

Physical Layout Techniques cont.Physical Layout Techniques cont.The n+ diffusion can be defined by “NPIMP” and “THIN”. With poly across, a NMOS is formed.The p+ diffusion can be defined by “PPIMP” and “THIN”. With poly across, a PMOS is formed. Also PMOS is formed on “NWELL”.Conductor: Poly and metals. They are in different layer and disconnected unless through “CONT” or “VIA”. “CONT” is for poly and metal1. “VIA” is used between 2 metals.There is also “THIN” at “vdd!” And “gnd!”, “CONT” is required to connect “THIN” and “Metal1”. Once the “THIN” exist, there is PPIMP or NPIMP.After finish drawing, do not forget to place pins on inputs and outputs.


pp. 332002/9/17

Layout editor Layout editor bindkeybindkey


pp. 342002/9/17

Useful HotkeysUseful Hotkeys

Some useful hotkeys:r: draw rectangular blockz/Z: room in and room outk/K: ruler on/offs:stretchc: copym: moveu: undoDel: deleteq:queryp: create path


pp. 352002/9/17

LSWLSW


pp. 362002/9/17

Option => DisplayOption => Display

存取目前設定狀況

設定X or Y軸之移動的最小間距

顯示所能顯示的層次


pp. 372002/9/17

Options => EditorOptions => Editor

Set gravity on時所能影響之範圍在為幾個unit之內

Set gravity on 之control type

設定游標靠近object時即被吸引到object的邊緣


pp. 382002/9/17

Create pinCreate pin

Create->Pin->Shape pin


pp. 392002/9/17

InverterInverter’’s Layouts Layout


pp. 402002/9/17

OnOn--line DRC(Diva)line DRC(Diva)Design rule check:

Choose Verify->DRC

Error會出現於CIW的視窗中

預設的command file 是DRC

指定tech. file

相同的Net name視為相接


pp. 412002/9/17

OnOn--line DRC(Diva) cont.line DRC(Diva) cont.當DRC on-line check完後,會有一些remark並且閃爍在出錯的地方.

Verify -> Makers -> Explain ,點選於閃爍處已獲得違反rule的資訊.

Verify -> Makers -> Find ,點選Apply依序解釋閃爍處所違反的rule.

不斷反覆Check直到沒有違反Design rule為止.


pp. 422002/9/17

Learning DIVALearning DIVA--ExtractExtractChoose

Verify -> Extract

DIVA依據divaEXT.rul檔做extract,將所佈局的MOS等元件與尺寸extract成netlist,其訊息show於CIW中,必須由CIW中確定無error與warning(若有error或warning可藉由Verify->Makers->Find..改正),Library Manager中可看到增加了etracted view.


pp. 432002/9/17

CDL_OUTCDL_OUT--11File->Export->CDL

This step translates Extracted to Netlist file


pp. 442002/9/17

CDL_OUTCDL_OUT--22

Extracted view

Output file name

Use library to choose


pp. 452002/9/17


pp. 462002/9/17

HW 1HW 11-bit Full AdderRequirement:Diva-DRC check must passprint out extracted Netlist file(CDL-out)print out 1-bit FA layout diagram


pp. 472002/9/17


pp. 482002/9/17

Good luck!

Thank you!

lab1 layout training -...

Documents