laboratory 2: large signal amplifier author: ryan child...

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ECE 466 Electronic Design Laboratory Winter, 2011 Laboratory 2: Large Signal Amplifier

Laboratory 2: Large Signal Amplifier

Author: Ryan Child

Teammate: Shea Watson

Project Start Date: 1/24/2011

Report Submission Date: 2/14/2011

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OBJECTIVE: To investigate the design and operation of a large-signal bipolar transistor power amplifier for operation in the audio frequency range. PRINCIPLES OF OPERATION: The full amplifier consists of three stages: a differential amplifier, a signal splitter, and a push-pull, or complementary output stage. The push-pull amplifier consists of two transistors that alternately “pull up” and “push down” the voltage across the load. There is a zero-degree phase difference and very little voltage and current gain. It was tested with the circuit in Figure 1. The two diodes exist to eliminate crossover distortion — a problem that arises when the input is near 0V and both transistors, Q5 and Q6, are turned off. If the input were connected directly to the bases of these two transistors, it would take an input voltage of ±0.7V to turn either transistor on. As a result, there would be a short flat segment at 0V where the input “crosses over” from a positive to a negative voltage or vice-versa. With the diodes in place, both transistors are on at Vin=0V, so the output will be smooth and continuous.

Figure 1: Push-pull stage

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The signal splitter circuit in Figure 2 takes a single-sided input near one of the supply rails and transfers this into a large voltage swing centered around 0V. Instead of using diodes, an additional BJT is used along with one fixed resistor and one potentiometer. The potentiometer can be used to vary the voltage drop across the two resistors, which controls the amount of crossover distortion at the output. The single-ended input is split into a full swing positive-to-negative signal as follows: When the input voltage rises, it begins to cut off Q10 because the voltage at the emitter is fixed due to the constant current provided by Q14. As Q10 turns off, its VCE increases and pushes down the base of Q5, turning it off as well. Q6 remains on, pulling the load down towards the negative supply rail. When the input voltage falls, the opposite happens and the load is pulled up towards the positive supply rail.

Figure 2: Signal splitter circuit connected to complementary output stage

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The differential amplifier in Figure 3 works as its name suggests; it amplifies the difference between two signals, rather than the signals themselves. One of its most useful characteristics is its very high open loop voltage gain, which is utilized in this circuit. Differential amplifiers have both inverting and non-inverting inputs, and they work by “steering” the current between the two transistors. The total amount of current in both collectors is fixed by the current mirror of Q8. Since the emitters are tied to a single node, a voltage increase at the base of one transistor will increase the emitter of the other transistor while its voltage remains fixed, thus reverse-biasing that transistor’s emitter-base junction and cutting it off. For example, if the base of Q3 rises to 1V, its emitter will rise to VB – 0.7 = 0.3V, while the base of Q2 remains at 0V. The majority of the current mirror current then is flowing through Q3, which pushes the output voltage down. Since a rise in the input voltage causes a decrease in output voltage, this input is called the inverting input, and the other input, at the base of Q2, is called the non-inverting input. The non-inverting input can optionally be adjusted by replacing the node connecting R23, R4, and R7 with a potentiometer. Connecting all three stages together results in a power amplifier whose frequency characteristics are suitable for audio applications; that is, the bandwidth covers most of the audible frequency spectrum. As previously mentioned, the differential amplifier has a very high open loop gain, which will result in clipping at the output even for very small signals. The gain can be controlled while increasing the bandwidth by feeding back a portion of the output to the non-inverting input of the differential stage. Since the output is in phase with the input, this is negative feedback that decreases the difference between the two inputs to the differential amplifier, which reduces the output of the differential stage.

Figure 3: Differential amplifier circuit

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ANALYSIS: Differential amplifier gain: The differential amplifier can be simplified as shown in Figure 4. The adjustable current mirror set by Q8 (See Figure 3) is replaced by a constant current source. The voltage divider at the base of Q2 is replaced by ground and the resistor at the base of Q3 is removed for simplicity.

Figure 4: Simplified circuit for finding differential amplifier gain

The equations for the emitter currents of Q3 and Q2 are:

𝑖!! =𝐼!𝛼 𝑒

!!!!!!!!

𝑖!! =𝐼!𝛼 𝑒

!!!!!!!!

Combining these two equations, we get:

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𝑖!!𝑖!!

= 𝑒!!!!!!!

!!

The current of the current mirror, I, is the sum of the two emitter currents:

𝐼 = 𝑖!! + 𝑖!!

= 𝑖!! +𝑖!!

𝑒!!!!!!!

!!

= 𝑖!! 1+ 𝑒!!!!!!!

!! Solving this equation for iE1 and letting vB2=0,

𝑖!! =𝐼

1+ 𝑒!!!!!!

From this equation it is apparent that the transconductance is a non-linear function of vB1, so we approximate the transconductance by evaluating this equation at the peak voltage of our small signal input at vB1=41.9mV:

𝑔! ≈𝑖!! 𝑣!! = 𝑣!!"#

𝑣!!"#

=𝐼

𝑣!!"# 1+ 𝑒!!!"#!!

=965×10!!

0.0419 1+ 𝑒!.!"#$!.!"#$

= 834μ𝐴𝑉

Multiplying this by the maximum input voltage at vB1,

𝑖!! ≈ 𝑔!𝑣!!"# = 834×10!! 41.9×10!! = 805μ𝐴

Noting that this current is approximately equal to the current flowing through R3 (iE3), and that the output voltage is approximately 0.7 volts lower than the emitter of Q4, we can get the output voltage for the maximum input voltage:

𝑣!!"# = 24− 𝑖!!𝑅! − 0.7 = 24− . 805 33 − 0.7 = −3.27𝑉

To get the amplitude of the signal at the output, we need to compare this minimum voltage with the output voltage for vB1=0. At this voltage, the currents iE1 = iE2 = I / 2 = 482.50µA. Therefore,

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𝑣! 𝑣! = 0 = 24− 𝑖!!𝑅! − 0.7 = 24− 0.4825 33 − 0.7 = 7.38𝑉

So, the voltage gain of the differential amplifier is (7.38 – (-3.27)) / 0.0419 = 254 V/V. DESIGN AND SIMULATION: Tables of measured component values: Component Calculated Measured C1 .47 uF .471 uF R2 10kΩ 10kΩ R10 (1kΩ potentiometer) 543 Ω 543 Ω R3 33 kΩ 32.5 kΩ R1 3.9 kΩ 3.83 kΩ R9 100 Ω 100 Ω R23 4.7 kΩ 4.7 kΩ R4 10 kΩ 10 kΩ R7 10 kΩ 10 kΩ R19 (10k pot + 5kΩ) 12 kΩ 14.62 kΩ R18 2 kΩ 2 kΩ R14 100 Ω 100 Ω R13 (100 Ω pot) 100Ω 100 Ω R16 54 Ω 47 Ω R15 54 Ω 47 Ω R8 .47 Ω .47 Ω R11 .47 Ω .47 Ω R12 16 Ω 16.1 Ω R_fdbk 2.2 MΩ 2.2 MΩ βQ4 N/A 136 βQ7 N/A 80 βQ14 N/A 120 βQ6 N/A 200 βQ5 N/A 195 βQ10 N/A 196 βQ9 N/A 204 βQ3 N/A 77.3 βQ2 N/A 128 βQ1 N/A 152 βQ8 N/A 101

Table 1: Measured component values

Circuit component calculations: Resistors R8 and R11 are typically used in push-pull amplifiers to reduce the spread of internal emitter resistances. They are typically 0.3 to 0.5Ω, so we chose 0.47Ω.

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The purpose of R13 and R14 is to provide two adjustable diode drops that eliminate crossover distortion at the output. Choosing 100Ω for these resistors gives us approximately 0.7/100 = 7mA current, through these resistors, which is an acceptable level for ¼ watt resistors. Starting at the load, we can find the required voltages for most of the output stage by considering that the amplifier is required to deliver at least 10 watts to a 16Ω load. The RMS current

required is given by 𝐼!"# =!!= !"

!"= 0.8𝐴. The peak current is then given by 𝐼!"#$ =

𝐼!"# 2 = 1.2𝐴. This means the peak voltage across the load must be 1.2 * 16 = 19.20V. An additional drop is across R8 and is 1.2A*0.47Ω = 0.56V. There is another 0.7 drop across the BE junction of Q5, making the maximum voltage at the base of Q5 19.2 + 0.56 + 0.7 = 20.46V. If Q5 is to be kept out of the saturation region, its emitter voltage should then be no more than 20.46 + 0.3V = 20.76V. A rule of thumb is to use five times the base current to bias the bases of BJTs, so assuming a common-emitter current gain (beta) of 100 for transistors, we want a current of (1.2A / 100) * 5 = 60mA in the signal splitter. This means we need (24-20.76V) / 60mA = 54Ω for R16. We chose the same for R15 because of symmetry. Also because of symmetry, we know the base of the current mirror must be approximately -20.76 + 0.7V = -20V. We chose values of 14kΩ and 2kΩ for R19 and R18, respectively, to get this base voltage in the current mirror. These resistor values can be higher than the resistors in the other branch of the current mirror, because the transistor used to set the current was a small signal BJT (2N3904) while the transistors in the base-biasing network were power transistors. The capacitor C1 was chosen to be 0.47µF as this was one of the largest available capacitors available that would fit in the breadboard sockets. R23, R4, R7, and R2 were chosen so that the resistance seen by the bases of both differential transistors is equal. 10kΩ is a typical value and was chosen for convenience. Ideally we would have chosen 5kΩ for R23, but it is not a standard resistor value and was not available in the lab, so we chose 4.7kΩ. A current mirror with roughly the same base voltage as the mirror in the output was needed for the differential stage. However, for the differential amplifier, a constant current source value of 1mA is typical. For a base voltage of -20V, we therefore needed (-24 – (-20)) / 1mA = 4kΩ for R1. A similar resistor ratio of 1:6 was chosen for the current mirror, and it was convenient to use a 1kΩ potentiometer for R10, so we went with a 100Ω resistor in R9 for maximum control of the quiescent current in the differential stage. The load resistor of the differential stage was chosen to be 33kΩ so that the output of the differential stage would still lie between ground and the positive supply rail but still have good voltage gain (a large current swing and/or large load resistance make for a good voltage gain in this stage). The load resistor of 16Ω at the output of the circuit was specified in the lab description.

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Designed circuits:

Figure 5: Schematic of complementary circuit

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Figure 6: Schematic of differential amplifier circuit

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Figure 7: Schematic of signal splitter circuit

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Figure 8: Schematic of final circuit

SPICE input models: The SPICE transistor models used in the final netlist are given in Table 2.

Reference Number Model Q1 2N3904 Q2 2N3904 Q3 2N3904 Q4 2N3906 Q5 2N3055 Q6 2N2955 Q7 2N3055 Q8 2N3904 Q9 2N3055 Q10 2N2955 Q14 2N3904

Table 2: SPICE input models

Design verification plots from SPICE simulations:

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Figure 9: Complementary circuit SPICE simulation waveform

Figure 10: Signal splitter stage SPICE simulation waveforms

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Figure 11: Differential amplifier SPICE simulation waveform

Figure 12: AC-Coupled full circuit SPICE simulation waveforms

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Figure 13: DC-coupled open loop transient SPICE simulation waveforms

Figure 14: DC-coupled open loop AC sweep SPICE simulation

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Figure 15: DC-coupled closed loop transient analysis SPICE simulation waveforms

Figure 16: DC-coupled closed loop AC sweep SPICE simulation

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DEVICE CHARACTERISTICS: See Appendix TEST RESULTS : Oscilloscope plots:

Figure 17: Complementary output stage, Vin=5V

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Figure 20: Complementary output stage with diodes bypassed, resulting in crossover distortion

Figure 21: Differential amplifier oscilloscope plot

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Figure 22: AC-coupled full amplifier

Figure 23: Complete amplifier, DC-coupled, open loop gain

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Figure 24: Complete amplifier, DC-coupled, closed loop gain, sinewave input, 1kHz

Figure 25: Complete amplifier, DC-coupled, closed loop gain, squarewave input, 1kHz

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Figure 26: Complete amplifier, DC-coupled, closed loop gain, squarewave input, 5kHz

The measured voltage transfer characteristics of the complementary output and the signal splitter stage are tabulated below.

Complementary Output Vout (V) DC 0 5 10 15 19 ‐5 ‐10 ‐15 ‐19

AC 1.005 0.983 0.833 0.515 0.27 0.978 0.808 0.47 0.26 Vin (V) DC 0 5.09 10.23 15.4 19.6 ‐5.16 ‐10.2 ‐15.4 ‐19.7

AC 1.029 1.007 0.852 0.527 0.28 1.003 0.831 0.48 0.27 AV (V/V) 0.98 0.98 0.98 0.98 0.96 0.98 0.97 0.98 0.96

Table 3: Copmlementary Output voltage transfer measurements

Signal Splitter Stage Vout (V) DC 1 5.1 ‐6 10.1 ‐11 15.6 ‐16 19.2 ‐19

AC 0.498 0.442 0.33 0.311 0.29 0.218 0.23 0.12 0.132 Vin (V) DC 20.9 20.8 21.1 20.7 21.2 20.5 21.4 20.3 21.5

AC 0.011 0.011 0.012 0.011 0.012 0.012 0.012 0.011 0.012 AV (V/V) 45.27 40.18 27.50 28.27 24.17 18.17 19.17 10.91 11.00

Table 4: Signal Splitter voltage transfer measurements

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Midband gains of the various stages and circuit configurations are shown below in AV (V/V) Measured Simulated Complementary Output (Vin = 19V) 0.96 0.88 Signal Splitter (DC Vin = 21.4V) 10.91 27.5 Differential Stage 104.41 120 Complete Amplifier, AC-Coupled 280.6 253 Complete Amplifier, DC 640 210 Complete Amplifier, DC with Feedback 558.13 100 Table 5: Measured vs simulated idband gains of various stages and circuit configurations

The measured frequency response of the AC-coupled complete circuit is shown numerically in Table 6 and graphically in Figure 27. Complete Complementary Output Amplifier ‐ AC‐Coupled Open Loop Vin (V) 0.037 Vin RMS (V) 0.026159

Frequency (Hz) Vout RMS (V) AV (V/V) 10 1.2 45.87 100 6.86 262.24 1000 7.34 280.59 3000 7.25 277.15 11263 5.98 228.60 24.3 5.8 221.72

f3dbl (Hz) 24.3 f3dbh (Hz) 11263 Bandwidth (Hz) 11238.7 Table 6: Complete amplifier - AC-Coupled OL Frequency response measurements

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Figure 27: Complete amplifier - AC-Coupled OL Frequency response measurements plot

Complete Complementary Output Amplifier ‐ DC‐Coupled Closed Loop Vin (V) 0.037 Vin RMS (V) 0.026159 RF (Ω) 2.20E+06 βF 4.52E‐03

Frequency (Hz) Vout RMS (V) AV (V/V) 10 3.8 145.27 100 12.54 479.38 1000 14 535.19 10000 14.6 558.13 15800 12.5 477.85 15.8 10.32 394.51

f3dbl (Hz) 15.8 f3dbh (Hz) 15800 Bandwidth (Hz) 15784.2 Table 7: Complete amplifier - DC-Coupled CL Frequency response measurements

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Figure 28: Complete amplifier - DC-Coupled CL Frequency response measurements plot

The measured results match the simulations in some cases but not in others. In particular, the complementary output circuit, the signal splitter, differential stage, and AC-coupled amplifier measurements all matched simulations relatively closely. We observed radically different results from simulations, however, for the final open-loop and closed-loop DC amplifiers. In fact, the gain of our breadboarded DC amplifier was much better than the gain found via SPICE simulations! Even after updating all components in our SPICE netlist to measured component values and BJT common-emitter current gains, transient simulations still did not match our measured results. The only explanation is that either 1) parasitics such as the capacitance of the solderless breadboard and external RF signals interacted with our circuit to actually improve its operation, 2) the BJTs used in our circuits were unknowingly being operated in modes that caused their performance to deviate significantly than that predicted by the device’s SPICE model, or 3) a combination of these two things. CONCLUSION: We were successful in designing and building a large signal amplifier consisting of a differential input stage and an output stage. In the process, we learned the principles of operation of differential amplifiers, signal splitters, and push-pull amplifiers. When these three stages are combined, they can be used One lesson learned in the design of differential amplifiers is to be careful of the bias collector currents in the two differential transistors. This is to allow maximum swing in both directions. In an earlier design, we chose too high of a load resistor that led to a very small bias current. This resulted in clipping at the bottom of the output of the differential stage, which was then amplified and clipped near the positive supply rail by the output stage, resulting in a pulse train at the output of the complete circuit.

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We learned that keeping the bias points at the top and bottom of the signal splitter and push-pull circuit symmetrical about ground is critical to ensure its proper operation. Potentiometers can be used in place of resistors to control bias currents and fine-tune the DC output level of the circuit. Finally, an important lesson learned this experiment is not to rely too heavily on SPICE simulations, when the actual circuit is to be breadboarded and parasitics may greatly influence the operation of the circuit. We spent a lot of time trying to get a perfect circuit in SPICE, only to find that the actual constructed circuit would not operate at all. To get our circuit to operate, we needed to more evenly balance the quiescent current flowing in the two branches of the differential stage, move the power supply closer to the differential circuit, and remove a troublesome potentiometer, whose resistance seemed to be unstable and affecting the circuit. APPENDIX: Curve tracer plots

Figure 29: Curve trace of Q1

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