labview fpga project management...
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Table of ContentsIntroduction..................................................................................................................................4Example LabView FPGA Project................................................................................................5Project creation...........................................................................................................................5
Target..................................................................................................................................7Adapter Module..................................................................................................................9Clocks...............................................................................................................................11Memory.............................................................................................................................15FIFOs................................................................................................................................20VI.......................................................................................................................................22Component Level IP.........................................................................................................23Extra I/O............................................................................................................................29RIO Device Setup.............................................................................................................29
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Illustration IndexFigure 1. 'patter_generator' LabView project..............................................................................5Figure 2. LabView 2010 SP1 Main Interface.............................................................................6Figure 3. New LV FPGA project.................................................................................................6Figure 4. Files corresponding to a new LV FPGA project..........................................................7Figure 5. Available targets...........................................................................................................7Figure 6. Identification of two cards present...............................................................................8Figure 7. Target FPGA...............................................................................................................8Figure 8. IO Module properties...................................................................................................9Figure 9. Clock output assignment...........................................................................................10Figure 10. Socketed CLIP implementation files........................................................................10Figure 11. CLIP VHDL source code..........................................................................................11Figure 12. Top level clock..........................................................................................................11Figure 13. Derived clock..........................................................................................................12Figure 14. Derived 80 MHz clock..............................................................................................14Figure 15. Add of additional base clocks..................................................................................15Figure 16. Input clock from the 6585 adapter card at DDCA....................................................15Figure 17: IO Module clock properties.....................................................................................16Figure 18. DRAM properties.....................................................................................................17Figure 19. DRAM banks in the project manager.......................................................................18Figure 20. DRAM Bank Properties............................................................................................19Figure 21. DRAM Clock selections...........................................................................................20Figure 22. DRAM Random access mode.................................................................................21Figure 23. DRAM Socketed CLIP implementation files............................................................21Figure 24. Embedded memory generator.................................................................................22Figure 25. Target scoped FIFO.................................................................................................23Figure 26. Host to target FIFO..................................................................................................24Figure 27. Target to host FIFO..................................................................................................24Figure 28. FIFOs in project manager........................................................................................25Figure 29. Adding a vi to the project manager..........................................................................25Figure 30. New component IP xml file......................................................................................27Figure 31. Xml component IP file..............................................................................................27Figure 32. Creation of a new IP item.......................................................................................28Figure 33. IP clock handling......................................................................................................30Figure 34. IP generics...............................................................................................................30Figure 35. IP terminals..............................................................................................................31Figure 36. IP Component item.................................................................................................34Figure 37. Extra I/O...................................................................................................................35Figure 38. RIO setup : bitstream...............................................................................................36Figure 39: RIO setup: autoload.................................................................................................36
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IntroductionIntroduction
The main purpose of this document is to depict the LabView FPGA philosophy to develop firmware. This description summarizes the steps necessary to create and manage a LabView FPGA project. It reproduces, in some detail and from scratch, all stages needed to get to a working project, where the user can access all components for customization or bug fixing.
In order to show to the user how to start using LV FPGA, an example project is illustrated here. A pattern generator application has been developed for sending / acquiring a user defined digital data pattern to / from the front end adapter card. This project gives an example on the necessary 'bricks' to build up a complete application. However, the concrete technical details of how it works and how this application must be used are not given here. For additional information, please refer to the documents 'Pattern generator documentation – User Manual' and 'Pattern generator documentation – Developper Guide'.
We will be using here a Ni-FlexRIO 7962R module along with an 6585 adapter card in pattern generator mode. All that follows has been developed using LabView FPGA release 10 SP1. The corresponding Xilinx tools necessary to compile the project's sources are release 11.5 (to be found under the C:\NIFPGA\programs\Xilinx11_5 folder). This is important for compatibility reasons when using a netlist generated by the user with Xilinx Core Generator.
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Example LabView FPGA ProjectExample LabView FPGA Project
The necessary firmware and software to run the FlexRIO 7962R card in pattern generator mode can be found under the 'patter_generator.lvproj' project file as shown in the figure below.
This project comprises two item cards, namely RIO0 and RIO1. Its use from the software point of view is described in the document 'Pattern generator documentation – User Manual'. Here we concentrate on the way to create an FPGA LabView project and on how to add items to it. Project creationProject creation
First step to start creating a LV FPGA project is, not surprisingly, launching LabView. The user is presented at this point with the following wizard, summarizing the several possibilities offered to him (open recent files / projects, inspect examples, obtaining help, etc.)
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Figure 1. 'patter_generator' LabView project
By selecting 'New → Empty Project', it is possible to generate a new, empty project as well as the corresponding files on disk
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Figure 2. LabView 2010 SP1 Main Interface
Figure 3. New LV FPGA project
After having successfully created a new project, the user may add / create new vi's to include custom functionalities to his application. The project contains source LV code to be run at the host side (PC), as well as source code to be executed in the programmable target (FPGA) within the FlexRIO card. Previous to manage any firmware resource, the user has to instantiate the target device.
TargetFor creating a new target the sequence
My Computer → New → Targets and Devices
allows accessing to a list of available target devices currently plugged to the PXI crate. For example, in the case of the figure below, two FPGA targets have been detected. They are identified as RIO0 and RIO1.
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Figure 4. Files corresponding to a new LV FPGA project
Figure 5. Available targets
In order to cross check which card corresponds to which target, the user can use the 'Measurement and Automation' tool provided with all LV installation, as shown in the capture below, where two cards are plugged to the slot number 6 and 8 of the crate. The alias names RIO0 and RIO1 are clearly identified here.
By selecting one of the proposed targets, a 'FPGA Target' instance is newly created under the project manager.
By default, some standard resources are included within a newly created target. These are a 40 MHz clock and an instance to the detected adapter module present, if any. In the case of the previous figure, an 6585 front end is available in its 'basic connector' configuration.
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Figure 6. Identification of two cards present
Figure 7. Target FPGA
Adapter Module
Adapter modules allow communicating the FPGA target with the outer world. They define a set of signal / port mapping to be accessed from the firmware. Several configurations are provided, and some other set up is necessary for its correct operation. For accessing the module properties, the user may use the sequence
IO Module → Properties
Here, a list of ni adapter modules is listed and their corresponding available different configurations are shown. For example, the 6585 module provides up to a 200 Mb/s SDR or 300 Mb/s DDR digital interface to FlexRIO products. It provides 32 LVDS digital I/O channels, 10 PFI lines (general purpose), and external clock input/output signals.
Three different configurations are possible for this adapter:
• The 'basic connector' is a simple connector-based CLIP for the NI FlexRIO LVDS adapter module. It has 32 data lines, eight PFI lines, two clock inputs, two clock outputs, and allows for individual clock output inversion.
• The 'basic channel' is a simple channel-based CLIP. It has 32 data lines, eight PFI lines, two clock inputs, two clock outputs, and allows for individual clock output.
• The 'DDR connector' is a DDR connector-based CLIP. It has 32 data lines, eight PFI lines, two clock inputs, two clock outputs, and allows for individual clock output inversion.
Right after having defined the configuration to be used, the user may proceed to defining the clock to output over each port (DDCA and DDCB).
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Figure 8. IO Module properties
In the previous capture, a list of the available clock sources is presented under the form of a list to be assigned to each DDC output clock. Refer to the 6585 technical documentation at http://sine.ni.com/nips/cds/view/p/lang/es/nid/207297 for details on this module.
Finally, to have a closer insight to the logic implemented behind this module, the user may have a look to the Socketed CLIP1 implementation files, available on disk.
The source code shown on previous figure gives a deeper insight on what's happening behind the user interface provided by the CLIP. This may be practical for deciding whether it is useful or not no instantiate custom, advanced hardware resources without having to compile the whole.
1 A socketed CLIP is a piece of VHDL code which interfaces the user code with the adapter card, including correct pin assignment as well as some low level management (clock multiplexing, etc.). Its main purpose is to provide the final user with a friendly interface to the adapter hardware.
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Figure 9. Clock output assignment
Figure 10. Socketed CLIP implementation files
At this point, the user may proceed to adding new hardware resources to the project. These new resources need to be created before being used within any firmware's vi. These include memories, FIFO's, clocks, etc.
ClocksClocks allow synchronization of processes in a variety of possible configurations. A top level clock can be declared by issuing the command
FPGA Target → Properties → Top-Level Clock
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Figure 11. CLIP VHDL source code
Figure 12. Top level clock
In this case, the user has to chose between all available clocks in the project manager. By default, only a base 40 MHz clock can be used. From this frequency, additional, derived clock sources can be generated
40 MHz On Board Clock → New FPGA Derived Clock
In the previous caption, a 80 MHz clock source is created. LV FPGA manages the necessary hardware resources to handle the new clock, so that the user doesn't need to care about low level, concrete implementation.
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Figure 13. Derived clock
Figure 14. Derived 80 MHz clock
Further on, there exists the possibility to add extra base clocks to the project manager
FPGA Target → New → FPGA Base ClockBase clock sources include the 10 MHz backplane PXI clock, and most important, the 'IO Module Clock 0 /1'. The last correspond to input clocks available from the 6585 adapter module explained in previous section of this document. The 'IO Module Clock 0' corresponds to the DDCA single ended input clock, while DDCB 'IO Module Clock 1' gives access to the DDCB differential input clock.Next figure shows how to get access to these clocks.
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Figure 15. Add of additional base clocks
Once the new resource has been generated, it should appear under the project manager as shown here
Finally, the user needs to specify what is the maximum expected frequency for this external clock. This is necessary for correctly constraining the generated source files. In next figure the user can introduce the main parameters regarding this clock
IO Module Clock → Properties
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Figure 16. Input clock from the 6585 adapter card at DDCA
Figure 17: IO Module clock properties
These informations will be sent to the synthesis Xilinx tools for its proper use.
MemorySeveral different types of memories can be used when dealing with a FlexRIO card. Two large DRAM blocks exist along with configurable, embedded blocks of BlockRam memory within the main FPGA. All of them can be instantiated from the project manager so that they can be used in firmware. As a first step, the user must configure the type of memory he will be using. For this, he needs to access to the target's properties
FPGA Target → Properties → DRAM Properties
Setting 'Socketed CLIP' for each of the two DRAM banks allows using pre-defined bridges to the DDR memory blocks. This eases the design of firmware by providing direct access to friendly interfaces providing whether a FIFO type or to a random access classic memory.At this point, the project manager includes two new items corresponding to each of the DRAM banks, as show below.
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Figure 18. DRAM properties
Before having access to them, it is necessary to enable the DRAM blocks. For doing this, verify the blocks' properties with
DRAM Bank 0 → Properties
The user must check enable the corresponding block so that it can be used from the project manager. This is possible from the 'General' tab. Then, one of the available configurations must be defined.The first configuration organizes the external memory as one large FIFO, using a 128-bit data port. To use the input side of the FIFO, the user must first configure the 'Write_Clock' to run
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Figure 19. DRAM banks in the project manager
Figure 20. DRAM Bank Properties
on the same clock domain as his input-side process. Then he needs to strobe the 'Write' signal for one clock cycle to cause the FIFO to latch the 'Write_Data_Upper' and 'Write_Data_Lower' signals. The 'Full' signal will assert high when the FIFO is full.To use the output side of the FIFO, the user first has to configure the 'Read_Clock' to run on the same clock domain as the output-side process. The 'Data_Available' signal will assert high when data is ready to be popped out of the FIFO. By strobe of the 'Read' signal for one clock cycle, data is pop out of the FIFO. The user must latch the 'Read_Data_Upper' and 'Read_Data_Lower' signals on the same clock cycle that he asserts the 'Read' signal.This version of the memory interface will automatically disable synchronization registers on all FPGA I/O to and from the memory interface. All synchronization registers on FPGA I/O to and from this memory interface must be disabled in order for it to function properly.Write and Read clock domains are to be defined under the 'Clock Selections' tab.
A second configuration is provided for having access to the DRAM memory in random access mode. In this case, LV presents a random-access external memory interface with a 128-bit data port. Requests to write to and read from memory are satisfied by issuing a write or read command to this memory interface. To issue a write, it is necessary to set the 'Command' signal to 0 and assert 'Command_Write_Enable'. To issue a read, it is necessary to set the 'Command' signal to 1 and assert 'Command_Write_Enable'. Then, the firmware needs to latch the read data on the same clock cycle that 'Read_Strobe' asserts. 'Command_Write_Enable' should never be asserted when 'Command_FIFO_Full' is true.
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Figure 21. DRAM Clock selections
Finally, to have a closer insight to the logic implemented behind this module, the user may have a look to the Socketed CLIP implementation files, available on disk.
The source code shown on previous figure gives a deeper insight on what's happening behind the user interface provided by the CLIP. However, some of the interface logic is hidden here by just providing netlists (compiled VHDL code), which makes reading these sources of a limited interest.
Note that the use of Memory Socketed CLIPs are mandatory in a firmware vi in order to transfer data between the DRAM and the FPGA. This means that the user is forced to create a firmware vi to instantiate and use them.
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Figure 22. DRAM Random access mode
Figure 23. DRAM Socketed CLIP implementation files
To end up with this section on memories, note that there exist an advanced use of the memory generator embedded with the LV FPGA project manager. By selecting
FPGA Target → Properties → DRAM Propertiesthe user will have access to a menu where he will be able to configure more advanced features
FPGA Target → New → Memory
This allows, for example, the generation of true double port RAMs, single port ROMS, etc., having access to more complex and flexible memory configuration options. This is a new item added to LV FPGA 2010 SP1. The author of this document never used this utility as these features are provided by the standard Xilinx tools.
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Figure 24. Embedded memory generator
FIFOsThe capability to use FIFOs in firmware include target scoped standard FIFOs generated using FPGA resources (BlockRam and build-in FIFOs), as well as DMA FIFO's. The last ones are one of the big advantages of using LV FPGA along with the FlexRIO technology. It shadows the complexity of implementing data readout through a DMA channel using the PXIe standard. Instead, users only need to instantiate a DMA FIFO component in their firmware vi and send / read data to / from the host PC as they would in any standard FIFO. For creating a new FIFO, the user must issue this sequence
FPGA Target → New → FIFOSeveral different possibilities are offered to the user here.Target scoped FIFO based on block memory, look-up tables or flip-flops. The actual number of elements can vary when using Target Optimal control logic because the application implements FIFOs using slice fabric or built-in control logic depending on the clock domain and target type on which the FIFO is used.
Host To Target – DMA, this type of FIFO allows the user to send data from the host PC to the target device.
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Figure 25. Target scoped FIFO
Target To Host – DMA, this type of FIFO allows the user to send data from the target device to the host PC.
Note that the use of DMA FIFO's is mandatory in a firmware vi in order to transfer data between the target device and the FPGA. Target scoped FIFO's are a gadget of LV FPGA, they can be easily generated using standard Xilinx tools. After having successfully created three FIFOs, one of each type, the project manager should
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Figure 26. Host to target FIFO
Figure 27. Target to host FIFO
look similar to the figure below
VIVi's can be created or imported to the project manager. For this, just proceed as shown below
FPGA Target / My Computer ...→ New → vi
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Figure 28. FIFOs in project manager
Figure 29. Adding a vi to the project manager
As an alternative, it is possible to add existing code to the current project. Three different alternatives exist
FPGA Target / My Computer → Add …
◦ File, adds a single file to the project
◦ Folder (snapshot), adds to the project the currently existing list of files in a folder
◦ Folder (Auto Populating), adds to a project all files in an existing folder and updates it if necessary, meaning that newly added files will be refreshed in the project's view
As a rule, firmware vi's must appear under the 'FPGA Target' item, while the host vi's should be included under the 'My Computer' item. As a good design practice, firmware vi's should be named with the 'FPGA' keyword appearing in the vi's name. This allows to clearly differentiate each type of vi (firmware and software).
Component Level IPThis kind of item gives the opportunity to the user to develop VHDL code. In addition, it allows the use of the tools provided by the Xilinx toolchain, namely the Core Generator. This way, the user may generate and instantiate all available FPGA resources. Then, the source code must be included in the project manager as a new item. At this point, it can be instantiated as any other item.Following the example provided by the 'pattern generator' project, a component level called 'pattern_top' will be created in an example project. Two files are necessary for this.
• Xml file, defining the interface between the VHDL code entity and LV FPGA; this interface defines input / output ports, clocks, asynchronous resets and conversion rules between VHDL data types and LV FPGA data types. It translates VHDL port names to LV FPGA signal names too.
• VHDL source code, defining the logic to be implementedOnce these two files are available2, the user must proceed as described here. First, define a new component IP in
FPGA Target → Properties → Component Level IPand select
Add → Xml Fileas shown below
2 Refer to the corresponding patter generator documentation 'Pattern generator documentation – User Manual' and 'Pattern generator documentation – Developper Guide' for more details on these two files
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Since release 2010 SP1 of LV FPGA, it is possible to create or modify and existing xml file graphically. There exists the possibility to check the syntax of an existing file too. The author of this document new gave a try to this, preferring to modify the file by his own using a standard text editor, as shown in next figure.
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Figure 30. New component IP xml file
Figure 31. Xml component IP file
The xml file includes a set of attributes declared using standard xml tags. Any of these files may be used as a template and adapted to new components by hand. Note that within a VHDL file there may exist additional component instantiations. These may be standard source files as well as netlists generated by external tools. A complete list of these additional files must be provided to LV FPGA and listed within the xml file, along with any other necessary file (constraints, etc.). This way, a whole structure may be created indecently of the LV FPGA workflow. Then, it may be used as a single IP component. All provided files will be transferred to Xilinx tools for synthesis, placement and routing.Once the project manager is aware of the existence of the IP component, a new item referring to this component can be created with
FPGA Target → New → Component Level IP
Some of the parameters of the IP component must be attached to LV FPGA items. For example, under the 'Clock Selections' tab, the user has to define which of the LV FPGA clocks must be connected to which IP clock, as declared in the xml file. Following with the same example (see figure below), three different clock domains are used in the VHDL code. The 'clk' signal must be connected to the fast, 160 MHz clock previously derived from a base clock. In a similar way, the 'clk_slow' clock must be associated to the base 40 MHz clock and finally, the 'extern_clock' has to be attached to the 'IO Module Clock 1' coming from the front face adapter card. See the 'Clocks' section of this document for more information of clock management within the project manager.
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Figure 32. Creation of a new IP item
In addition, if the user's VHDL code defines generics, its value may be defined under the 'Generics' tab. Otherwise, default values will be used as declared in the source VHDL file.
Finally, the port signals declared in the VHDL source code (entity) must correspond to valid LV FPGA data types (only 8, 16, 32 and 64 bits types are accepted). For a crosscheck of their
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Figure 33. IP clock handling
Figure 34. IP generics
correspondence, as defined in the xml file, the 'Terminals' tab gives the opportunity to the user to verify that signals have the correct type correspondence in the LV FPGA world.
At this point, a new 'pattern_top' item must be available in the global project view, as show below. In next figure, the new item is shown along with the list of available ports. This list corresponds to the signals enumerated in the entity declaration of the IP component, as can be appreciated in the corresponding VHDL source file. As stated before, the mapping between both (LV FPGA ports and entity signals) is given in the interface xml file.
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Figure 35. IP terminals
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Extra I/OExtra inputs / outputs can be added in the list of available items under the project manager. These include synchronization signals, status signals, etc. To get access to them, the user has to issue the order
FPGA Target → New → FPGA I/O
RIO Device SetupDefault device settings as well as default running firmware may be specified with the help of
FPGA Target → RIO Device Setup …This order gives access to the figures shown below, where the user may provide the default bitstream to be run at startup by loading it to a flash memory on board. In addition, he can decide how to behave at device startup / reboot.
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Figure 37. Extra I/O
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Figure 38. RIO setup : bitstream
Figure 39: RIO setup: autoload