larco rrogasian

8/7/2019 LARCO RROGASIAN

1/46

1

LABORATORY WORK REPORT

Question 1a

1.0. INTRODUCTIONThe combinational Logic circuit is the circuit which its output depends only on the input of the

circuit. Any change of the input means change in the output.

2.0 DESIGN THEORY

Since the circuit is combinational, the truth table can be used to realize its circuit and a K-map is

used to minimize each output of the circuit. From the given information, the J input is the control

signal of which when it is TRUE i.e. equals 1 and the input is converted to its equivalent code II

as indicated on the lab question. When the control signal J is FALSE i.e. equals 0 then inputs are

converted to its equivalent code III.

2.1. TRUTH TABLE

The truth table consists of five inputs J, A, B, C and D with four outputs W, X, Y and Z.

MINTERM

INPUT OUTPUT

J A B C D W X Y Z

0 0 0 0 0 0 d d d d1 0 0 0 0 1 0 0 1 1

2 0 0 0 1 0 0 1 0 0

3 0 0 0 1 1 d d d d

4 0 0 1 0 0 0 1 0 1

5 0 0 1 0 1 d d d d

6 0 0 1 1 0 d d d d

7 0 0 1 1 1 d d d d

8 0 1 0 0 0 0 1 1 0

9 0 1 0 0 1 0 1 1 1

10 0 1 0 1 0 1 0 0 0

11 0 1 0 1 1 d d d d


2/46

2

12 0 1 1 0 0 1 0 0 1

13 0 1 1 0 1 1 0 1 0

14 0 1 1 1 0 1 0 1 1

15 0 1 1 1 1 1 1 0 0

16 1 0 0 0 0 d d d d

17 1 0 0 0 1 0 0 0 0

18 1 0 0 1 0 0 0 0 1

19 1 0 0 1 1 d d d d

20 1 0 1 0 0 0 0 1 0

21 1 0 1 0 1 d d d d

22 1 0 1 1 0 d d d d

23 1 0 1 1 1 d d d d

24 1 1 0 0 0 0 0 1 1

25 1 1 0 0 1 0 1 0 0

26 1 1 0 1 0 0 1 0 1

27 1 1 0 1 1 d d d d

28 1 1 1 0 0 0 1 1 0

29 1 1 1 0 1 0 1 1 1

30 1 1 1 1 0 1 0 0 0

31 1 1 1 1 1 1 0 0 1

2.2. K-MAP MINIMIZATION

The minimization and simplification is done through the use of five variables K-map, and we

consider the Product of Sum (POS) and the Sum of Product (SOP) format.


3/46

3

i. For the output W

BCD

JA

000 001 011 010

00 d 0 d 0

01

0 0 d 1

11 0 0 d 0

10 d 0 d 0

From the K- Map:

SOP expression can be obtained by considering all 1s and dont cares, and the following

simplified expression was obtained.

W = JAB + BC + JAC

The total number of gates is five.

POS expression can be obtained by considering all Os and the dont cares, and the following

simplified expression was obtained.W = A (J+A+C) (A+B+C) (J+D+B)

ii. For the output X

BCD

JA

100 101 111 110

00 0 d d d

01 1 1 1 1

11 0 0 1 1

10 0 d d d


4/46

4

From the K- Map:

SOP gives the following value:

Collecting all 1s and dont cares the following simplified expression.

X = JAD +ABD + JCD+JABC+JABC+JABCD

The total number of gates is twelve.

POS

Collecting all the Os and the dont cares to obtain a simplified expressionX = (A+D) (J+A+B+C) (J+A+D+C) (J+A) (J+B+D+C) (J+A+B+C)

The total number of gates is twelve.

iii. For the output Y

BCD

JA

000 001 011 010

00d 0 d 1

01

1 1 d 0

11

0 1 d 1

10

d 0 d 0

BCD

JA

100 101 111 110

00

1 d d d

01

0 0 1 0

11

1 1 0 0

10

0 d d d


5/46

5

SOP

Collecting all 1s and dont cares the following simplified expression.

Y = JCD + JBC + JBCD+ABCD (a total of nine gates)

POS

Collecting all the Os and the dont cares to obtain a simplified expression

Y= (C+D) (J + B+C + D) (J+C) (J+B+C+D) (B+C)

The total number of gates is ten.

iv. The output Z

SOP

Z =

JBCD + JBD + JABD+JBD + JBD

The total number of eight gates are going to be used to implement the

BCD

JA

000 001 011 010

00

d 1 d 0

01

1 1 d 0

11

1 0 d 0

10

d 0 d 0

BCD

JA

100 101 111 110

00

0 d d d

01

0 1 0 1

11

1 1 0 0

10

1 d d d

BCD

JA

000 001 011 010

00

d 1 d 0

01

0 1 d 0

111 0 d 1

10

d 0 d 1

BCD

JA

100 101 111 110

00

1 d d d

01

1 0 0 1

110 1 1 0

10

0 d d d


6/46

6

POS

Collecting all the Os and the dont cares to obtain a simplified expression

Z= (J + B + D) (J+A + B+ D) (J+B + C+ D) (J + B + D) (J + B + D)

A total number of eleven gates are going to be used.

3.0. CIRCUIT AND SIMULATION

3.1. Circuit

With accordance to the above simplification, designs which favor a small number of gates have

been considered. And therefore, for implementing, SOP format is going to be used, for X a POS

format is considered despite of having the same number of gates but have less number of inputs

compared with the SOP format, for Y a SOP format is going to be used and a SOP is used.


7/46

7

J

DCBA

W

X

Y

Z

V10V

1234

A

KPD1

1234

output

W

X

Y

Z


8/46

8

3.2. Waveform

After simulating the following waveforms were thus obtained as shown below.

4.0 CONCLUSION

From the analysis above it can be observed that using different format representation (POS and

SOP) can result into reducing the number of gates used on the chip and input to the chip as well

and therefore minimizing cost and delay due to the large number of gates in the circuit.

Question 1b

W

X

Y

Z

161016001590158015701560


9/46

9

1.0. INTRODUCTIONEncoder is the digital function that produces a reserve operation from that of a decoder.

An encoder has 2n inputs and n output lines. The output lines generate the binary code for2n

input variables. The encoder assumes that only a single input is 1 at a time. The encoder is the

combinational circuit since the output depends directly from the input and the truth table is used

to realize the circuit of it.

2.0. DESIGN THEORYThe encoder as explained above in this case is the octal decoder which consist of 8 input lines

(equivalent to 2n and thus n=3) of which only one line is assumed high and consist of 3 output

lines that generates the corresponding input binary number.

2.1 TRUTH TABLEN

ote that the circuit has 8 inputs and could have 2

8

=256 possible input combination but only 8of these 256 inputs has any meaning and the other input are the dont care condition. That is why

only 8 inputs are considered with 3 output lines generating these eight inputs.

Therefore the below is the truth table of the 8 by 3 encoder (associating only 8 inputs with any

meaning) where A7 (most significant bit) through A0 (list significant bit) are the input and B2

(MSB) through B0 (LSB) are the output lines.

INPUTS OUTPUTS

A7 A6 A5 A4 A3 A2 A1 A0 B2 B1 B0

1 0 0 0 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 1 0

0 0 0 1 0 0 0 0 0 1 1

0 0 0 0 1 0 0 0 1 0 0

0 0 0 0 0 1 0 0 1 0 1

0 0 0 0 0 0 1 0 1 1 0

0 0 0 0 0 0 0 1 1 1 1

2.2. Minimization and simplifications


10/46

10

After the truth table, the following results obtained after simplification using the SOP format

where the output is the function of the inputs.

B2 = A3 + A2 + A1 + A0

B1 = A5 + A4 + A1 + A0

B0 = A6 + A4 + A2 + A0

3.0 CIRCUIT AND SIMULATION3.1 The circuit diagram

The circuit below was thus drawn from the simplified equations above using the circuit maker

software. The data sequence generates the inputs to the circuit. This data sequence is triggered by

the clock as shown on the circuit.

3.2. Waveform

After simulating the above circuit, the following were the waveform developed.

4.0CONCLUSIONAs spotted above, there are 8 inputs therefore 256 input combinations were expected.

CP1CP2

Q1Q2

V1

B0

B1

B2

1234

DISP1

87654321

CP1CP2

DataSeq

DS1

U2A

U1B

U1A

B0

B1

B2

1680167016601650164016301620


11/46

11

However the situation is not the case since out of all these 256 only 8 inputs has any meaning

and thus they are only considered while remaining are treated as dont care condition.

Encoders of this type however are not available in IC packages, since they can be easily

constructed with the OR gates. The encoder available in IC form is called the priority encoder.

Question 1c. Design of an 8X1 multiplexer

1.0INTRODUCTION


12/46

12

A digital multiplexer is the combinational logical circuit that selects binary information from one

of many input lines and directs it to a single output line. The selection of an input line is done by

a set of selection lines also known as control lines. There are normally 2n

input lines and n select

lines (of which its combination determines which input to output i.e. selected).

2.0. DESIGN THEORY

An 8x1 multiplexer is the digital circuit with the eight input lines (23) and thus 3 selection lines

to identify which input among the eight has been selected.

2.1. Truth table

The following bellow is the truth table realizing the multiplexer with eight inputs lines and a

single output line. A, B, and C are the selector.

INPUT OUTPU

T

A B C F

0 0 0 I1

0 0 1 I2

0 1 0 I3

0 1 1 I4

1 0 0 I5

1 0 1 I6

1 1 0 I7

1 1 1 I8

2.2. Minimization and simplification

From the table above the following simplification were thus obtained

F = ABC I0+ ABCI1 + ABC I2 + ABC I3 + ABC I4 + ABCI5 + ABCI6 + ABCI7


13/46

13

3.0. CIRCUIT AND SIMULATION

3.1. The circuit diagram

The circuit diagram below is a result the logic function obtain above after minimizing the

information from the truth table and the circuit thus drawn using the circuit maker software. The

selector inputs as well as the eight input data to the circuit are generated by the data sequencer of

which is triggered by the clock as shown on the circuit below.

3.2. Simulation and Wave Forms

From the same circuit maker then the wave forms of the developed circuit after simulating was

then obtained as shown on the wave forms that follow.

87654321

CP1CP2

DataSeq

DS2

34

DIS

F

CP1CP2

Q1Q2

V1

U1A

U1B

U2A

U2B

U3A

U3B

U4A

U4B

U5A

U5B

U6A

U7AU7BU7C87654321

CP1CP2

DataSeq

DS1


14/46

14

4.0. CONCLUSION

From the waveform there are glitches (the point where the wave goes high and back to low

immediately) observed which are resulted from the internal delays of the gates, longer circuit

wire and other related contributed factors. Multiplexer found itself very useful MSI function and

has a multitude of applications. It is used for connecting two or more sources to a single

destination among computer units and useful in constructing a common bus system.

Question 1d.

1. INTRODUCTIONA decoder is a combinational logic device which converts binary information from n input lines

to a maximum of 2nunique output lines. It is a combinational device since the output depends

direct from the input i.e. any change done on the input will also affect the output.If the n-1

F

750740730720710700


15/46

15

decoded information has unused or dont care combinations, the decoder output will have less

than 2n

outputs.

2. DESIGN THEORYDuring designing of 5X32 decoder i.e. 5 input lines with 32 output lines, four 3X8 decoders aretherefore used making a total of 32 outputs with three inputs shared among the all four decoders.

The remaining two input lines will be used to generate 4 output lines on which each of these four

lines will be used as an enable signal to the four decoders (3X8).

Therefore for designing simplicity, two circuits are developed one for 3X8 decoder and the

remaining one for 3X8 decoder. And the overall 5X32 decoder resulted by integrating the four

3X8 decoder and one 2X4 decoder in a block diagram.

i. For 3x8 decoderThe decoder receives three lines and produces eight lines on which among them is selected as an

output. On this decoder an enable signal is then also associated.

ii. Truth tableThe truth table below assumes the following: A is the MSB and C the LSB of the inputs while D7

is the MSB and D0 is the LSB of the outputs

A B C D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1

Minimization and simplifications

D7 = ABC D4 = ABC D1 = ABC

D6 = ABC D3 = ABC D0 = ABC

D5 = ABC D2= ABC


16/46

16

iii. 3x8 Decoder circuit

iv. 2X4 decoderThe decoder receives two lines and produces four lines on which among them is selected as an

output. On this decoder signal an enable signal is not associated.

3. Truth table

A

B

C

ENABLE

5V

INPUTS OUTPUTS

A B D3 D2 D1 D0

0 0 1 0 0 0


17/46

17

The truth table below assumes the following: A is the

MSB and C the LSB of the inputs while D7 is the MSB

and D0 is the LSB of the outputs

The outputs are: D3 = AB D2= AB D1 = AB D0 = AB

The circuit for 2X4 decoder is as follows

4. Circuit diagram

U2B U2A

U1D

U1C

U1B

U1A

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1


18/46

18

From the given two design a 5 by 32 decoder can be designed using four 3 by 8 decoders and 0ne

2 by 4 decoder as described above. The designed diagram in block diagram is as shown below

showing all the 32 outputs and the 5 inputs.


19/46

19

4555

A1A0

E Q0Q1Q2Q3

1/2

Decoder

1234 1234

U25B

U25A

U24B

U24A

U23B

U23A

U22B

U22A

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

U21B

U21A

U20B

U20A

U19B

U19A

U18B

U18A

12341234

1234 1234

U17B

U17A

U16B

U16A

U15B

U15A

U14B

U14A

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31CP1CP2

Q1Q2

CLK

87654321

CP1CP2

DataSeq

DataGen

U1A

U1B

U2A

U2B

U3A

U3B

U4A

U4B

U5AU5BU5C

12341234


20/46

20

Waveforms after the simulation of above circuit

Question 2a

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

370360350340330320


21/46

21

1. INTRODUCTIONA memory cell is a storage device with the capability of storing a single bit data at a time. This

memory cell can either be a single core memory or flip flop of different types such as JK, SR, D

and T flip flop.

2. DESIGN THEORYAs the memory cell is concern, it can be active or in active. The decision of whether the cell is

active or not active is done through the use of selector signal. However when the cell is active

then it can either be performing writing or reading. The reading and writing operation is mainly

done by the Read/write signal to the system where 1 for the read and 0 for the write.

The circuit behaves purely combinational when during reading the data and sequential when

during writing.

i. During reading

Truth table

R/W Sel Output data

0 0 inactive

0 1 Dont care

1 0 inactive

1 1 Dout

Minimization and simple circuit

Output = R/WSelDout

U1A


22/46

22

ii. During writingDuring writing, the select (S) need to be high making the cell active in order to accept the written

data. Apart from that, the write signal also needs to be active to signify writing.

Assume the cell has two state that is state 0 (the previous written data was zero) and state 1 (theprevious written data is 0ne)

a) State diagram

b) State tableData previous

in cell

Data to be written

0 1

A A B

B A B

c) State assignment tableFrom the table above, let A=0 and B=1 and therefore the following is the state assignment table.

P.S Input data N.S

0 0 0

0 1 1

A B


23/46

23

1 0 0

1 1 1

d) The excitation state and truth table using SR flip flop

P.S Input data

(Din)

N.S S R

0 0 0 0 d

0 1 1 1 0

1 0 0 0 1

1 1 1 d 0

Minimization

From the table above, the following have been obtained

S= Din and R= Din

However, for the data to be written as explained above, then the select signal need to be high and

the R/W signal need to be zero. Therefore, the data input is going to be ended with these to

signals and thus the S and R are thus going to be as follows

S = SelWDin and R = SelWDin

3. The circuit diagramFor the memory cell which reads and writes, then the following circuit which is the combination

of the above two is thus obtained.


24/46

24

Resulting wave forms

Question 2b

1. INTRODUCTION

RW5V

Sel5V

Din

DoutCP1CP2

Q1Q2

CLK

S

R Q_Q

S0

Di n

Dout

340330320310300290280


25/46

25

Memory cells can be configured in different configurations containing cells of any number such

as a configuration of 4x3 where four rows of three memory cells. And each memory cell is a one

bit memory cell.

2. DESIGN THEORYA 4x3 RAM consist of 12 memory cells in total of which each three memory cells are arranged

on a single row. The design is based on a single memory cell. The single cell involves the

following signals; the selector signal for deciding the activeness or inactive of the cell, the

Read/write signal for making decisions whether to write or to read with bit 1 for read and 0 for

write, the data in signal supplying data to the memory and the data out signal to produce the

result during read.

The four rows of three memory cell each are controlled by the enable input of the decoder. The

decoder is disabled when the line is zero and at this time none of the memory words are selected

and when the decoder is enabled i.e. the line is 1 one among the four words is selected dependingon the addressing.

3. Circuit realizationi. Considering a single cell

Memory cell


26/46

26

The bellow circuit is the single memory cell as designed on the above problem 2a.

The select signal which is the address to be monitored by the decoder can either be one

indicating the word has been selected or zero signifies no word for that memory has been

selected, while the R/W signal signifies read (1) or write (0) operation respectively. For the 4X3

memory unit then each cell need to have this signal for symmetry purpose. The clock in this case

behaves as the input data signal.

ii. Circuit realization for the 4X3 memory unitFrom the theory and analysis from the single cell memory, then a three row four column circuit

is designed and obtained as shown below where the input to the memory unit is generated by thedata sequencer on which at this moment acts as the buffer for input data and is triggered by the

clock as shown on the circuit below. The decoder as explained above is the one which provide a

select signal to each row indicating which row is active i.e. which word has been selected. And

on a single word can be selected at a time however the memory unit is capable of handling four

words of three bits each. Furthermore, the decoder is triggered by the enable signal (as explained

above)

RW5V

Sel5V

Din

DoutCP1CP2

Q1Q2

CLK

S

R Q_Q

S0


27/46

27

V35V

V20V

CLK

D0D1D2

CP1CP2

Q1Q2

V1

1234

DISP1U31A U30B

U30A

U29C

U29B

U29A

U28C U

U28AU27CU27B U26CU26BU26A

87654321

CP1CP2

DataSeq

DS1

U23E

U18A

U17C

U17B

U17A

U16C

U16B

U16A

U15C

S

R Q_Q

U12

S

R Q_Q

U9

S

R Q_Q

U7

S

R Q_Q

U5

U23A

U23B

U23C

U23D

4555

A1A0

E Q0Q1Q2Q3

1/2

U25A

U24A

U22A

U21A

U23F

U20C

U20B

U20A

U19C

U19B

U19A

U18C

U18B

S

R Q_Q

U11

S

R Q_Q

U10

S

R Q_Q

U8

S

R Q_Q

U6

U15B

U15A

U14C

U14B

U14A

U13C

U13B

U13A

S

R Q_Q

U4

S

R Q_Q

U3

S

R Q_Q

U2

S

R Q_Q

U1

U24B

U24C

U24D

U24E


28/46

28

Waveform after the simulation of above circuit

LAB 3: DESIGN COUNTERS.

CLK

D0

D1

D2

1180117011601150114011301120


29/46

29

(a)The N-bit binary counter is a device that counts up to 2N. It then resets and counts againfrom zero. Design a four-bit binary counter with J-K flip-flops.

1. INTRODUCTIONCounters are N bits devices which when pulsed counts from0 to 2

N 1, and the process then

repeats. Actually they are the moduloN counters where N is the number of bits and 2N

is the

number of states to be taken by the counter.

The counter will increase by 1 for each input pulse. When the output reaches 2N

1 then

the next state of the circuit will go low, that is the process repeats itself again.

2. DESIGN THEORYThe four bits binary counter is the counter which counts from 0 and adds one to obtain

the next state value up to 241=15 when a pulse is received before reset back to zero and the

process repeats. Since the counter counts from zero, then the counter will have 16 states and four

bits will be involved. The counter will thus have 16 outputs and will be designed using four JK

Flip Flops since four bits will be needed to represent the 16 states effectively.

The following are the design states which are to be followed.

2.1THE STATE DIAGRAM OF THE COUNTER


30/46

30

The counter moves from on state to another when a pulse is issued

2.2THE STATE TABLE OF THE COUNTER FROM THE STATE DIAGRAM ABOVE:

Present State (P.S) Next State (N.S)

S/N S3 S2 S1 S0 Q3 Q2 Q1 Q0

0 0 0 0 0 0 0 0 1

1 0 0 0 1 0 0 1 0

2 0 0 1 0 0 0 1 1

3 0 0 1 1 0 1 0 0

4 0 1 0 0 0 1 0 1

5 0 1 0 1 0 1 1 0

6 0 1 1 0 0 1 1 1

7 0 1 1 1 1 0 0 0

8 1 0 0 0 1 0 0 1


31/46

31

2.3THETRUTH TABLE OF THE COUNTER:

Present State (P.S) Next State (N.S) FF3 FF2 FF1 FF0

S3 S2 S1 S0 Q3 Q2 Q1 Q0 J3 K3 J2 K2 J1 K1 J0 K0

0 0 0 0 0 0 0 1 0 d 0 d 0 d 1 d

0 0 0 1 0 0 1 0 0 d 0 d 1 d d 1

0 0 1 0 0 0 1 1 0 d 0 d d 0 1 d

0 0 1 1 0 1 0 0 0 d 1 d d 1 d 1

0 1 0 0 0 1 0 1 0 d d 0 0 d 1 d

0 1 0 1 0 1 1 0 0 d d 0 1 d d 1

0 1 1 0 0 1 1 1 0 d d 0 d 0 1 d

9 1 0 0 1 1 0 1 0

10 1 0 1 0 1 0 1 1

11 1 0 1 1 1 1 0 0

12 1 1 0 0 1 1 0 1

13 1 1 0 1 1 1 1 0

14 1 1 1 0 1 1 1 1

15 1 1 1 1 0 0 0 0


32/46

32

0 1 1 1 1 0 0 0 1 d d 1 d 1 d 1

1 0 0 0 1 0 0 1 d 0 0 d 0 d 1 d

1 0 0 1 1 0 1 0 d 0 0 d 1 d d 1

1 0 1 0 1 0 1 1 d 0 0 d d 0 1 d

1 0 1 1 1 1 0 0 d 0 1 d d 1 d 1

1 1 0 0 1 1 0 1 d 0 d 0 0 d 1 d

1 1 0 1 1 1 1 0 d 0 d 0 1 d d 1

1 1 1 0 1 1 1 1 d 0 d 0 d 0 1 d

1 1 1 1 0 0 0 0 d 1 d 1 d 1 d 1

2.4 MINIMIZATION USINGK-MAPS

Consider FF3

For input J3 For input K3

J3=S2S1S0 K3=S2S1S0

Consider FF2

S1S0

S3S2

00 01 11 10

00 0 0 0 0

01 0 0 1 0

10 d d d d

11 d d d d

S1S0

S3S2

00 01 11 10

00 d d d d

01 d d d d

10 0 0 1 0

11 0 0 0 0


33/46

33


J2=S1S0

K2=S1S0

Consider FF1


J1=S0

K1=S0

Consider FF0

S1S0

S3S2

00 01

11

10

00 0 0 1 0

01 d d d d

10 d d d d

11 0 0 1 0

S1S0

S3S2

00 01

11

10

00 d d d d

01 0 d 1 0

10 0 0 1 0

11 d d d d

S1S0

S3S2

00 01 11 10

00 0 1 d d

01 0 1 d d

10 0 1 d d

11 0 1 d d

S1S0

S3S2

00 01 11 10

00 d d 1 0

01 d d 1 0

10 d d 1 0

11 d d 1 0


34/46

34


J0=1

K0=1

3. CIRCUIT DIAGRAM AND WAVEFORMS

key5V

CLK

S0S1S2S3

CP1CP2 Q1Q2

CLK

1234

output

SJCPK

R

Q_Q

S0

SJCPK

R

Q_Q

S1

SJCPK

R

Q_Q

S2

SJCPK

R

Q_Q

S3

S1S0

S3S2

00 01 11 10

00 1 d d 1

01 1 d d 1

10 1 d d 1

11 1 d d 1

S1S0

S3S2

00 01 11 10

00 d 1 1 d

01 d 1 1 d

10 d 1 1 d

11 d 1 1 d


35/46

35

4. CONCLUSSION AND RECOMMENDATION

The circuit performs as intended and depicts a modulo 4 counter.


36/46

36

QUESTION 3(b)

Design a divide-by-12 counter that will count (in binary) the number of pulses on the input line.

Use J-K flip-flops.

1. INTRODUCTIONDivide by N counters are the counters which counts up from zero to 2N - 1 then resets to one

and the process then repeats. Actually they are the modulo N counters where N is the

number of bits and 2N states.

The counter will increase by 1 for each input pulse. When the output reaches 2n 1 then

the next state of the circuit will go low. Thus next state becomes zero and the process

repeats itself.

2. DESIGN THEORYTo design a four-bit binary counter, will require 2

Nstates, where N is the maximum number of

bits in the counter. In our case its four bits (specified from the question). Thus we have 24

=16

states in total.

The state will be increasing by 1 for each input pulse. When the output reaches 1011=11(in base

10), the next state would expected to be 1100 but for divide by 12 counter reset the counters i.e.

clears all the registers and starts from 0000 rather than 1100.

Since the counter has 12 states then a total of four JK flip flop are going to be used.


37/46

37

2.1THE STATE DIAGRAM FOR THE COUNTER:

2.2 THE STATE TABLE FOR THE ABOVE STATE DIAGRAM:

Present State (P.S) Next State (N.S)

S/N S3 S2 S1 S0 Q3 Q2 Q1 Q0

0 0 0 0 0 0 0 0 1

1 0 0 0 1 0 0 1 0

2 0 0 1 0 0 0 1 1

3 0 0 1 1 0 1 0 0

4 0 1 0 0 0 1 0 1

5 0 1 0 1 0 1 1 0

6 0 1 1 0 0 1 1 1

7 0 1 1 1 1 0 0 0

8 1 0 0 0 1 0 0 1


38/46

38

2.3THE TRUTH TABLE:

Present State (P.S) Next State (N.S) FF3 FF2 FF1 FF0

S3 S2 S1 S0 Q3 Q2 Q1 Q0 J3 K3 J2 K2 J1 K1 J0 K0

0 0 0 0 0 0 0 1 0 d 0 d 0 d 1 d

0 0 0 1 0 0 1 0 0 d 0 d 1 d d 1

0 0 1 0 0 0 1 1 0 d 0 d d 0 1 d

0 0 1 1 0 1 0 0 0 d 1 d d 1 d 1

0 1 0 0 0 1 0 1 0 d d 0 0 d 1 d

0 1 0 1 0 1 1 0 0 d d 0 1 d d 1

0 1 1 0 0 1 1 1 0 d d 0 d 0 1 d

0 1 1 1 1 0 0 0 1 d d 1 d 1 d 1

9 1 0 0 1 1 0 1 0

10 1 0 1 0 1 0 1 1

11 1 0 1 1 0 0 0 0

12 1 1 0 0 d d d d

13 1 1 0 1 d d d d

14 1 1 1 0 d d d d

15 1 1 1 1 d d d d


39/46

39

1 0 0 0 1 0 0 1 d 0 0 d 0 d 1 d

1 0 0 1 1 0 1 0 d 0 0 d 1 d d 1

1 0 1 0 1 0 1 1 d 0 0 d d 0 1 d

1 0 1 1 0 0 0 0 d 1 0 d d 1 d 1

1 1 0 0 d d d d d d d d d d d d

1 1 0 1 d d d d d d d d d d d d

1 1 1 0 d d d d d d d d d d d d

1 1 1 1 d d d d d d d d d d d d

2.4 MINIMIZATION USINGK-MAPS

Consider FF3


J3=S2S1S0 K3=S1S0

Consider FF2

S1S0

S3S2

00 01 11 10

00 0 0 0 0

01 0 0 1 0

10 d d d d

11 d d d d

S1S0

S3S2

00 0111

10

00 d d d d

01 d d d d

10 d d d d

11 0 0 1 0


40/46

40


J2=S3

S1S0

K2=S1S0

Consider FF1


J1=S0

K1=S0

Consider FF0

S1S0

S3S2

00 01

11

10

00 0 0 1 0

01 d d d d

10 d d d d

11 0 0 0 0

S1S0

S3S2

00 01

11

10

00 d d d d

01 0 0 1 0

10 d d d d

11 d d d d

S1S0

S3S2

00 01 11 10

00 0 1 d d

01 0 1 d d

10 d d d d

11 0 1 d d

S1S0

S3S2

00 01 11 10

00 d d 1 0

01 d d 1 0

10 d d d d

11 d d 1 0


41/46

41


J0=1

K0=1

3. CIRCUIT DIAGRAM AND WAVEFORMS:Circuit diagram

The minimization above with the resulted equations end up in producing the following circuit

diagram:

Simulation and waveforms

V25V

CLK

S0S1S2S3

1234

DISP1

CP1CP2

Q1Q2

CLK

SJCP

KR

Q

_Q

S0

SJCP

KR

Q

_Q

S1

SJCPK

R

Q_Q

S2

SJCPK

R

Q_Q

S3

U2A

S1S0

S3S2

00 01 11 10

00 1 d d 1

01 1 d d 1

10 d d d d

11 1 d d 1

S1S0

S3S2

00 01 11 10

00 d 1 1 d

01 d 1 d d

10 d d d d

11 d 1 1 d


42/46

42

Simulation was done using the circuit maker and after simulation the following waveforms were

obtained.

4. CONCLUSION AND RECOMMENDATION

From the waveform, a delay is observed during the raising edge of a clock to each of the output.

The delay is resulted from the internal gates delay and delays due to the JK flip flop used.

Furthermore, the change of S3 is very much slow i.e. change slowly as compare with the output

S0 which is the fastest, changes once after every two clock pulse (which is twice as much thespeed of output S2 as can be seen from the wave forms ).

LAB4: DESIGNOF SEQUENTIAL CIRCUITS USINGMEMORY CELLS.


43/46

43

Design a synchronous sequential circuit whose inputs are binary levels and that the following

state assignment is used:

Y = 0 A

Y = 1 B

Use Karnaugh maps to find:

(a)The State Table; and(b)The State Diagram.

Hint: Use D Flip-Flop as your memory device.

1. INTRODUCTIONA sequential circuit is the one in which the decisions are made based on combination of the

current input as well as the past history of the inputs, furthermore a synchronous sequential

circuit is the one which is triggered by using clock.

The D flip flop is commonly used in situations where there is feedback from the output backto the input through some other circuitry and this feedback can sometimes cause the flip-flop

to change states more than once per clock cycle. In order to ensure that the flip-flop changes

state just once per clock pulse, we break the feedback loop by constructing a master-slave

flip-flop.

2. DESIGN THEORY2.1STATE DIAGRAM


44/46

44

2.2THE STATE TABLE

PRESENT

STATE

[Q(t)]

NEXT STATE [Q(t+1)]

In=0 In=1

A: 0 A/0 B/1

B:1 B/1 A/0


45/46

45

2.3THE TRUTH TABLE

2.4 THE EXCITATION TABLE

3. K-MAP MINIMIZATION

In Q(t) Q(t+1) OUTPUT(Z)

0 0 0 0

0 1 1 1

1 0 1 1

1 1 0 0

In Q(t) D

0 0 0

0 1 1

1 0 1

1 1 0

Q(t)

In

0 1

0 0 1

1 1 0


46/46

( ) ( )n n

D I Q t I Q t !

1. CIRCUIT DIAGRAM AND WAVEFORMS

The circuit diagram of the synchronous

V1_3

U1B_4

U1A_3

U1A_2

U1A_1

V3_1

U1B_5

U4A_3

L1_1

V35V

U1B

U1A

L1

CP1CP2

Q1Q2

V1

U4A

SD

CP

R

Q_Q

U3A

U2A

larco rrogasian

Documents