laser tracking system (lts) son nguyen jassim alshamali aja armstrongmatt aamold
Post on 22-Dec-2015
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TRANSCRIPT
Laser Tracking System (LTS)
Son NguyenSon Nguyen Jassim Alshamali Jassim Alshamali
Aja ArmstrongAja Armstrong Matt Matt AamoldAamold
Presentation Outline
• CDR Checklist
• Digitization Sub-Systems
• Controls Sub-Systems
• Target Detection
• Project Schedule
Slight Changes to Project
• B/W sampling instead of Color – B/W uses intensity sampling– Color uses phase sampling from the back
porch
• Black background instead of white – Better laser detection
• Two power supplies instead of one
CDR Checklist
• Timing for digitization
• Obtained main schematics
• Functioning servos
• Creating PWM design
• Designing structure
Digitization Sub-System
• Video Frame Timing
• Video Line Timing
• Sync Separator Outputs
• State Machine Diagram
• Timing Counters
• Timing Schematic
Digitization – Video Frame Timing
• Odd/Even Fields
• Not every line in output of NTSC is valid data
• Last line on each field is half line
Digitization – Video Line Timing
63.5 us line time – not all is valid data
B/W is intensity based
Digitization – Sync Separator
Digitization – State Machine
Digitization – Timing Counters
• Counter A – Divides 50Mhz to 12.5Mhz; sampling clock
• Counter B - Throw out invalid lines; starts from line sync; 1,111,250ns @50Mhz = 55,562 cycles
• Counter C – Throw out invalid line data; starts from Counter B; 9.4us @50Mhz = 470 cycles
• Counter D – Sampling counter; starts from Counter C; 640 samples throughout 52.6us; Uses 12.5Mhz clock (Coordinate Counter A)
• Counter E – Keeps track of which line in frame; 242 valid full lines (Coordinate Counter B)
Digitization – Timing Schematic
Controls Sub-System
• Structure Design
• Servo Testing
• Pulse Wave Modulator Design
• Power Supply Design
Controls - Structure
• Rotary Base will serve as the x-axis
• Designs for the y-axis movement are in progress
Controls - Servo Testing
• Dual Timer Chip Used to Implement Hardware PWM
• 50hz Base Signal Required• Changing the duty cycle changes the relative
position of the servo
QuickTime™ and aTIFF (Uncompressed) decompressor
are needed to see this picture.
Controls - Servo Testing
• HiTec HS-50 Servo– Full Counter-Clockwise 4.2% Duty Cycle– Full Clockwise 9.8% Duty Cycle– Center 7.0% Duty Cycle
• Airnotics….Servo– Full Counter-Clockwise 3.2% Duty Cycle– Full Clockwise 9.8% Duty Cycle– Center 5.6% Duty Cycle
Controls - Pulse Wave Modulator Design
• Pulse Wave Modulator (PWM) controls the duty cycle required to move the servos.
• Implementation of the PWM will be on board the FPGA
• Design of PWM will be designed in Verilog
QuickTime™ and aTIFF (Uncompressed) decompressor
are needed to see this picture.
Controls - Pulse Wave Modulator
• PWM consists of several parts– Clock Divider to bring the 50Mhz clock of the
FPGA down to 45hz-55hz for the base frequency of the PWM.
– Verilog code to generate the behavior of a PWM
• Accumulator and registers will be used to adjust the duty cycle of the 45hz-55hz waveform
Controls - Pulse Wave Modulator
• The clock divider was made with flip flops to bring the frequency down to 47hz
QuickTime™ and aTIFF (LZW) decompressor
are needed to see this picture.
Controls - Power Supply Design
• Servos– 9 Volt unregulated transformer
• With a 5 volt regulator
• Digitizing Board– 12-15 Volt unregulated transformer
• With 12 and 5 regulated voltages
Overall Power
• Components– Camera
• 12V * 200 mA = 2.4 Watts
– Servos• Maximum of (9V-5V) * 1A = 4 Watts
– All IC’s will go off of FPGA• FPGA will use a regulated 5V
Target Detection
• Four main state machines
– Target detector
– Choosing mode
– Static mode
– Dynamic mode
State Machine for Target Detector
Project Schedule
Any Questions??