(Layer0) Mechanical Issues + Test-Beams

S. Bettarini

On behalf of the Pisa Group

V Super-B workshop – Paris 9th May 2007

Outline

• Support structure for a baseline striplet L0

• For the APSEL MAPS candidate pixel sensor:– Mechanical/Thermal issues – Prototypes: micro-channel on AlN substrate

• “Looking for” a test-beam facility– The “demonstrator”

• Conclusions

Layer0 striplets R&D issuesTechnology for L0 baseline striplet design well estabilshed– Double sided Si strip detector 200 m thick– Existent redout chip (FSSR2 - BTeV) matches the requirements for striplets

redout with good S/N ~ 25.– Redout speed and efficiency not an issue with the (safety factor x5 included in

the expected background rate)

– Possible reduction in L0 material budget (from 0.45% 0.35% X0) with R&D on the connection between the silicon sensor and the FEE:• Interconnection critical given the high number of readout channels/module

(~3000). Possible choices:– Multiple layers of Upilex with Cu/Au traces with bonding (as in SVT) – Kapton/Al microcables with Tape Automated Bonding (as in ALICE experiment)

Conceptual design module “flat”

Readout RightReadout Left

z

HDI

Si detector 12.9x97.0 mm2 1st fanout, 2nd fanout

HDI

Mechanical constraints & assembling procedures• The Layer0 module must be bent (HDI w.r.t.

sensor plane) to fit inside the radius of the current BaBar Layer1 ( R(L1)=32.5 mm )

• Each hybrid is mounting 6 chips (FSSR2: 7.5 x 5 mm2)

Assembly Procedure:• The module is assembled FLAT (length=284 mm x width=54.5 mm):

• The fanouts are glued on the detand micro-bonded• The DFA is electrically tested and Defects eventually cured• The HDI is connected to the fanouts and bonded

• Using bending masks we rotate the hybrids (using the flexibility of the kapton circuits).

Si det

Fanout estension

HDI

R(L0)=15mm

• Freezing the module into the final geometry by a stiff carbon-fiber/kevlar structure (ribs & end-pieces “a la BaBar”: 0.5 mm thick and 4 mm height)

R(L1)=32.5mm

Module Layer0 (3D-view)

Hybrids

Striplets Si detector(fanout cut-away)

Upilexfanout

Carbon-Kevlar ribs

Endpiece

chip

Buttons(coupling HDI to flanges)

Placing the Layer0 module on the flanges

Semi-circularflanges(cooling circuitinside)

Thermal Conductive wings

Places forButtons

Final Layer 0 structure

r-cross section

3-D view

Layer 0 mounting procedures:

• Mech. tolerances are very tight !• Four modules are first mounted on semi-circular flanges.• The cooling circuit is inside the annular region of the circular flanges, with thermal conductive wings to drain the heat from the hybrids• The two halves are then coupled to wrap the whole structure over the beam pipe cylinder .

Further investigating: • structural and thermal FEA • test on prototypes. There is still some room left for final tuning to optimize/minimize the material (e.g. aluminum micro-cables).

MAPS moduleThermal StudyDesign Requirements

Power Dissipation:• Electronics & sensor integrated

great amount of heat dissipated on the active area.

• Spec’s for the MAPS Layer 0 :

– Power = 210 W / layer (Power = 50 W/cell = 2 W/cm2)

– Electronics Working Temp. range: [0,50] oC

The need to evacuate heat in the sensitive area is driving the mechanical problem.

Viable solutions depending on

• Module Step 0 Double Side.

The possibility of strong reduction of Pixel cell power dissipation ? • Module step 1 Double side.

Low Power scenarioP < 5 uW/channel

P > 5 uW/channel(most-likely scenario)

Cooling heath sink by

Thermal Conduction

Cooling heath sink by Thermal Convection

Sensible Thermal analysis:reduction power dissipation versus material with better thermal conductivity.

•Module Microchannel Double Side.

Module Step 0 Double Sided(Dissipation with Thermal Conduction:)

Cooled Region

• N°2 read-out units (“caterpillar”) composed by 4 chips each , 12.8mm x 12.8mm.

• Two silicon layers (up/down) placed on the mechanical support forming a ladder.

Low Power scenario

Typical DS Module Boundary Conditions

Power: 2 watt/cm2 on each silicon surface

Temperature : Surface between aluminum pipe and AlN substrate @ 10 °C

Geometry: Longitudinal Cross Section

FEA results on Double-Sided (thermal conduction)

How the Tmax temperature changes modifying the power consumption of silicon (AlN substrate180 watt/mK)

• Tmax = 837 °C with 2 watt/cm2

• Tmax = 195 °C with 0.4 watt/cm2 (1/5 of nominal total power)

• Tmax = 103 °C with 0.2 watt/cm2 (1/10 of nominal total power)

And……. modifying the material? (Increasing thermal conductivity)BeO Substrate: (280 watt/mK)

• Tmax = 628 °C with 2 watt/cm2

• Tmax = 134 °C with 0.4 watt/cm2 (1/5 of nominal total power)

• Tmax = 72 °C with 0.2 watt/cm2 (1/10 of nominal total power)

Diamond Substrate: (800 watt/mK)

Tmax = 236 °C with 2 watt/cm2

Tmax = 56 °C with 0.4 watt/cm2 (1/5 of nominal total power)

Tmax = 33 °C with 0.2 watt/cm2 (1/10 of nominal total power = 5uW/ch)

Typical thermal gradient:

Low Power scenario

Module Microchannel Double Sided(Dissipation with Thermal Convection)

Cooled channel

• N°2 read-out units (“caterpillar”) composed by 4 chips each , 12.8mm x 12.8mm.

• Two silicon layers (up/down) placed on the mechanical support forming a ladder.

High Power

Microchannel Module Boundary Conditions

Geometry: Transversal Cross Section

Power: 2 watt/cm2 on each silicon surface

Temperature : Inlet cooling liquid @ 10 °C

AlN-AlN Interface: 50 m of Conductive Glue (4 watt/mK)

High Power

FEA results on Microchannel ModuleTypical results:

Tmax = 11.3 °C with 2 W/cm2 on each sensor surface

The Hydraulic cooling circuit parameters are:

Tinlet = 10 °C

Delta T = 3 °C

Hydraulic diameter = 0. 897 mm

Flow = 0.251 l / min

V (H2O) = 6.6 m/sec

Pressure losses = 1 atm

Reynold number = 5933

If we want to decrease the fluid velocity and pressure losses

we need to accept a bigger T.

Tinlet = 10 °C

Delta T = 8 °C

Hydraulic diameter = 0. 897 mm

Flow = 0.094 l / min

V (H2O) = 2.5 m/sec

Pressure losses = 0.187 atm

Reynold number = 2225

High Power

Remarks• Module without fluid refrigerant possible only with low power

scenario and diamond support structure.• Solutions implying fluid flowing inside the detector needs

pipes on ladders for which the ideal goal support (X0) ~ Si

(X0) is hardly achieved.• Performace OK with a total L0 materia budget <0.5 % X0. .

– micro-channel module 0.41 % X0.

Alternative approach:• the beam pipe tube is a cold source (1 kW cooling system, T=12 °C ) to evacuate the Layer 0 heat. • The external cilinder of the beam pipe used as a support for the Silicon chips. To study: its mechanical /thermal stress due to the passage of the beam (normal modes, etc …).

• Works in progress– Mechanical characterization of 50/150/300 m thick silicon wafer

(bending tests, membrane beahaviour etc.)– AlN material procured (Haldemann & Porret) for microchannel module

prototype – Carbon fibers (M46J) supports arriving (Plyform) for prestress test

• Future works– R&D on Micromachining: laser ablation for Microchannel module– R&D on glueing technology for very low glue thickness– Assembling of AlN microchannel prototype structure with traditional technique – Vibration analysis of the microchannel module prototype– Study on the beam pipe as the L0 support

Ongoing R&D activities

Work in Structural Diagnostic labLoad / deformation diagram

sample 50 m thick (L=42 mm, f=8 mm)

The Silicon sensor

can be shaped as a

cilinder of 64 mm

in diameter!

Test-beam in 2008• In the 2nd half of 2008 MAPS and striplet

detectors ready to be tested on the beam

• Still looking for the best site.

• Test of the whole system, consisting of:– Sensor MAPS – DSSD striplets– Read-out (FSSR2)– DAQ/AM

The “DEMONSTRATOR” (inside the reference telescope)

S1

S2

S3

T-2,1T-4,3

Striplets-1Striplets-2

MAPS-1

MAPS-2

beam

T-1,2,3,4 :reference telescope modules (~2x2 cm2 ) DSSD 300 m thick25 p-side, 50 n-side m pitch50 m r.o. pitch (3 chip FSSR2/side)

S-1,2,3 scintillator (coinc. NIM/TTL outputto the DAQ)

Striplets-1,2:(1.29x7.0 cm2 )DSSD 200 m thick ( 45o)25 p-side, 50 n-side m pitch50 m r.o. pitch (chip FSSR2)

MAPS-1,2 : MAPS (several mm2)50x50 mm2 (50 mm-thick)

Test-beam

Demonstrator

Test-beam purposes• Find the capability rate of the system• Study efficiencies & resolutions vs. track’s incident angle

DAQ architecture

The Associative Memory Boardprovides Level 1 trigger signal to the DAQbased on the hits of the demonstrator:pattern-matching “a la CDF”, tracks found during detector readout.

Conclusions• Provided a working design for the striplet L0

• R&D ongoing for the mechanical/thermal issues of the pixel L0 with the CMOS MAPS sensor. Focus on:– power dissipation – minimize the material

The spec’s of the problem are defined:room for new ideas and mechanical solutions!

• Series of test-beams for the demonstrator (1st starting in summer 2008 and then in 2009)

Looking for the best test-beam facility.

Back-up SLIDES

Layer 0 baseline design

• Module active area = 1.29 x 9.7 cm2 • Double sided detector, 200 um thick, with striplets, (45 degrees w.r.t

det edges), readout pitch 50 um. • strip area = 50 um x 1.83 cm, 3080 strips/module • 770 strips readout on each short side of the module (left/right)

– bring signals outside the active region with traces on a fanout support (as in SVT modules, z side several fanout layers/module depending on pitch

U

V

1.29 cm

9.7 cm

r= 1.5 cm

Readout Right

Readout Left

• Octagonal shape with R=1.5 cm, LAB accept. 300 mrad in FW and BW

50 m

50 m

L~ 9.7 cm

d~

1.2

9 c

m

P side

N side

Pstop to insulate n+ strips or pspray

L_strip ~ 1.83 cm

Front end chip I

• Expected background hit rate = 5 MHz/cm2 @ r=1.5cm– Including x 10 safety factor 50 MHz/cm2 used in the

following

• L0 strip rates (> 450 kHz) are not acceptable with present SVT front end (ATOM chip) :– With 1 s readout window L0 strip occupancy > 45%– Inefficiency due to shadowing: a single hit (the first in the

readout window) is retrieved from the pipeline when LV1 trigger is received background hits can shadow hits from physics

– Such a high occupancy affects pattern recognition

Front end chip II • Try a different approach for readout: fast, data driven readout

architecture, with no analog storage, with enough output bandwidth to ensure that no data is lost due to readout deadtime.

• FSSR2, designed for the BTeV Forward Silicon Tracker (Pavia/Bergamo-Fermilab), has the right features:– Mixed-signal integrated circuit for the readout of silicon strip detectors

(selectable shaper peaking time: 65-85-125 ns)

– TSMC 0.25 µm CMOS tech. with enclosed NMOS Rad. Hard

– 128 analog channels, sparsified digital output with address, timestamp, and pulse height information for all hits

– Architecture designed to run with 132 ns bunch crossing (timestamp granularity = BCO clock = 7.6 MHz), readout clock @ 70 MHz 840 Mb/s output data rate.

– For more details on FSSR2 see for example:• V. Re et al., “FSSR2, a Self-Triggered Low Noise Readout Chip for Silicon Strip

Detectors”, 2005 IEEE Nuclear Science Symposium Conference Record• V. Re: “First prototype of a silicon microstrip detector with the data-driven readout chip

FSSR2 for a tracking-based trigger system” , presented @ 10th Pisa Meeting on Advanced Detectors, La Biodola (Isola d’Elba), May 21 – 27, 2006

FSSR2 for L0 striplets• In SuperB L0 expected FSSR2 chip occupancy (132 ns) =

6%– Should be OK for pattern recognition – Is FSSR2 fast enough for SuperB?– YES, if you believe to simulation performed for BTeV

• FSSR2 chip optimized for BTeV operation:– With 2 interactions/bunch crossing (132 ns), expected BTeV FSSR2

occupancy 2% – With standard operation (132 ns BCO clock) FSSR2 can handle 2%

occupancy with efficiency > 99%.

• FSSR2 Simulation performed for BTeV with 6% occupancy (6 interactions/bunch crossing) indicates: – Efficiency ~ 96.5%, with standard BCO clock frequency – Can improve efficiency (~ 98.5%) with x 4 BCO clock frequency.

• FSSR2 chip can read L0 striplets (6% occupancy) with 98.5% efficiency

Layer 0 S/N with FSSR2

• Assume noise performance as measured in FSSR2: – ENC=a+b*CD

– a=240 e- , b=35 e-/pF

• Serie resistance increases by ~ 14% the slope b:Rs = Lfanout *2 cm + Ldet*20

cm=55 e_n=4kT Rs/3 Equivalent Noise Charge =

600 e-

0

500

1000

1500

2000

0 10 20 30 40 50

tp=65 nstp=85 nstp=125 ns

EN

C [

e r

ms]

CD

[pF]

BLR selected

ENC = 240 + 35 e/ pFENC = 230 + 28 e/ pFENC = 220 + 24 e/ pF

• Signal = 16000 e- (Si 200 um thick)• S/N = 26 ( ~ 24 including 300 e- thr. dispersion

added to noise in quadrature)

CD = 9pF

FSSR2 noise vs det Capacitance

Radiation Hardness• Si detector dose ~ 6.6 Mrad/yr (safety included). Should be

ok (rough estimate of noise contribution due to leakage current ~ 670 e- after 5 years of operation, to be added in quadrature to previous noise figure).

• Chip dose depends on their radial location. – Assuming chip located at radius of ~ 2.4 cm expected chip dose ~ 200 krad/yr OK !

FSSR2 Irradiation with 60Co -rays to a total ionizing dose of 20 Mrad (no bias applied

during irradiation) Chip fully functional after irradiation; noise and charge sensitivity are not

affected Threshold dispersion with BLR selected increases by about 15 % (remains

below the spec value of 500 e rms)

Materials Data Sheet

Material X0 (cm) Density (gr/cm3) K = Termal Cond.(W/ mK) E (kg/mm2) CTE(um/ mK)Si 9.4 2.3 124 11200 5.5Be 35.3 1.8 216 28000 11.5Al 9.0 2.7 210 7000 24.0C.F. 25.0 1.6 160 12400Upilex 28.5 1.4 0,35 300 30.0Al2O3 25.0 4.8 30 35000 8.0Cu 1.4 9.0 386 12000 16.4

H20 36.0 1.0 609x10 -3

AlN 25.0 3.3 180 27600 4.7BeO 35 2.86 280 36000 7.5KX1100 25 2.2 600 - 2.5 600 0.1

We have to look materials for support structure with the following properties:Low CTE, low X0, high K, high tensile modulus E, high temporal stability.Important to use materials with similar CTE to reduce bimetallic effect.

ResolutionintrinsicDUT= (residuals

2 - extr.track2 - MSonDUT

2)1/2

D=500 mm, d=10 mm, P()=15 GeV, Si(DUT)=300 m,

x/y =25 m/sqrt(12)=7.2 m= intrinsic

<>MS= 4 x 10-5 rad

residuals = 8.8 m

extr.track = 3.6 m

MSonDUT= 3.6 m

Line Fit to the hits of the telescope(w/o DUT)

hit

250 mm

residual

DUT

Event Display (50 tracks)