layout of the osmosis optical switch controller board using expedition
DESCRIPTION
Layout of the OSMOSIS Optical Switch Controller Board using Expedition. or IS hindsight nearly always 20/20 … ?. Outline. OSMOSIS Project Design Entry Board Structure, Materials Signals, Rules, Constraints 1 st Approach 2 nd Approach 3 rd Approach “Final” Approach Conclusion. - PowerPoint PPT PresentationTRANSCRIPT
Layout of the OSMOSIS Optical Switch Controller Board using Expedition
or
IS hindsight nearly always 20/20 … ?
pdi, Layout of the OSMOSIS OSCB, May 2006
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Outline
OSMOSIS Project Design Entry Board Structure, Materials Signals, Rules, Constraints 1st Approach 2nd Approach 3rd Approach “Final” Approach Conclusion
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Design Entry
.
.
.
8 FPGA Designs
I/O Designer
DesignView
HyperLynx
PreLayoutSimulations
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OSCB Chassis
Test chassis with apre-version of the OSCB Board
Pre-OSCB
OSCI Interface Cards
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Size: 431.8 x 573mm (17" x 22.5")- fits into a 19" chassis
each slot connector has 125 pins single ended, 120 diff pin pairs; total of 285 signal pins
1 FPGA, 1020 pins
7 FPGAs, 1704 pins
40 Slot connectors 20 on front 20 on back
OSCB Board
3644 Components
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OSCB
View from Top
Use Blind Vias
Connector Fanout Problem
1.8
mm
Blocked Routing Channels
Half Board Thickness2.0mm minimum (78mils) (16 Layers)
Free Routing Channels
OSCI Conn
OSCI Conn
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12 Rows of signal pins
min 12 internal layers
(outer layers not used)
• ≥ 16 signal layers
1704 pin FPGA (Xilinx FF1704 Package)
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High speed design requirements
12954 Nets— 4072 diff pairs (clocks + data)— 5000 single ended
Clock frequency: 125MHz, 156MHz I/O Technology used:
- LVPECL Master Clock- LVDS Data, Clk, Sync- LVCMOS Control, uncritical signals
Impedances:- LVPECL 100 Ω balanced- LVDS 100 Ω balanced- LVCMOS 60..70 Ω single ended
Long Wires: up to 750mm (30")
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S1,HS2,V
S3,H
S4,V
S5,HS6,V
S7,H
S8,V
Board Structure 16s16p
B.C. Plane, (high . Plane, (high εεr)r)
B.C. Plane, (high . Plane, (high εεr)r)
"LoFlow" Prepreg
Hal
f B
oar
d T
hic
knes
s ~
2.3m
m (
90m
ils)
Blind Via 1-16
Thru Via, Drill: 0.45mm (18mil)Aspect Ratio 1:10
Blind Via 1-16, Drill: 0.2mm (8mil)Aspect Ratio 1:11Thru Via
+3.3V
GND
GND
GND
GND
GND
GND+2.5V
+1.5V
ExcessiveMaterial
Danger!
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Isola IS620
Low Dielectric Loss: <0.01 @ 2..10GHz (FR4: 0.02)
Low Permitivity: εr = 3.5 @ 1GHz(FR4: 4.4)
Low vertical CTE: 40ppm/ºC(FR4: 175ppm/ºC)Lower risk of torn vias!
Cost: ~3x FR4 (“moderate”) FR4 compatible, but process parameter tuning
required
Board Material
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Rules / Constraints
Done in CES:- 86 Signal Classes- 1 additional Scheme for BGA Areas- 7 Clearance Rules for Netclasses
General Rules Trackwidth (60..70 Ω):Track Width outer: 200 μm (8 mils),
inner: 150 μm (6 mils) Track-to-Track outer: 200 μm (8 mils),
inner: 100 μm (4 mils) Diff Pairs on inner Layers (100 Ω):
100-140-100, 100-115-100 (μm)
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Wiring challenge
Each star consists of ~900 Signals
Exception:Local diff pair wiring
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Challenges
Board Manufacturing:- Size alone not a problem, but...- 100μm Structures alone not a problem, but…- 32 Layers alone not a problem, but…- IS620 alone not a problem, but… All together, - can that be done at all?
Wiring:- 12900 Signals is much, but… 4000 Diff Pairs is incredibly much! but… most of these pairs wired in global stars
This is going to be tough!
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1st Approach
PlacementTop: all major compsBottom: "Chickenfood"
Top Bottom
"Standard" routingmethod:- PWR/GND- Critical Signals-
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1st Approach - Observations (1)
- 6 week effort Only 80% completion (still 1500 opens!)
- manual completion not feasible
need breakthrough!
- Autorouter takes looong (days!)
Almost impossible to do test runs
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1st Approach - Observations (2)
Autorouter cannot convert blind vias into thru vias: poor FPGA fanout
Manually add thru vias under the inner 4 rows of signal pins
Thru Via (1 btw)Blind Via (1-16)
(2 between)
4 inner rows
8 outer rows
Blind Via (1-16)(2 between)
12 rows
Power Supply
Thru Via
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Autorouter cannot connect a diff pair to different vias
Manually convert blind vias to thru vias, where necessary
blind vias
thru vias
Diff Pairs
1st Approach - Observations (3)
Autorouter does not know fences (hard or soft)
"Workaround":Use route obstructs to guide router
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1st Approach - Observations (4)
Question of an expert: Why are all FPGAs on the same side?
Discussion with manufacturer: FPGAs on both sides can be done
place 4 FPGAs on top side and
4 FPGAs on bottom side
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2nd Approach
New FPGA placement – 4 on top, 4 on bottom
Rewire from scratch - except master CLK and supply
(0v2, 10sep05)
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2nd Approach - Observations (1)
Much better results!(still ~1000 opens)
Did not solve the problem, Need breakthrough!
Asked Mike Bare from Mentor Graphics:Are we doing something wrong?
No principal mistakes, approach seems to be OK. settings seem to be OK.
Asked US top PCB „Guru“: Can this board be done?
Feasible; forget autorouter! Would do it manually, would need only 12 layers, would take 3 months – too late!
MG Switzerland runs an autorouter test without diff pair definition (all signals single ended)
99.8% Completion! 15 opens finished manually in under 1 hour
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2nd Approach - Observations (3)
Congestion in the top connector area:Wide single ended bus causes partial blockage of diff pairs
Conclusion: Turn top daughtercard slots 180º
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2nd Approach - Observations (4)
On the edge of despair…
Expedition very, very slow - e.g. „Save“ takes about 10 minutes - e.g. move and drop a simple component (e.g. Cap) can take 10-15 seconds - 2GB of memory not sufficient crashes - Routing passes can take several days - CES seems to extremely slow down Expedition
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3rd Approach
Turn top daughtercard section 180º
Buy new PC- Athlon 64 X2 Dual Core 4800+- 4GB Memory- Latest MB technology
Rewire from scratch (except power supplies)
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3rd Approach - Observations (1)
Further improvement???? opens
Still not the final solution, Need breakthrough!!!
Too many open diff pairs after autoroute:Router seems to have real difficulties with diff pair fanout out of the BGAs
No immediate solution, Manually place 2 diff vias individually!
Difficult / often impossible to place a diff pair of vias, even if there is enough space
Even with new PC:Slow performance still almost unbearable
Use ExtremePCB and ExtremeAR!
No immediate solution, Manual routing! Mostly easy!
Measure: Use 4 more layers
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4th Approach – Add 4 more layers(possible without changing board thickness)
S1,HS2,V
S3,H
S4,V
S5,HS6,V
S7,H
S8,V
S1,HS2,V
S3,H
S4,V
S5,HS6,V
S7,HS8,V
S9,HS10,V
20s16p16s16p
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4th Approach
Use 4 more layers
Install XtremePCB,setup server + 2 client sessions, and
Add one more person
Install XtremeAR setup server + 3 client processes
Remove CESCES slows down Expedition even more with the new pre-release required for running XtremeAR
Rewire from scratch
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4th Approach – Use LDIR
Vertical layers are more utilized,especially 5 inner PFGAs need more vertical routing space
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- All PWR / GND- Flow Control Bus (single ended)- Master Clock (DP) and Sync Signals (SE),
tuning, manual clean-up
- Diff Pairs:Partial route (per FPGA)
1) route opposite side - force thru vias
2) route FPGA side - force blind vias
3) route both sides
4) manual Clean-Up
4th Approach – Routing Method (1)
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4th Approach – Routing Method (2)
- Repeat Partial Routing / Clean-up...
- Single Ended Signals- Tuning- DRC- Clean-Up- DRC- Generate Data
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• Supply all done
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• Flow Control Bus
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• Flow Control Bus
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• Flow Control Bus • Global Sync Signals
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• Flow Control Bus • Global Sync Signals
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• Flow Control Bus • Global Sync Signals • Master Clock (Diff Pairs)
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• Flow Control Bus • Global Sync Signals • Master Clock (Diff Pairs)
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• Flow Control Bus • Global Sync Signals • Master Clock (Diff Pairs) • Local Diff Pairs (1)
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• Flow Control Bus • Global Sync Signals • Master Clock (Diff Pairs) • Local Diff Pairs (1)
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• Flow Control Bus • Global Sync Signals • Master Clock (Diff Pairs) • Local Diff Pairs (1) • Local Diff Pairs (2)
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• Flow Control Bus • Global Sync Signals • Master Clock (Diff Pairs) • Local Diff Pairs (1) • Local Diff Pairs (2)
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• Flow Control Bus • Global Sync Signals • Master Clock (Diff Pairs) • Local Diff Pairs (1) • Local Diff Pairs (2) • Global Diff Pairs (1)
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• Flow Control Bus • Global Sync Signals • Master Clock (Diff Pairs) • Local Diff Pairs (1) • Local Diff Pairs (2) • Global Diff Pairs (1)
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• Flow Control Bus • Global Sync Signals • Master Clock (Diff Pairs) • Local Diff Pairs (1) • Local Diff Pairs (2) • Global Diff Pairs (1) • Global Diff Pairs (2)
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• Flow Control Bus • Global Sync Signals • Master Clock (Diff Pairs) • Local Diff Pairs (1) • Local Diff Pairs (2) • Global Diff Pairs (1) • Global Diff Pairs (2)
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• Flow Control Bus • Global Sync Signals • Master Clock (Diff Pairs) • Local Diff Pairs (1) • Local Diff Pairs (2) • Global Diff Pairs (1) • Global Diff Pairs (2) • Global Diff Pairs (3)
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• Flow Control Bus • Global Sync Signals • Master Clock (Diff Pairs) • Local Diff Pairs (1) • Local Diff Pairs (2) • Global Diff Pairs (1) • Global Diff Pairs (2) • Global Diff Pairs (3)
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• Flow Control Bus • Global Sync Signals • Master Clock (Diff Pairs) • Local Diff Pairs (1) • Local Diff Pairs (2) • Global Diff Pairs (1) • Global Diff Pairs (2) • Global Diff Pairs (3) • Global Diff Pairs (4)
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• Flow Control Bus • Global Sync Signals • Master Clock (Diff Pairs) • Local Diff Pairs (1) • Local Diff Pairs (2) • Global Diff Pairs (1) • Global Diff Pairs (2) • Global Diff Pairs (3) • Global Diff Pairs (4)
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• Flow Control Bus • Global Sync Signals • Master Clock (Diff Pairs) • Local Diff Pairs (1) • Local Diff Pairs (2) • Global Diff Pairs (1) • Global Diff Pairs (2) • Global Diff Pairs (3) • Global Diff Pairs (4) • Global Diff Pairs (5)
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• Flow Control Bus • Global Sync Signals • Master Clock (Diff Pairs) • Local Diff Pairs (1) • Local Diff Pairs (2) • Global Diff Pairs (1) • Global Diff Pairs (2) • Global Diff Pairs (3) • Global Diff Pairs (4) • Global Diff Pairs (5)
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• Flow Control Bus • Global Sync Signals • Master Clock (Diff Pairs) • Local Diff Pairs (1) • Local Diff Pairs (2) • Global Diff Pairs (1) • Global Diff Pairs (2) • Global Diff Pairs (3) • Global Diff Pairs (4) • Global Diff Pairs (5) • Single Ended (1)
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• Flow Control Bus • Global Sync Signals • Master Clock (Diff Pairs) • Local Diff Pairs (1) • Local Diff Pairs (2) • Global Diff Pairs (1) • Global Diff Pairs (2) • Global Diff Pairs (3) • Global Diff Pairs (4) • Global Diff Pairs (5) • Single Ended (1)
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• Flow Control Bus • Global Sync Signals • Master Clock (Diff Pairs) • Local Diff Pairs (1) • Local Diff Pairs (2) • Global Diff Pairs (1) • Global Diff Pairs (2) • Global Diff Pairs (3) • Global Diff Pairs (4) • Global Diff Pairs (5) • Single Ended (1) • Single Ended (2)
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• Flow Control Bus • Global Sync Signals • Master Clock (Diff Pairs) • Local Diff Pairs (1) • Local Diff Pairs (2) • Global Diff Pairs (1) • Global Diff Pairs (2) • Global Diff Pairs (3) • Global Diff Pairs (4) • Global Diff Pairs (5) • Single Ended (1) • Single Ended (2)
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• Flow Control Bus • Global Sync Signals • Master Clock (Diff Pairs) • Local Diff Pairs (1) • Local Diff Pairs (2) • Global Diff Pairs (1) • Global Diff Pairs (2) • Global Diff Pairs (3) • Global Diff Pairs (4) • Global Diff Pairs (5) • Single Ended (1) • Single Ended (2) • Tuning, Clean-Up
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4th Approach – Observations (1)
Marginal improvement of routing results
- Further improvement of placement to free routing channels
Now we have quick feedback, Can do router test runs!
- Routing passes take now hours (instead of days)
Can be easily completed manually in most cases!
- Beyond 90% completion autorouter leaves more and more nets (DPs!) open
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4th Approach – Observations (2)
Tedious manual repair- Router introduces many diff pair separations
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4th Approach – Observations (3)
Tedious manual repair- Odd FPGA routing
Partial blockage
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4th Approach – Observations (4)
Still not the final solution- Further improvement
Fallback Solution: Partial wiring
97.7% completion (672 opens!) – after manual effort
- Time has now become the determining factor! manufacturing deadline
Design does not fully meet requirements reduced performance
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Board Statistics
Parts Placed: 3643 Pins: 42142 Nets: 12954 Differential Pairs: 4072 Connections: 29246
Routed: 97.7% (672 Opens) Total Trace Length: 2.59 km (1.6 miles) Parts Placed: 3643 Total plated holes: 50987
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Tools Used
I/O Designer
Hyperlynx (pre Layout Simulation)
DesignView
CES
Expedition
Hyperlynx(Post Layout Simulation)
Xtreme
1 2 3 4
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Overall Results (1)
Our approach seems to be OK, no obvious mistakes
Extra four layers (due to poor router performance): Symptom treatment, not fix! caused additional manufacturing problems
CES performance inadequate!Especially for large designs, where CES is really needed, it becomes almost unusable
Xtreme AR brought breakthrough!
Outstanding support from MG Switzerland!
Bare in Mind: According to MG this is one of themost complex and demanding designs at the time
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Overall Results (2)
Router has difficulties with diff pair fanout of large BGAs, many opens can easily be routed manually- Our view: Diff pair fanout of large BGAs not
solved
Router introduces separated diff pairs
Lack of router control, e.g.- cost factors, - x/y vs. orthogonal routing,- control script,- fences (hard and soft)
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Overall Results (3)
No "Advanced Fanout":- Fanout traces and vias should be flagged accordingly and considered part of device, even after device is placed
much less hassle when large device with fanout needs to be moved/pushed
Spread doesn't seem to work properly with diff pairs
Too much hidden automatism,should be left to the user when to use auto functions
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Oh, by the Way - Some (Personal) Insights
The answer is: Yes, almost always!
When changing over to a new PCB tool – better don't start with a design such as this one!
For designs like this: There is no quick solution!
OSCB design brought tools to the limits - BUT – to make things clear – OSCB is an exception
- Tool supports newest technology - Mentor Graphics is committed to do their part