lbnl michal szelezniak, eric anderssen, leo greiner, thorsten stezelberger, joe silber, xiangming...

LBNLMichal Szelezniak, Eric Anderssen, Leo

Greiner, Thorsten Stezelberger, Joe Silber, Xiangming Sun, Chinh Vu, Howard Wieman

UTAJerry Hoffman, Jo Schambach

IPHCMarc Winter CMOS group

STAR PXL DetectorSensor Cable Development

September 6-9, 2011 ,Mont Sainte Odile, France

Workshop on system integration of highly granular and thin vertex detectors

Workshop on system integration of highly granular and thin vertex detectorsSeptember 6-9, 2011, Mont Sainte Odile

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Michal Szelezniak

• Introduction• PXL ladder characteristics• Cable development plan• Infrastructure testing board• Testing parameters• Testing results• Summary

Outline


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Michal Szelezniak

Mechanical support with kinematic mounts (insertion side)

Insertion from one side2 layers5 sectors / half (10 sectors total)4 ladders/sector

MAPSRDObuffers/drivers

4-layer kapton cable with aluminium tracesAluminum conductor Ladder Flex Cable

Ladder with 10 MAPS sensors (~ 2×2 cm each)

carbon fiber sector tubes (~ 200µm thick)

20 cm

PXL detector mechanical design


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Michal Szelezniak

PXL electrical connection diagram

10 parallel systems, each composed of:• 4 ladders (1 sector)• Mass Termination Board• Readout board


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Michal Szelezniak

cable bundle

drivers

pixel chips

adhesive

wire bonds

capacitors

adhesivecomposite backer

kapton flex cable

Signal # of traces type Width (0.005” t&s)

Sensor output (PH-2)Sensor output (Ultimate)

10 x 4 x 2 = 8010 x 2 x 2 = 40

LVDSLVDS

0.800” (20.32 mm)0.400” (10.16 mm)

CLK 2 LVDS 0.020” (0.51 mm)CLK_RETURN* 2 LVDS 0.020” (0.51 mm)Marker* 2 LVDS 0.020” (0.51 mm)START (PH-2)START (Ultimate)

12

CMOSLVDS

0.010” (0.25 mm)0.020” (0.51 mm)

SPEAK* 1 CMOS 0.010” (0.25 mm)JTAG + RSTB* 5 CMOS 0.050” (1.27 mm)TEMP 2 analog 0.020” (0.51 mm)Total (Phase-2)Total (Ultimate production)

9552

0.950” (24.14 mm)0.520” (13.22 mm)

PXL ladder and cable

Ladder composition:

Signal count on the cable for 2 generations of PXL sensors:

Phase-1 – challenging

Ultimate – a bit easier

*- signals required for prototyping and testing but not on final production boards.


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• 2 layer Al conductor cable with vias in low mass region• 0.004” (100 µm) traces and 0.004” (100 µm) spaces• 70% fill factor• Conductor thickness in low mass region is 21 µm (Cu) or 32 µm (Al)• Kapton thickness is 25 µm.• Bond wire connection between Al and Cu cable sections.• Cable size is approximately 2.3 cm x 28 cm.

Low mass region calculated X0 for Al conductor = 0.073 %Low mass region calculated X0 for Cu conductor = 0.232 %

Preliminary Design: Hybrid Copper / Aluminum conductor flex cableCurrent goal of cable development


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Michal Szelezniak

1. Infrastructure testing board (ITB)

Evaluate general design of running 10 sensors on a ladder

Find and test the working envelope of bypass capacitance and power supply and ground connections

2. Prototype detector cable – FR-4 with Cu traces

Correct size and the same layout geometry as the final cable

attempt to have the thickness of the Cu layer mimic the final cable to give the correct power and ground impedances

testing of this cable via digital output only

3. Prototype detector cable – Kapton with Cu traces

direct translation of the previous stage cable into a Kapton flex cable

4. Prototype detector cable – Kapton with Al traces

PXL cable development plan


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Michal Szelezniak

Infrastructure Testing Board (ITB)

Analog readout - one sensor at a time Jumper selectable power source to each individual sensor In series replaceable resistor for each sensor power supply (analog and digital) Removable board level capacitor bypassing Removable individual sensor capacitor bypassing Readout over 2 m fine wire as per final ladders Readout through the full HFT data path including MTB, 160 MHz LVDS CLK All buffering and drivers use the same chips as the final ladder First prototype with full-thickness Phase-1, the second prototype with 50 µm Phase-2

• Phase-1 (Phase-2) sensor

Phase-1 prototype Reticle size (~ 4 cm²)

Pixel pitch 30 μm ~ 410 k pixels

Column parallel readout Column discriminators Binary readout of all pixels Data multiplexed onto 4 LVDS outputs @ 160 MHz Integration time 640 μs

Phase-2 prototype Small mask adjustments to improve discriminator

threshold dispersion

ITB with 10 sensors (Phase-1, 2)


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ITB layout

Configuration Jumpers

Analog readout buffers

(9× Phase-1, 1× Phase-2)

Ladder-like layout except for Power and GND


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Test parameters

Sensor characterization – fit threshold scan data to the error function

Faulty columnFaulty column

Noise

FPN

σ distribution µ distribution


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Michal Szelezniak

Testing conditions

Data labels used

Testing condition

ref each sensor measured individually, other sensors OFF

3.3 V Default voltage

3.0 V Reduced voltage

5_Ohm Additional resistance between the ITB power supply and each of the sensors

C34_35 Half of VDA and VDD small bypassing capacitors

C32-25 no VDA, VDD small capacitors

0.5xC Reduced number of VCLP capacitors

0xC no VCLP capacitors near sensors

BUS Bus type power distribution; 2 buses: VDA, VDD

1PWR Two buses connected together, single power supply

(low activity)* Low switching activity: all sensors’ thresholds set high, at 250 DAC

(high activity) High switching activity: each sensor was configured for zero threshold

NOTE: progressive capacitor removal (top-to-bottom)* A Phase-1-based PXL prototype would operate at <300 hits per sensor (inner layer)


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Testing results – temperature

average ITB temperature profile observed consistently throughout the test (results from the characteristics of the cooling system)

15

17

19

21

23

25

27

29

31

33

0 2 4 6 8 10

sensor #

aver

age

tem

per

autr

e (d

eg. C

)

Sensor performance is independent of temperature in this range


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Michal SzelezniakTesting results – noise in the digital readout

Average noise and FPN extracted from threshold scan measurements FPN data marked with * excludes the first two sensors in the chain Error bars - standard deviation (σ) of the noise distribution.

0

0.2

0.4

0.6

0.8

1

1.2

1.4

3.0V 5_Ohm C34_35 C32-35 0.5xC 0xC BUS REV 1PWR

test setup

aver

age

no

ise,

FP

N (

mV

)

noise (limited activity) FPN (limited activity) FPN (limited activity)*

noise (switching) FPN (switching) FPN (switching)*


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Noise performance

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

0 1 2 3 4 5 6 7 8 9 10

sensor #

no

ise

(mV

) 3.3 V

5 Ohm

C32-35

0xC

BUS

Low switching activity


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Michal Szelezniak

Fixed pattern noise

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

0 1 2 3 4 5 6 7 8 9 10

sensor #

FP

N (

mV

)

3.3 V

5 Ohm

C32-35

0xC

BUS

Low switching activity


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Michal Szelezniak

Analog output test results

15

17

19

21

23

25

27

29

test setup

aver

age

EN

C (

e-)

2

2.5

3

3.5

4

4.5

5

5.5

6

ref

3.3V

3.0V

3.0V

*

5 Ohm

C34,3

5

C32-3

50.

5 C

0.5

C R

NO_C BUS

BUS_REV

aver

age

no

ise

(AD

C)

15

17

19

21

23

25

27

29

reduced activity full activity


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Michal Szelezniak

Summary

Phase-1 sensor performance appears independent of the number of high-frequency decoupling capacitors on the board (confirmed by analog and digital readout)

Unaffected performance after removing all small capacitors associated with VDD, VDA and VCLP voltages.

Test results obtained from threshold scans suggest that the bus-type power distribution provides, on average, a slightly better noise performance but with an increased FPN. Both effects are within 10-20 % and with the damaged sensor readout and limited testing capabilities can not be considered accurate.

ITB equipped with 50 µm Phase-2 sensors is under test

Stage 2 – FR4 prototype cable is in the design phase for the PXL production sensor (Ultimate)


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Backup slides


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Michal Szelezniak

PXL grounding plan

lbnl michal szelezniak, eric anderssen, leo greiner, thorsten stezelberger, joe silber, xiangming...

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