LC3 controlState GraphsCompleteness and conflict issuesCreating transition tables and next state equations

from state graphsSequence detectors One-hot encodingCascaded countersUARTAsynchronous inputs

Review for Exam 3

LC3-The Fetch Cycle

1. MAR PC

2. MDR Memory[MAR]

PC PC+1

3. IR MDR

Fetch0

Fetch1

Fetch2

enaPCldMAR

enaMDRldIR

selMDR = 1 ldMDRselPC=00ldPC

Counters and Other Finite State Machines

For counters, the state encodings are usually significant

7SegmentDecoder

Q0

Q2

Q3

Q1

00000001

0010

0011

01000101

0110

0111

1000

1001

For general purpose FSMs, the encoding ofthe states is usually not significant

For example, in the following state graph, the Encodings of the state are irrelevant

…Event 1Event 2Event 1

Event 2 Event 3

State Graphs for Counters with Inputs

The INC signal determineswhether or not to transition to the next state

Completeness Issues

This state graph is not complete. Why not?

What happens in state ’10’ when INC’ occurs?

Completeness Issues

In order for a state graph to be complete:

• It must completely specify the FSM

• Paths leaving a state must specify all POSSIBLE cases

To check for completeness, OR together all of the exiting paths.If the result is “1” then the design is complete.

Conflict Issues

This state graph is not conflict free. Why not?

What happens in state ’10’ when CLR and INC occur simultaneously?

In order for a state graph to be conflict free:

• It must completely specify the FSM

•For a given set of input conditions, the transition from a state must be unique

To check for conflicts, AND together all pairs of the exiting paths. If the result is “0” for all pairs, the design has no conflicting transitions.

Conflict Issues

Creating transition tables and next state equations from state graphs

The resulting next state and output equations are:

N1 = Q0 + Q1 TDONE’ N0 = TOKEN Q1’ Q0’ CLRT = Q0 SPRAY = Q1

This is a sequence detector. It has 1 input – ‘Xin’.It detects the sequence 0..1..1 on the input. When detected, the output signal ‘Z’ is asserted.

As long as ‘Xin’ is a ‘1’ we stay in state S0.

1..1..1..1..

When we detect a ‘0’ we move to state S1.

1..1..1..1..0..

As long as ‘Xin’ is a ‘0’ we stay in state S1.

1..1..1..1..0..0..0..0..

When we detect a ‘1’ we move to state S2.

1..1..1..1..0..0..0..0..1..

If the next value of ‘Xin’ is a ‘1’ we move to state S3.

1..1..1..1..0..0..0..0..1..1 We have found the sequence 0..1..1 so we also assert the output ‘Z’. We are done!

But what if the next value of ‘Xin’ is a ‘0’?

1..1..1..1..0..0..0..0..1..0.. We move back to state S1 to wait for the next ‘1’.

Problems

This machine is only useful for detecting the 1st

occurrence of the pattern 0..1..1. After that, itsimply loops at state S3 forever while asserting

the ‘Z’ output.

Here is a modified version

It detects an occurrenceof the pattern, asserts the output ‘Z’ for oneclock cycle and then goeson to look for the nextoccurrence of the pattern

Note: when transitioningfrom state S3, a ‘0’ sendsthe machine to state S1 while a ‘1’ sends it to stateS0.

A Mealy Version of the Detector

The major difference is that the output ‘Z’is asserted on thetransition ‘Xin’ fromstate S2.

It is a Mealy machinebecause the output is a function of the currentstate and the input.

A Mealy machine often allows a reduction in thenumber of states necessary to implement a machine.Here is a machine which does the same function.

One-Hot EncodingOne-Hot encoding has the following characteristics:

– There is one flip flop for each state

– Only one state bit can be high at a time

– One state bit must always be high

– It uses more flip flops than dense encodings

– Tradeoff is that input forming logic and output forming logic are usually much

smaller and simpler.

StateA 1 0 0B 0 1 0C 0 0 1

Encoding

Take for example the following state graph

a’

ab’c

b’c’

b

A

B

C

State Encoding and Structure

D Q AA+

D Q BB+

D Q CC+

StateA 1 0 0B 0 1 0C 0 0 1

Encoding

With one-hot encoding, each state has its own flip flop.

Note: ‘A’ is the name of a state. It is also the name of the wire coming out from the flip flop for state ‘A’.

The same holds true for states ‘B’ and ‘C’

One Hot Encodings

• IFL and OFL can usually be created via inspection– Each state bit can be done separately from

the others– Lots of don’t cares lead to simple solutions

By inspection we can see:a’

ab’c

b’c’

b

A

BC

One Hot Encodings

• IFL and OFL can usually be created via inspection– Each state bit can be done separately from

the others– Lots of don’t cares lead to simple solutions

By inspection we can see:A+ = a’A + b’cB + C

a’

ab’c

b’c’

b

A

BC

One Hot Encodings

• IFL and OFL can usually be created via inspection– Each state bit can be done separately from

the others– Lots of don’t cares lead to simple solutions

By inspection we can see:A+ = a’A + b’cB + CB+ = aA + b’c’B

a’

ab’c

b’c’

b

A

BC

One Hot Encodings

• IFL and OFL can usually be created via inspection– Each state bit can be done separately from

the others– Lots of don’t cares lead to simple solutions

By inspection we can see:A+ = a’A + b’cB + CB+ = aA + b’c’BC+ = bB

a’

ab’c

b’c’

b

A

BC

Cascaded Counters

Mod4 Counter

2

INC=‘1’

Rollover0

Digit0

CLR

Mod4 Counter

2

Rollover1

Digit1

CLR

clk1 clk

‘1’

clk

Digit0 2 0

Clk1(Rollover0)

3

Digit1 1 2

1 2

Sequence should be: …-12-13-20-21-22-23-30-…

but we get: …-12-23-20-21-22-33-30-…

?????

DO NOT TIE CLKinputs on modulesto anything but the clock !!!!!!

Even if you tinker untilyou get the right countsequence, you mustguarantee that signalRollover0 has no hazards

Digit0 transition from 1-2 makes this difficult if not impossible

Another Common Ripple Counter

CLK

T Q Q’

‘1’T Q Q’

‘1’T Q Q’

‘1’T Q Q’

‘1’

Q3 Q2 Q1 Q0

Sequence is:

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000

So what is the problem?

Timing Diagram

clk

Q0

Q1

Q2

Q3

Q0 changes in response to clock edge

Only after it changes does Q1’s FF get a clock

Only after that does Q2’s FF get a clock

Net effect is that all the FF’s change at different times

Logic depending on Q3 has very little timeto react before next clock edge

Do Not Use Asynchronous or Ripple Counters

CLK

T Q Q’

‘1’T Q Q’

‘1’T Q Q’

‘1’T Q Q’

‘1’

Q3 Q2 Q1 Q0

Mod4 Counter

2

INC=‘1’

Rollover0

Digit0

CLR

Mod4 Counter

2

Rollover1

Digit1

CLR

clk1

clk

‘1’

D Q

D Q

IFL

Inc

TerminalCount

RollOver

CountValue

The right way!

Clr

A Mod4 Counter

A Dataflow MUX – Version 1module mux21(q, sel, a, b);

input sel, a, b;output q;

assign q = (~sel & a) | (sel & b); ]endmodule

Much simpler, less typing, familiar C-like syntax.Synthesizer turns it into optimized gate-level design.

A Dataflow MUX – Version 2

module mux21(q, sel, a, b);input sel, a, b;output q;

assign q = sel?b:a; endmodule

Even simpler, uses C-like ?: construct

A Dataflow MUX – Multi-Bitmodule mux21(q, sel, a, b);

input sel;input[15:0] a, b;output[15:0] q;

assign q = sel?b:a; endmodule

Same assignment statement works for multi-bit wires as for 1-bit wires.Key Ideas: The predicate must evaluate to true or false (1 or 0) The parts getting assigned must be proper widths.

2:1Mux

16

16

16

a

b

sel

q

1

0

A Dataflow MUX – Multi-Bit

module mux21(q, sel, a, b, c, d);input sel;input[15:0] a, b;output[15:0] q;

assign q = (sel==0)?a: (sel==1)?b: (sel==2)?c:d;endmodule

16

1616

a

b

sel

q01

00

16

16

c

d 11

104:1Mux

2

1

Mark

Space

Line idling Start bit

7 data bits

Parity bit Stop bit

Line idling again

UART Character Transmission

Mark

Space

7 data bits – Least significant bit firstParity bit(odd parity)

1 1 0 1 0 1 0

The letter ‘W’ (1010111)

Mark

Space

UART Character Reception

Receiver should sample in middle of bits

Start bit says a character is coming

Receiver can use a timer (counter) to time when it samples

Mark

Space

UART Character Reception

If receiver samples too quickly, see what happens…

Mark

Space

UART Character Reception

If receiver samples too slowly, see what happens…

Receiver resynchronizes every time a new start bit arrives.Only has to be accurate enough to receive 8-9 bits

UART Receiving

• Receiver checks to see if stop bit is there when it expects at end of character– If not, reports framing error to host CPU

• New start bit can appear immediately after stop bit– Receiver will re-synchronize on start bit

TransmitterState

Machine

Parity Generator

Mod 10Counter

ShiftRegister

300 HZCounter

Send

ParitySelect

300Hz

Din

ParityBit

Load

Shift

Dout

EnableCounter

Count=10Increment

7

Busy

Transmitter Block Diagram

Transmitter FSMSend’

Idle

Load

Send

Load, Busy, ResetCounter, ResetBRG

Count 300Hz’

Shift

300Hz

Count=10’

Wait

Count=10

Shift, Increment,Busy

Send

Send’

BusyA one-hot state encodingwould make for a simple implementation.

Be sure to choose stateencodings and use hazard-free logic minimization that ensures Busy signal will have nohazards…

Reset/Load, Shift

Asynchronous Signals

• Problem: asynchronous signals do not respect setup and hold times– Signals may change at any time

Clock

Tsu

Th

ok ok ok okbad bad

Metastability

S=0

R=0Q=1

Q’=0

• Imagine if R pulsed high for a very short time and back low– Could it impart enough energy to get Q halfway

between ‘1’ and ‘0’? Yes.– Latch might hang in the midway point for some time– Called metastability

Metastability

• Violating tsetup for a D flip flop can cause very short pulses on signals Y and Z, and make flip flop metastable

D

CLK

Q

Q’

Y

Z

Solution #1: Synchronize Signal A

D Q

D Q

IFL

A

N0

N1

C0

C1

5ns

10ns

clk

clk

D Q

clk

IFL now sees synchronous

input

Synchronizing flip flop still susceptible togoing metastable due to setup time violations.

Solution beyond scope of this class.

Solution #2: Use Gray Codes for States

D Q

D Q

IFL

A

11

A

A’

00

N0

N1

C0

C1

5ns

10ns

clk

clk

01

A

A’

00

Will never have casewhen both pathstransitioning…

State change will occur or it won’t…

Solution #2 – Doesn’t Always Work

• To understand the problem, need to understand hazards.

Gates Have Real Timing…A

g1

g2

F

F

A’B=1

AC=1

g1

g2Called a false output – static equations indicate F=1 butdynamic behavior gives a “glitch”

Solution #3

• Use both gray code states and hazard-free logic minimization– Gray codes ensure only one state bit changes– HFLM ensures no hazards (false outputs) exist

11

S

01

S’

D Q

D Q

IFL

A

N0

N1

C0

C1

5ns

10ns

clk

clk