lect2 up120 (100325)

Lecture 120 – Component Matching (3/25/10) 20-1

CMOS Analog Circuit Design © P.E. Allen - 2010

LECTURE 120 – COMPONENT MATCHINGLECTURE ORGANIZATION

Outline• Introduction• Electrical matching• Physical matching• SummaryCMOS Analog Circuit Design, 2nd Edition ReferencePages 56-59 and new material

Lecture 120 – Component Matching (3/25/10) Page 120-2


INTRODUCTIONWhat is Accuracy and Matching?

The accuracy of a quantity specifies the difference between the actual value of thequantity and the ideal or true value of the quantity.The mismatch between two quantities is the difference between the actual ratio of thequantities and the desired ratio of the two quantities.

Example:x1 = actual value of one quantityx2 = actual value of a second quantityX1 = desired value of the first quantityX2 = desired value of the second quantityThe accuracy of a quantity can be expressed as,

Accuracy = x - X

X = XX

The mismatch, , can be expressed as,

=

x2x1

-X2X1

X2X1

= X1x2X2x1

- 1



Relationship between Accuracy and MatchingLet:

X1 = |x1 - X1| x1 = X1 ± X1

andX2 = |x2 – X2| x2 = X2 ± X2

Therefore, the mismatch can be expressed as,

= X1(X2 ± X2)X2(X1 ± X1) – 1 =

1 ±X2

X2

1 ±X1

X1

– 1 1 ±X2

X2 1 +-

X1X1

– 1

1 ± X2

X2 +-

X1X1

– 1 = ± X2

X2 +-

X1X1

Thus, the mismatch is approximately equal to the difference in the accuracies of x1 and x2assuming the deviations ( X) are small with respect to X.



123456789

10

0 X0 1 2 3 4 5 6 7 8 9 10 1211

Num

ber

of S

ampl

es

041005-011314

Characterization of the MismatchMean of the mismatch for N samples-

m = 1N

i=1

N

i

Standard deviation of the mismatch for N samples-

s = = 1

N-1i=1

N( i - m )2

Example:

m = 25340 = 6.325 s = 2.115



Motivation for Matching of ComponentsThe accuracy of analog signal processing is determined by the accuracy of gains and timeconstants. These accuracies are dependent upon:

Gain Ratios of components or areasTime constants Products of components or areas

Ratio Accuracy?

Actual Ratio = X1± X1X2± X2 =

X1X2

1±X1

X1

1±X2

X2

X1X2 1±

X1X1 1+-

X2X2

X1X2 1±

X1X1 +-

X2X2

If X1 and X2 match ( X1/X1 X2/X2), then the actual ratio becomes the ideal ratio.

Product Accuracy?

Product accuracy = (X1± X1)(X2± X2) = X1X2 1±X1

X1 1±X2

X2 X1X2 1±X1

X1 ±X2

X2

Unfortunately, the product cannot be accurately maintained in integrated circuits.



Switched Capacitor CircuitsSwitched capacitor circuits offer a solution to the product accuracy problem.A switched capacitor replacement of aresistor:

The product of a resistor, R1, and a capacitor,C2, now become,

R1C2 = TcC1 C2 =

1fcC1 C2 =

C2fcC1

The accuracy of the time constant (product) now becomes,C2fcC1 1±

C2C2 +-

C1C1 +-

fcfc

Assuming the clock frequency is accurate and larger than the signal bandwidth, then timeconstants in analog signal processing can be accurately matched by ratios of elements.

060316-06

+

−v1

+

−v2

φ1 φ2

C1+

−v1

+

−v2

R1= C1

Tc

φ1

φ2Tc



Types of Mismatches1.) Those controlled or influenced by electrical design

- Transistor operation- Circuit techniques- Correction/calibration techniques

2.) Those controlled or influenced by physical design- Random statistical fluctuations (microscopic fluctuations and irregularities)- Process bias (geometric variations)- Pattern shift (misalignment)- Diffusion interactions- Stress gradients and package shifts- Temperature gradients and thermoelectrics- Electrostatic interactions



ELECTRICAL MATCHINGMatching PrincipleAssume that two transistors are matched (large signal model parameters are equal).Then if all terminal voltages of one transistor are equal to the terminal voltages of theother transistor, then the terminal currents will be matched.

Q1 Q2

iC1 iC2iB1 iB2

iE1 iE2

M1 M2

iD1 iD2

041005-02

Note that the terminals may be physically connected together or at the same potential butnot physically connected together.



Examples of the Matching Principle

VB

iD1 iD2

M1 M2

M3 M4

+

-Vio

M5M1 M2

M3 M4

VB

iD1 iD2

041005-03

iD1 iD2

M1 M2+

-Vio

M5

Cascode current mirror:The key transistors are M1 and M2. The gates and sources are physically connected

and the drains are equal due to M3 and M4 gate-source drops. As a result, iD1 will bevery close to iD2.

Differential amplifier:When iD1 and iD2 are equal, the fact that the drains of M1 and M2 are equal should

give the smallest value of the input offset voltage, Vio.

Note: Since the drain voltages of M3 and M4 in both circuits are not necessarily equal,the gate-source voltages of M3 and M4 are not exactly equal which cause the drainvoltages of M1 and M2 to not be exactly equal.



Gate-Source MatchingNot as precise as the previous principle but useful for biasing applications.A. If the gate-source voltages of two or more FETs areequal and the FETs are matched and operating in thesaturation region, then the currents are related by the W/Lratios of the individual FETs. The gate-source voltagesmay be directly or indirectly connected.

iD1 = K’W1

2L1 (vGS1-VT1)2 (vGS1-VT1)2 =

2K’iD1

(W1/L1)

iD2 = K’W2

2L2 (vGS2-VT2)2 (vGS2-VT2)2 =

2K’iD2

(W2/L2)

If vGS1 = vGS2, then W2

L2iD1 =

W1

L1iD2 or iD1 =

W1/L1

W2/L2iD2

B. If the drain currents of two or more transistors are equal and the trans-istors are matched and operating in the saturation region, then the gate-source voltages are related by the W/L ratios (ignoring bulk effects).

If iD1=iD2, then

vGS1 = VT1+W2/L2

W1/L1(vGS2-VT2) or vGS1 = vGS2 if

W2

L2=

W1

L1

+

-

vGS1

iD1M1

iD2M2

+

-

vGS2

W1L1

W2L2

Fig. 290-02

+

-vGS1

iD1

iD2M2

+

-vGS2

W1L1

W2L2

Fig. 290-0



Process Independent Biasing - MOSFETThe sensitivity of the bias points of all transistors depend on both the variation of thetechnological parameters and the accuracy of the biasing circuits.Gate-source voltage decomposition:

The gate-source voltage of the MOSFET can be divided into two parts:1.) The part necessary to form or enhance the channel, VT

2.) The part necessary to cause current toflow, VGS – VT = VON , called theoverdrive.

This overdrive can be expressed,

VON = VDS(sat) = 2ID

K’(W/L)The dependence of the bias point on the technology, VT, can be reduced by making VON= VDS(sat) >> VT.

This implies that small values of W/L are preferable. Unfortunately, this causes thetransconductance to become small if the current remains the same.



Doubly Correlated SamplingIllustration of the use of chopper stabilization to remove the undesired signal, vu, from thedesired signal, vin. In this case, the undesired signal is the gate leakage current.

+1

-1t

T fc = 1

vin

vu

voutvB vC

Vin(f)

Vu(f)

VB(f)

ffc0 2fc

f

f

3fcVC(f)

ffc0 2fc 3fc

A1 A2

Clock

VA(f)

ffc0 2fc 3fc

vA

Fig. 7.5-8



An Op Amp Using Doubly Correlated Sampling to Remove DC Offsets

051207-01

clkb

clk

clk

clkb

Inn

Inn

Inp

InpVDD

clk clkb

clkclkb

clkb

clkclk

clkb

Inn

Inn

Inp

InpVDD

VDD

M1 M2

M3 M4

Cc

M5

R1

R2

• Chopping with 50% duty cycle• All switches use thick oxide devices to reduce gate leakage• Gain gm1(rds2||rds4)gm5R2Will examine further in low noise op amps.



Self-Calibration TechniquesThe objective of self-calibration is to increase the matching between two or morecomponents (generally passive).The requirements for self-calibration:1.) A time interval in which to perform the calibration2.) A means of adjusting the value of one or more of the components.

Fixed Component

AdjustableComponent

Comparisonof values

041007-05

Self-calibration can typically improve the matching by a factor of 2-3 bits (4-8).



Example of Capacitor Self-CalibrationConsider the charge amplifier below that should have a gainof unity.

Assume the amplifier has a DC input offset voltage of Vio. The following shows how tocalibrate one (or both) of the capacitors.

+-

VRef

vOUT

C1

C2Vio

VRef -Vio+ -

Vio+-

Autozero Phase

+-

VRef

vOUT

C2

C1

Vio

Vio+-

+

-

Calibration Phase

VRef -Vio

vx

041007-07

In the calibration phase, vx, is:

vx = (VREF-Vio)C2

C1+C2 - (VREF-Vio)

C1C1+C2

= (VREF-Vio)C2-C1C1+C2

The correction circuitry varies C1 or C2 until vx = 0 as observed by vOUT.

+-

vIN vOUT

C1 C2

041007-06



Variable ComponentsThe correction circuitry should be controlled by logic circuits so that the correction canbe placed into memory to maintain the calibration of the circuit during application.Implementation for C1 and C2 of the previous example:

C1

S1

C1

S2 S3

C1

2N

SN

C1 1-2K1 2K 2K+1

C1

2K+2

Capacitor C1

C2

S1

C2

S2 S3

C2

2N

SN

C2 1-2K1 2K 2K+1

C2

2K+2

Capacitor C2041007-08

K is selected to achieve the desired tolerance or variationN is selected to achieve the desired resolution (N > K)

Additional circuitry:Every self-calibration system will need additional logic circuits to sense when the valueof vx changes from positive to negative (or vice versa) and to store the switch settings inmemory to maintain the calibration.



Basics of Dynamic Element Matching†

Dynamic element matching chooses different, approximately equal-valued elements torepresent a more precise value of a component as a function of time.Goal of dynamic element matching:Convert the error due to element mismatch from a dc offset into an ac signal of equivalentpower which can be removed by the appropriate means (doubly-correlated sampling,highpass filtering of a sigma-delta modulator, etc.)

† L. R. Carley, “A Noise-Shaping Coder Topology for 15+ Bit Converters, IEEE J. of Solid-State Circuits, vol. 24, no. 2, April 1989, pp. 267-273.

R0

S0VRef

i

All resistor are approximately equalvalued to within some tolerance

R1

S1

R2

S2

R3

S3

R4

S4

R5

S5

R6

S6

R7

S7

R8

S8

R9

S9 R0

S0

R1

S1

R2

S2

R3

S3

R4

S4

R5

S5

R6

S6

R7

S7

R8

S8

R9

S9

R0

S0

R1

S1

R2

S2

R3

S3

R4

S4

R5

S5

R6

S6

R7

S7

R8

S8

R9

S9Time t2

Time t1

041010-01



How Dynamic Element Matching WorksAssume that we have three approximately equal elements with the following currents:

Element 1 = 0.99mA Element 2 = 1.03mA Element 3 = 0.98mA

Ideal current output level

Error when dynamicelement matching is not used

Error when dynamicelement matching is used

t0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0

1

2

3

t0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

-1

0

+1

+2

Nor

mal

Err

or (

%)

Elements → 1 1 1 1 1 1 1,2 1,2 1,2 1,2 1,2 1,2 1,2,3

t0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

-1

0

+1

+2

Dyn

amic

Ele

men

tM

atch

ing

Err

or (

%)

Elements → 1 3 2 3 1 2 1,2 2,3 1,3 1,2 1,3 2,3 1,2,3+3

-2

-3 060405-06

Ide

al C

urre

nt (

mA

)



Issues of Dynamic Element Matching• The selection of the elements must be truly random for the maximum benefit to occur.• If the number of elements is large this can be an overwhelming task to implement. An

approximation to random selection is the butterfly-type randomizer below:S1

S1

S2

S2

S3

S3

S4

S5

S5

S5

S6

S6

S7

S7

S8

S8

S9

S9

S10

S10

S11

S11

S12

S12

Three-stage, eight-linebutterfly randomizer.Each pair of switchesmarked with the samelabel is controlled toeither exchange the two signal lines or pass them directly to the next stage.

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7041010-03

• When using the dynamic element technique, one needs to be careful that the averagingactivity of the dynamic element matching process does not interfere with otheraveraging processes that might be occurring simultaneously (i.e. modulators).

• Other references:1.) B.H. Leung and s. Sutarja, “Multibit - A/D Converter Incorporating A Novel Class of Dynamic Element Matching

Techniques,” IEEE Trans. on Circuits and Systems-II, vol. 39, no. 1, Jan. 1992, pp. 35-51.

2.) R. Baird and T. Fiez, “Linearity Enhancement of Multibit - A/D and D/A Converters Using Data WeightedAveraging,” IEEE Trans. on Circuits and Systems-II, vol. 42, no. 12, Dec. 1995, pp. 753-762.



PHYSICAL MATCHINGReview of Physical MatchingWe have examined these topics in previous lectures. To summarize, the sources ofphysical mismatch are:

- Random statistical fluctuations (microscopic fluctuations and irregularities)- Process bias (geometric variations)- Pattern shift (misalignment)- Diffusion interactions- Stress gradients and package shifts- Temperature gradients and thermoelectrics- Electrostatic interactions



Rules for Resistor Matching†

1.) Construct matched resistors from the same material. 2.) Make matched resistors the same width. 3.) Make matched resistors sufficiently wide. 4.) Where practical, use identical geometries for resistors (replication principle) 5.) Orient resistors in the same direction. 6.) Place matched resistors in close physical proximity. 7.) Interdigitate arrayed resistors. 8.) Place dummy resistors on either end of a resistor array. 9.) Avoid short resistor segments.10.) Connect matched resistors in order to cancel thermoelectrics.11.) If possible place matched resistors in a low stress area (minimize pieozoresistance).12.) Place matched resistors well away from power devices.13.) Place precisely matched resistors on the axes of symmetry of the die.14.) Consider the influence of tank modulation for HSR resistors (the voltage modulation

of the reverse-biased depletion region changes the sheet resistivity).15.) Sectioned resistors are superior to serpentine resistors.

† Alan Hastings, Art of Analog Layout, 2n d ed, 2006, Pearson Prentice Hall, New Jersey



Rules for Resistor Matching – Continued16.) Use poly resistors in preference to diffused resistors.17.) Do not allow the buried layer shadow to intersect matched diffused resistors.18.) Use electrostatic shielding where necessary.19.) Do not route unconnected metal over matched resistors.20.) Avoid excessive power dissipation in matched resistors.

Lecture 120 – Component Matching (3/25/10) 0-23


Rules for Capacitor Matching†

1.) Use identical geometries for matched capacitors (replication principle). 2.) Use square or octogonal geometries for precisely matched capacitors. 3.) Make matched capacitors as large as possible. 4.) Place matched capacitors adjacent to one another. 5.) Place matched capacitors over field oxide. 6.) Connect the upper electrode of a matched capacitor to the higher-impedance node. 7.) Place dummy capacitors around the outer edge of the array. 8.) Electrostatically shield matched capacitors. 9.) Cross-couple arrayed matched capacitors.10.) Account for the influence of the leads connecting to matched capacitors.11.) Do not run leads over matched capacitors unless they are electrostatically shielded.12.) Use thick-oxide dielectrics in preference to thin-oxide or composite dielectrics.13.) If possible, place matched capacitors in areas of low stress gradients.14.) Place matched capacitors well away from power devices.15.) Place precisely matched capacitors on the axes of symmetry for the die.




Mismatched TransistorsAssume two transistors have vDS1 = vDS2, K1’ K2’ and VT1 VT2. Therefore we have

iOiI =

K2’(vGS - VT2)2

K1’(vGS - VT1)2

How do you analyze the mismatch? Use plus and minus worst case approach. Define K’ = K’2-K’1 and K’ = 0.5(K2’+K1’) K1’= K’-0.5 K’ and K2’= K’+0.5 K’

VT = VT2-VT1 and VT = 0.5(VT1+VT2) VT1 =VT -0.5 VT and VT2=VT+0.5 VT

Substituting these terms into the above equation gives,

iOiI =

(K’+0.5 K’)(vGS - VT - 0.5 VT )2

(K’-0.5 K’)(vGS - VT + 0.5 VT)2 =

1 +K’

2K’ 1 -VT

2(vGS-VT)2

1 -K’

2K’ 1 +VT

2(vGS-VT)2

Assuming that the terms added to or subtracted from “1” are smaller than unity givesiOiI ≈ 1 +

K’2K’ 1 +

K’2K’ 1 -

VT

2(vGS-VT)2

1 -VT

2(vGS-VT)2

1 + K’

K’ - 2 VT

(vGS-VT)

If K’/K’ = ±5% and VT/(vGS-VT) = ±10%, then iO/iI 1 ± 0.05 ±(-0.20) = 1±(0.25)



Geometric EffectsHow does the size and shape of the transistor effect its matching?Gate Area:

Vth = CVth

W effLeffKp = K’

CKp

W effLeffW/W =

C W/W

W effLeff

where CVth, CKp and C W/W are constants determined by measurement.

Values from a 0.35μm CMOS technology:

Vth,NMOS = 10.6mV·μm

W effLeff Vth,PMOS =

8.25mV·μmW effLeff

and

W

W NMOS = 0.0056·μm

W effLeff

WW PMOS =

0.0011·μmW effLeff

The above results suggest that PMOS devices would be better matched than NMOSdevices in this technology.



Pelgrom’s LawSpatial Averaging: Local and randomvariations decrease as the device sizeincreases, since the parameters “averageout” over a greater area.Pelgrom’s Law:

s2( P) = Ap

2

WL + Sp2 Dx

2

where,

P = mismatch in a parameter, PWL = width times the length of the device (effective Pelgrom area)Ap = proportionality constant between the standard deviation of DP and the area of

the deviceDx = distance between the matched devices

Sp = proportionality constant between the standard deviation of P and Dx

As Dx becomes large, the standard deviation tends to infinity which is not realistic.

Threshold mismatch for 0.18 m NMOS



Rules for Transistor Matching†

1.) Use identical finger geometries. 2.) Use large active areas. 3.) For voltage matching, keep VGS-VT, small ( i.e. 0.1V). 4.) For current matching, keep VGS-VT, large (i.e. 0.5V). 5.) Orient the transistors in the same direction. 6.) Place the transistors in close proximity to each other. 7.) Keep the layout of the matched transistors as compact as possible. 8.) Where practical use common centroid geometry layouts. 9.) Place dummy segments on the ends of arrayed transistors.10.) Avoid using very short or narrow transistors.11.) Place transistors in areas of low stress gradients.12.) Do not place contacts on top of active gate area.13.) Keep junctions of deep diffusions as far away from the active gate area as possible.14.) Do not route metal across the active gate region.15.) Place precisely matched transistors on the axes of symmetry of the die.16.) Do not allow the buried layer shadow to intersect the active gate area.17.) Connect gate fingers using metal connections.




SUMMARY• IC technology offers poor absolute values but good relative values or matching• In analog circuits, gains are determined by ratios (good matching) and time constants

are determined by products (poor matching)• Electrical matching is determined in the electrical design phase

- Matching due to equal terminal voltages- Matching due to process independent biasing- Doubly correlated sampling- Self-calibration techniques- Dynamic element matching

• Physical matching is determined in the physical design phase- Random statistical fluctuations (microscopic fluctuations and irregularities)

- Process bias (geometric variations)- Pattern shift (misalignment)- Diffusion interactions - Stress gradients and package shifts- Temperature gradients and thermoelectrics- Electrostatic interactions

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