lecture 12: adderskmram/1192-2192/lectures/adders.pdf · 2017. 10. 16. · carry-skip adder...

Introduction to

CMOS VLSI

Design

Lecture 12:

AddersDavid Harris, Harvey Mudd College

Kartik Mohanram and Steven Levitan

University of Pittsburgh

CMOS VLSI Design11: Adders Slide 2

Outline

Single-bit Addition

Carry-Ripple Adder

Carry-Skip Adder

Carry-Lookahead Adder

Carry-Select Adder

Carry-Increment Adder

Tree Adder


Single-Bit Addition

Half Adder Full Adder

A B Cout S

0 0

0 1

1 0

1 1

A B C Cout S

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

A B

S

Cout

A B

C

S

Cout

out

S

C

out

S

C


Single-Bit Addition

Half Adder Full Adder

A B Cout S

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

A B C Cout S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

A B

S

Cout

A B

C

S

Cout

out

S A B

C A B

out ( , , )

S A B C

C MAJ A B C


Full Adder Design I

Brute force implementation from eqns

out ( , , )

S A B C

C MAJ A B C

ABC

S

Cout

MA

J

ABC

A

B BB

A

CS

C

CC

B BB

A A

A B

C

B

A

CBA A B C

Cout

C

A

A

BB


Full Adder Design II

Factor S in terms of Cout

S = ABC + (A + B + C)(~Cout)

Critical path is usually C to Cout in ripple adder

SS

Cout

A

B

C

Cout

MINORITY


Layout

Clever layout circumvents usual line of diffusion

– Use wide transistors on critical path

– Eliminate output inverters


Full Adder Design III

Complementary Pass Transistor Logic (CPL)

– Slightly faster, but more area

A

C

S

S

B

B

C

C

C

B

BC

out

Cout

C

C

C

C

B

B

B

B

B

B

B

B

A

A

A


Full Adder Design IV

Dual-rail domino

– Very fast, but large and power hungry

– Used in very fast multipliers

Cout

_h

A_h B_h

C_h

B_h

A_h

Cout

_l

A_l B_l

C_l

B_l

A_l

S_hS_l

A_h

B_h B_hB_l

A_l

C_lC_h C_h

CMOS VLSI Design

Transmission Gate Full Adder

A

B

P

Ci

VDDA

A A

VDD

Ci

A

P

AB

VDD

VDD

Ci

Ci

Co

S

Ci

P

P

P

P

P

Sum Generation

Carry Generation

Setup

© Digital Integrated Circuits2nd Arithmetic CircuitsRabaey


Carry Propagate Adders

N-bit adder called CPA

– Each sum bit depends on all previous carries

– How do we compute all these carries quickly?

+

BN...1

AN...1

SN...1

Cin

Cout

11111

1111

+0000

0000

A4...1

carries

B4...1

S4...1

Cin

Cout

00000

1111

+0000

1111

Cin

Cout


Carry-Ripple Adder

Simplest design: cascade full adders

– Critical path goes from Cin to Cout

– Design full adder to have fast carry delay

Cin

Cout

B1

A1

B2

A2

B3

A3

B4

A4

S1

S2

S3

S4

C1

C2

C3


Inversions

Critical path passes through majority gate

– Built from minority + inverter

– Eliminate inverter and use inverting full adder

Cout

Cin

B1

A1

B2

A2

B3

A3

B4

A4

S1

S2

S3

S4

C1

C2

C3


PGK

For a full adder, define what happens to carries

– Generate: Cout = 1 independent of C

• G =

– Propagate: Cout = C

• P =

– Kill: Cout = 0 independent of C

• K =


PGK

For a full adder, define what happens to carries

– Generate: Cout = 1 independent of C

• G = A • B

– Propagate: Cout = C

• P = A B

– Kill: Cout = 0 independent of C

• K = ~A • ~B


Generate / Propagate

Equations often factored into G and P

Generate and propagate for groups spanning i:j

Base case

Sum:

:

:

i j

i j

G

P

:

:

i i i

i i i

G G

P P

0:00:00inGCP0:00:00inGCP

0:0 0

0:0 0

G G

P P

iS

CMOS VLSI Design17

Manchester Carry Chain

CoC

i

Gi

Di

Pi

Pi

VDD

CoC

i

Gi

Pi

VDD


CMOS VLSI Design18


G2

C3

G3

Ci,0

P0

G1

VDD

G0

P1

P2

P3

C3

C2

C1

C0


CMOS VLSI Design19


Pi + 1

Gi + 1

Ci

Inverter/Sum Row

Propagate/Generate Row

Pi

Gi

Ci - 1

Ci + 1

VDD

GND

Stick Diagram



Generate / Propagate

Equations often factored into G and P

Generate and propagate for groups spanning i:j

Base case

Sum:

: : : 1:

: : 1:

i j i k i k k j

i j i k k j

G G P G

P P P

:

:

i i i i i

i i i i i

G G A B

P P A B

0:0 0

0:0 0 0

inG G C

P P

1:0i i iS P G

Gi:kGk-1:jPi:kPk-1:j

Gi:j

Pi:j


PG Logic

S1

B1

A1

P1

G1

G0:0

S2

B2

P2

G2

G1:0

A2

S3

B3

A3

P3

G3

G2:0

S4

B4

P4

G4

G3:0

A4

Cin

G0

P0

1: Bitwise PG logic

2: Group PG logic

3: Sum logicC

0C

1C

2C

3

Cout

C4


Carry-Ripple Revisited

:0 1:0 i i i iG G P G

S1

B1

A1

P1

G1

G0:0

S2

B2

P2

G2

G1:0

A2

S3

B3

A3

P3

G3

G2:0

S4

B4

P4

G4

G3:0

A4

Cin

G0

P0

C0

C1

C2

C3

Cout

C4


Carry-Ripple PG DiagramD

ela

y

0123456789101112131415

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

Bit Position

ripplet


Carry-Ripple PG DiagramD

ela

y

0123456789101112131415

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

Bit Position

ripple xor( 1)pg AOt t N t t


PG Diagram Notation

i:j

i:j

i:k k-1:j

i:j

i:k k-1:j

i:j

Gi:k

Pk-1:j

Gk-1:j

Gi:j

Pi:j

Pi:k

Gi:k

Gk-1:j

Gi:j G

i:j

Pi:j

Gi:j

Pi:j

Pi:k

Black cell Gray cell Buffer


Carry-Skip Adder

Carry-ripple is slow through all N stages

Carry-skip allows carry to skip over groups of n bits

– Decision based on n-bit propagate signal

Cin

+

S4:1

P4:1

A4:1

B4:1

+

S8:5

P8:5

A8:5

B8:5

+

S12:9

P12:9

A12:9

B12:9

+

S16:13

P16:13

A16:13

B16:13

Cout

C4

1

0

C8

1

0

C12

1

0

1

0


Carry-Skip PG Diagram

For k n-bit groups (N = nk)

skipt

012345678910111213141516

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:016:0


Carry-Skip PG Diagram

For k n-bit groups (N = nk)

skip xor2 1 ( 1)pg AOt t n k t t

012345678910111213141516

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:016:0


Variable Group Size

Delay grows as O(sqrt(N))

012345678910111213141516

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:016:0

CMOS VLSI Design

Carry Look Ahead Eq

Co,k = f(Ak,Bk, Co,k-1) = Gk + Pk*Co,k-1

Co,k = Gk + Pk(Gk-1 + Pk-1*Co,k-2)

Co,k = Gk + Pk(Gk-1+Pk-1(… +P1(G0 + P0*Ci,0)))

Ci,0 = 0

11: Adders Slide 30

CMOS VLSI Design31

LookAhead - Basic Idea

Co k f Ak Bk Co k 1– Gk PkCo k 1–+= =

AN-1, BN-1A1, B1

P1

S1

• • •

• • • SN-1

PN-1Ci, N-1

S0

P0Ci,0 Ci,1

A0, B0


CMOS VLSI Design32

Look-Ahead: Topology

Co k Gk Pk Gk 1– Pk 1– Co k 2–+ +=

Co k Gk Pk Gk 1– Pk 1– P1 G0 P0Ci 0+ + + +=

Expanding Lookahead equations:

All the way:

Co,3

Ci,0

VDD

P0

P1

P2

P3

G0

G1

G2

G3


CMOS VLSI Design33

Logarithmic Look-Ahead

Adder

A7

F

A6A5A4A3A2A1

A0

A0

A1

A2A3

A4A5

A6

A7

F

tp log2(N)

tp N


CMOS VLSI Design34

Carry Lookahead Trees

Co 0 G0 P0Ci 0+=

Co 1 G1 P1 G0 P1P0 Ci 0+ +=

Co 2 G2 P2G1 P2 P1G0 P+ 2 P1P0C i 0+ +=

G2 P2G1+ = P2P1 G0 P0Ci 0+ + G2:1 P2:1Co 0+=

Can continue building the tree hierarchically.


CMOS VLSI Design

Trees

Groups of 4 computed in parallel

Each group

– C0,0 C0,1 C0,2 and C03

– Eg C02 = G2 + P2G1 + P2 P1G0 + P2 P1 P0

Ci,0 = G2+P2 C0,1

11: Adders Slide 35


74181 Carry Lookahead

74181


Tree of CLAs


Carry-Lookahead Adder

Carry-lookahead adder computes Gi:0 for many bits

in parallel.

Uses higher-valency cells with more than two inputs.

Cin

+

S4:1

G4:1

P4:1

A4:1

B4:1

+

S8:5

G8:5

P8:5

A8:5

B8:5

+

S12:9

G12:9

P12:9

A12:9

B12:9

+

S16:13

G16:13

P16:13

A16:13

B16:13

C4

C8

C12

Cout


CLA PG Diagram

012345678910111213141516

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:016:0


Higher-Valency Cells

i:j

i:k k-1:l l-1:m m-1:j

Gi:k

Gk-1:l

Gl-1:m

Gm-1:j

Gi:j

Pi:j

Pi:k

Pk-1:l

Pl-1:m

Pm-1:j


Carry-Select Adder

Trick for critical paths dependent on late input X

– Precompute two possible outputs for X = 0, 1

– Select proper output when X arrives

Carry-select adder precomputes n-bit sums

– For both possible carries into n-bit group

Cin+

A4:1

B4:1

S4:1

C4

+

+

01

A8:5

B8:5

S8:5

C8

+

+

01

A12:9

B12:9

S12:9

C12

+

+

01

A16:13

B16:13

S16:13

Cout

0

1

0

1

0

1



Factor initial PG and final XOR out of carry-select

5:4

6:4

7:4

9:8

10:8

11:8

13:12

14:12

15:12

0123456789101112131415

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

incrementt



Factor initial PG and final XOR out of carry-select

5:4

6:4

7:4

9:8

10:8

11:8

13:12

14:12

15:12

0123456789101112131415

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

increment xor1 ( 1)pg AOt t n k t t


Variable Group Size

Also buffer

noncritical

signals

3:25:4

6:4

8:7

9:7

12:11

13:11

14:11

15:11

10:7

3:25:4

6:4

8:7

9:7

12:11

13:11

14:11

15:11

10:7 6:0

3:0

1:0

0123456789101112131415

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

0123456789101112131415

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0


Tree Adder

If lookahead is good, lookahead across lookahead!

– Recursive lookahead gives O(log N) delay

Many variations on tree adders


Brent-Kung

1:03:25:47:69:811:1013:1215:14

3:07:411:815:12

7:015:8

11:0

5:09:013:0

0123456789101112131415

15:014:013:0 12:011:010:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0


Sklansky

1:0

2:03:0

3:25:47:69:811:1013:1215:14

6:47:410:811:814:1215:12

12:813:814:815:8

0123456789101112131415

15:014:013:0 12:011:010:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0


Kogge-Stone

1:02:13:24:35:46:57:68:79:810:911:1012:1113:1214:1315:14

3:04:15:26:37:48:59:610:711:812:913:1014:1115:12

4:05:06:07:08:19:210:311:412:513:614:715:8

2:0

0123456789101112131415

15:014:013:0 12:011:010:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0


Tree Adder Taxonomy

Ideal N-bit tree adder would have

– L = log N logic levels

– Fanout never exceeding 2

– No more than one wiring track between levels

Describe adder with 3-D taxonomy (l, f, t)

– Logic levels: L + l

– Fanout: 2f + 1

– Wiring tracks: 2t

Known tree adders sit on plane defined by

l + f + t = L-1


Tree Adder Taxonomy

f (Fanout)

t (Wire Tracks)

l (Logic Levels)

0 (2)

1 (3)

2 (5)

3 (9)

0 (4)

1 (5)

2 (6)

3 (8)

2 (4)

1 (2)

0 (1)

3 (7)


Tree Adder Taxonomy

f (Fanout)

t (Wire Tracks)

l (Logic Levels)

0 (2)

1 (3)

2 (5)

3 (9)

0 (4)

1 (5)

2 (6)

3 (8)

2 (4)

1 (2)

0 (1)

3 (7)

Kogge-Stone

Brent-Kung

Sklansky


Han-Carlson

1:03:25:47:69:811:1013:1215:14

3:05:27:49:611:813:1015:12

5:07:09:211:413:615:8

0123456789101112131415

15:014:013:0 12:011:010:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0


Knowles [2, 1, 1, 1]

1:02:13:24:35:46:57:68:79:810:911:1012:1113:1214:1315:14

3:04:15:26:37:48:59:610:711:812:913:1014:1115:12

4:05:06:07:08:19:210:311:412:513:614:715:8

2:0

0123456789101112131415

15:014:013:0 12:011:010:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0


Ladner-Fischer

1:03:25:47:69:811:1013:12

3:07:411:815:12

5:07:013:815:8

15:14

15:8 13:0 11:0 9:0

0123456789101112131415

15:0 14:013:012:0 11:010:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0


Taxonomy Revisited

f (Fanout)

t (Wire Tracks)

l (Logic Levels)

0 (2)

1 (3)

2 (5)

3 (9)

0 (4)

1 (5)

2 (6)

3 (8)

2 (4)

1 (2)

0 (1)

3 (7)

Kogge-

Stone

Sklansky

Brent-

Kung

Han-

CarlsonKnowles

[2,1,1,1]

Knowles

[4,2,1,1]

Ladner-

Fischer

Han-

Carlson

Ladner-

Fischer

New

(1,1,1)

(c) Kogge-Stone

1:02:13:24:35:46:57:68:79:810:911:1012:1113:1214:1315:14

3:04:15:26:37:48:59:610:711:812:913:1014:1115:12

4:05:06:07:08:19:210:311:412:513:614:715:8

2:0

0123456789101112131415

15:014:013:0 12:011:010:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

(e) Knowles [2,1,1,1]

1:02:13:24:35:46:57:68:79:810:911:1012:1113:1214:1315:14

3:04:15:26:37:48:59:610:711:812:913:1014:1115:12

4:05:06:07:08:19:210:311:412:513:614:715:8

2:0

0123456789101112131415

15:014:013:012:011:010:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

(b) Sklansky

1:0

2:03:0

3:25:47:69:811:1013:1215:14

6:47:410:811:814:1215:12

12:813:814:815:8

0123456789101112131415

15:014:013:0 12:011:010:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

1:03:25:47:69:811:1013:12

3:07:411:815:12

5:07:013:815:8

15:14

15:8 13:0 11:0 9:0

0123456789101112131415

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

(f) Ladner-Fischer

(a) Brent-Kung

1:03:25:47:69:811:1013:1215:14

3:07:411:815:12

7:015:8

11:0

5:09:013:0

0123456789101112131415

15:014:013:012:011:010:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

1:03:25:47:69:811:1013:1215:14

3:05:27:49:611:813:1015:12

5:07:09:211:413:615:8

0123456789101112131415

15:014:013:012:011:010:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

(d) Han-Carlson


Summary

Architecture Classification Logic

Levels

Max

Fanout

Tracks Cells

Carry-Ripple N-1 1 1 N

Carry-Skip n=4 N/4 + 5 2 1 1.25N

Carry-Inc. n=4 N/4 + 2 4 1 2N

Brent-Kung (L-1, 0, 0) 2log2N – 1 2 1 2N

Sklansky (0, L-1, 0) log2N N/2 + 1 1 0.5 Nlog2N

Kogge-Stone (0, 0, L-1) log2N 2 N/2 Nlog2N

Adder architectures offer area / power / delay tradeoffs.

Choose the best one for your application.

lecture 12: adderskmram/1192-2192/lectures/adders.pdf · 2017. 10. 16. · carry-skip adder...

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