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Lecture 24: Interconnect parasitics

EECS 312Reading: 8.2.1, 8.4.2 (text), 4.2, 4.3.1

(2nd edition)

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Last Time

• 1T DRAM operation– A major component of digital systems today– Great density, relies on charge sharing to read data,

must be refreshed periodically (leakage currents)• Packaging provides an interface from the chip to

the external world• To send signals off-chip, we need to drive large

capacitances– This is best done by creating a cascaded buffer chain

where each inverter is ~3X larger than its driver

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Lecture Overview

• Simultaneous switching noise (L*di/dt noise)

• Introduce wiring capacitance• Models to calculate these parameters

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L di/dt

VDD

L

L

VoutVin

CL

i(t)Significant inductance due to packaging between the actual power supply and the gates themselves

Large current draws across this L voltage drop

Often called simultaneous switching noise (SSN) since a lot of simultaneous switching will increase di/dt

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SSN Analysis

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Voltage waveforms due to SSN

8

4

1 active driver

Ground bounce shown at left (GND > 0V)

How to limit:

1) Use packaging with small inductance

2) Slow down transitions at I/O pads (reduce di/dt)

3) Low-swing I/O – incompatible with external chips (usually I/O voltage > regular voltage)

time

Vol

tage

0V

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IC Wiring (Interconnect)

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Impact of Interconnect Parasitics

• Reduce Reliability

• Affect Performance

Classes of Parasitics

• Capacitive

• Resistive

• InductiveNot covered in 312

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Nature of Interconnect

Local Interconnect

Global Interconnect

SLocal = STechnology

SGlobal = SDie

Remember scaling?

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Real Data on nature of interconnect

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Capacitance: The Parallel Plate Model

SiO2

Substrate

L

W

T

HILD

ILD: Interlevel dielectric

Bottom plate of cap can be another metal layer

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Permittivities of modern insulators

There is a tremendous push towards low-k (r < 4.0) dielectrics for metallization

This helps delay and power!

Difficult to manufacture

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Fringing Capacitance

w S

Twire

H is sometimes called T – can be confusing

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Typical Wiring Capacitance Values

Top plate

Bottom plate in [aF/m]1000aF = 1fF

Shaded: fringeUnshaded: area

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Capacitance values for diff. configs

Parallel plate model significantly underestimates capacitance when width is comparable to ILD height

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Interwire (Coupling) Capacitance

Substrate

SiO2

Insulator

Level1

Level2

Creates Cross-talkLeads to coupling effects among adjacent wires

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Interwire CapacitanceLayer Poly M1 M2 M3 M4 M5

Capacitance (aF/m), min spacing

40 95 85 85 85 115

Example: if two wires on layer Metal 3 run parallel to each other for 1mm, the capacitance between these two wires is 85aF/m * 1000m = 85000aF = 85fF

In today’s process technologies, interwire capacitance can account for up to 80% of the total wire capacitance

Past

M1Sub

Present / Future

M1

Sub

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Empirical Capacitance ModelsEmpirical capacitance models are the easiest and fastest way to find accurate capacitances for interconnect configurations

Limited configurations can be investigated, 3D effects are not considered

5.025.0

06.106.177.0ILD

wire

ILDILDoxwire H

THW

HWC

Capacitance per unit length This model assumes no neighboring

wires; optimistic

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Wire Capacitance Rule of Thumb

Modern processes have per unit length wiring capacitances around 2 pF/cm

Equal to 0.2 fF per micron of wirelength

This is fairly accurate for wire widths < 2m

Compare this to the amount of MOSFET gate capacitance ~ 1 fF / micron width

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Example Back-end processIntel6 metal layers0.13m processVias shown (connect layers)

Aspect ratio = Twire/Wmin

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Lecture Summary• Simultaneous switching noise is a key problem for

off-chip drivers– Drive them as slowly as allowed

• General interconnect characteristics– Local wires and global wires– Many metal levels, connect with vias

• Capacitance is the primary parasitic– Area, fringing, interwire components– Interwire dominates today– Both simple and complex models exist to compute

capacitance as a function of wire geometry

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Inductance

• Inductance, L, is the measure of ability to store energy in the form of a magnetic field

• Inductance of a wire consists of a self-inductance and a mutual inductance term

Z = R + jL• At high frequencies, inductance can become an

appreciable portion of the total impedance

Angular frequency = 2f

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Inductance is a weak function of conductor dimensions

Most strongly influenced by distance to return path – commonly the power grid

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Why is inductance important?• Inductance may lead to:

– Voltage overshoot– Ringing / non-monotonic voltage response– Faster rise/fall times (enhancing noise)

• Higher performance leads to higher inductive effects– Bandwith ~ 0.35 / rise time– If L * Bandwidth becomes comparable to R,

inductive effects need to be considered

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Inductive effects in action

- Yellow lines are distributed RLC simulation results of a 5 mm line with 30 ps input rise time to large CMOS inverter

- Overshoot and non-monotonic response is seen

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Inductance Trends• Inductance is a weak function of conductor

dimensions (logarithmic)• Inductance is a strong function of current

return path distance– Want to have a nearby ground line to provide a

small current loop• Inductance is most significant in long, fast-

switching nets with low resistance– Clocks are the most susceptible

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Dealing with Inductance

Bus linesVdd GND

• DEC approach in Alpha 21264 -- use entire planes of metal as references (Vdd and GND) to eliminate inductance

- Loss of routing density, added metal layers reduce yield & raise costs

• Another industry approach uses shield wires every ~ 3 signal lines in a dense array

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How to model inductance?• Efficient RLC modeling is possible now

- Asymptotic Waveform Evaluation (AWE)

• Inductance extraction is not available now

- Hot research topic; should not be solved in the next few years- Difficult due to uncertainty in current return path

• Figures of merit can be used; Inductance important when:

C

RL

CL

R2Length

LC2Trise

- Line must be long for the time-of-flight to be comparable to rise time- Line must be short enough such that attenuation does not eliminate inductive effects

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The Transmission Line

Vinr l

c

r l

c

r l

c

r l

c

Voutx

g g g g

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Lossless Transmission Line - Parameters

vacuumspeed of light in

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Wave Propagation Speed

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Wave Reflection for Different Terminations

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Transmission Line Response (RL=

0.0

1.0

2.0

3.0

4.0

5.0V

0.0

1.0

2.0

3.0

4.0

V

0.0 5.0 10.0 15.0t (in tlightf)0.0

2.0

4.0

6.0

8.0

V

RS = 5Z0

RS = Z0

RS = Z0/5

(a)

(b)

(c)

VDestVSource

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Lattice Diagram

VSource VDest

0.8333 V

1.6666 V+ 0.8333

+ 0.8333

+ 0.5556

+ 0.5556

+ 0.3704

+ 0.2469

+ 0.3704

+ 0.2469

2.2222 V

3.1482 V

3.7655 V

...

2.7778 V

3.5186 V

4.0124 V

L/

t

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When to Consider Transmission Line Effects?