lecture 28 field-effect transistors 28 field-effect transistors. ... mosfet summary. electrical...
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ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.
Lecture 28Field-Effect Transistors
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.
Field-Effect Transistors
1. Understand MOSFET operation.
2. Analyze basic FET amplifiers using the load-line technique.
3. Analyze bias circuits.
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.
4. Use small-signal equivalent circuits to analyze FET amplifiers.
5. Compute the performance parameters of several FET amplifier configurations.
7. Understand the basic operation of CMOS logic gates.
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.
NMOS Transistor
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.
NMOS Transistor
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.
Operation in the Cutoff Region
toGSD Vvi ≤= for 0
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.
Operation Slightly Above Cut-Off
By applying a positive bias between the Gate (G) and the body (B), electrons are attracted to the gate to form a conducting n-typechannel between the source and drain. The positive charge on the gate and the negative charge in the channel form a capacitor where:
oxgate t
WLdAC εε ==
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.
The amount of negative charge that accumulates in the channel is given by:
DS
toGSgate
vL
EL
VvCQ
μμτ
2
velocityL
)(
===
−=
This amount of charge is able to move a distance L from the source to the drain in a time τ given by:
Operation Slightly Above Cut-Off
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.
The initial current flow for low drain-source voltage is given by:
DStoGSox
DS
toGSgate
DS
vVvLt
WvL
VvC
Qi
)(
)(metransit ti
in transit charge
2
−=
−=
==
μεμ
τ
Operation Slightly Above Cut-Off
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.
Operation Slightly Above Cut-Off
DStoGSox
DS vVvLt
Wi )( −=με
For small values of vDS, iD is proportional to vDS. The device behaves as a resistance whose value depends on vGS.
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.
Operation in the Triode Region
( )[ ]22 DSDStoGSD vvvvCi −−=
2KP
LWC ⎟
⎠⎞
⎜⎝⎛=
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.
Operation in the Saturation Region
( )
2
2
DSD
toDSGS
toDSGSDSGSGD
toGD
toGSD
Cvi
VvvVvvvvv
VvVvCi
=
+==−→−=
=
−=
boundary the at saturation into transition the at
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.
Exercise 12.1Consider an NMOS transistor having Vto=2V. What is the region of
operation (triode, saturation, or cutoff) if:
1. vGS = 1V and vDS = 5V? Cutoff since vGS <Vto
2. vGS = 3V and vDS = 0.5V? Triode since vGS >Vto and vDS<vGS - Vto
3. vGS = 3V and vDS = 6V? Saturation since vGS >Vto and vDS>vGS – Vto
4. vGS = 5V and vDS = 6V? Saturation since vGS >Vto and vDS>vGS - Vto
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.
Exercise 12.2Suppose that we have an NMOS transistor with KP = 50μA/V2, Vto = 1V, L = 2μm and W = 80μm. Sketch the drain characteristics for vDS from 0 to 10V and vGS=0, 1, 2, 3 and 4V.
For vGS= 0 or 1V, the transistor is cutoff and the drain current is zero. In the saturation region:
2
26
)(
/12
80)1050(21
2
toGSD VvCI
VmaxLWKPC
−=
=⎟⎠⎞
⎜⎝⎛=⎟
⎠⎞
⎜⎝⎛= −
The boundary between the triode and saturation regions occurs when toGSDS Vvv −=
394243112
)()( DSDGS vmAiVv
2DSD CvI =
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.
Exercise 12.2
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.
PMOS Transistor
p+ p+
n
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.
MOSFET Summary
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.
Exercise 12.3Suppose that we have an PMOS transistor with KP = 25μA/V2, Vto= -1V, L = 2μm and W = 200μm. Sketch the drain characteristics for vDS from 0 to -10V and vGS= 0, -1, -2, -3 and -4V.
For vGS= 0 or -1V, the transistor is cutoff and the drain current is zero. In the saturation region:
2
26
)(
/25.12
200)1025(21
2
toGSD VvCI
VmaxLWKPC
−=
=⎟⎠⎞
⎜⎝⎛=⎟
⎠⎞
⎜⎝⎛= −
The boundary between the triode and saturation regions occurs when toGSDS Vvv −=
325.114253125.12
)()(
−−−−−−
DSDGS vmAiVv
2DSD CvI =
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.
Exercise 12.3
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.
Load-Line Analysis of a Simple NMOS Circuit
( ) ( )tvtiRv DSDDDD +=
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.
To establish the load line, we first locate two points on it:
Load-Line Analysis of a Simple NMOS Circuit
For vDD = 20V and RD=1kΩ
( ) ( )
( ) ( )
mAkViv
VvitvtikV
tvtiRv
DDS
DSD
DSD
DSDDDD
201200
200120
=Ω
=→=
=→=+Ω=
+=
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.
Load-Line Analysis of a Simple NMOS Circuit
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.
Load-Line Analysis of a Simple NMOS Circuit
The quiescent operating point (Q point) is found for vin = 0V
0Vfor 44)()(
==+=
in
inGS
vVVtvtv
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.
Load-Line Analysis of a Simple NMOS Circuit
The maximum gate-to-source voltage is found for vin = 1V
1Vfor 54)()(==
+=
in
inGS
vVVtvtv
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.
Load-Line Analysis of a Simple NMOS Circuit
The minimum gate-to-source voltage is found for vin = -1V
1Vfor 34)()(
−==+=
in
inGS
vVVtvtv
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.
Load-Line Analysis of a Simple NMOS Circuit
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.
Peak to peak swing of vGS is 2V
Peak to peak swing of vDS is 12V 6212" −=−
=VA"
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.
The output is not proportional to the input. The output goes down by 7V for a change of +1V on the input. The output goes up by 5V for a change of -1V on the input. The output is said to be “distorted”. This is due to the uneven spacing of the characteristic curves.
vDSQ=11V+5V
-7V
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.
Load-Line Analysis of a Simple NMOS Circuit
Uneven spacing of the drain characteristics
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.
Exercise 12.4Find vDSQ, vDSmin and vDSmax if the circuit values are changed to VDD=15V, VGG=3V:
3V
15V
1Vfor 4-1Vfor 2V0Vfor 3
3)()(
+======
+=
in
in
in
inGS
vVvvV
Vtvtv
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.
To establish the load line, we first locate two points on it:
For vDD = 15V and RD=1kΩ
( ) ( )
( ) ( )
mAkViv
VvitvtikV
tvtiRv
DDS
DSD
DSD
DSDDDD
151150
150115
=Ω
=→=
=→=+Ω=
+=
Exercise 12.4
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.
Exercise 12.4
vDSQ=11V
vDSmin=6V vDSmax=14V
1Vfor V4
-1Vfor 2V
0Vfor V3
max
min
+==
==
==
inGS
inGS
inGS
vv
vv
vvQ
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.
FET Logic
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.
CMOS Inverter
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.
Two-Input CMOS NAND Gate
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.
Two-Input CMOS NOR Gate
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.