lecture 29: lm3s9b96 microcontroller – pulse width modulator (pwm)
TRANSCRIPT
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Lecture 29: LM3S9B96 Microcontroller – Pulse Width Modulator (PWM)
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Stellaris® LM3S9B96 MicrocontrollerData Sheet
Chapter 22Pulse Width Modulator (PWM)
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Pulse Width Modulator (PWM)
Using analog signal (continuous in terms of both voltage and current) Simple and straightforward BUT: not easy to regulate, not power efficient, not resilient
to noise PWM is a powerful technique for digitally encoding
analog signal levels High-resolution counters are used to generate a square
wave The duty cycle of the square wave is modulated to encode
an analog signal Typical applications: switching power supplies, motor
control Power loss in the switching devices is very low: “on” no
current, “off” not voltage drop
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Pulse Width Modulator (PWM)
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Switching Power Supplies
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H Bridge for Motor Control
An H bridge is an electronic circuit that enables a voltage to be applied across a load in either direction
S1 S2 S3 S4 Result
1 0 0 1 Motor moves right
0 1 1 0 Motor moves left
0 0 0 0 Motor free runs
0 1 0 1 Motor brakes
1 0 1 0 Motor brakes
1 1 0 0 Shoot-through
0 0 1 1 Shoot-through
1 1 1 1 Shoot-through
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Pulse Width Modulator (PWM)
The Stellaris PWM module consists of four PWM generator blocks and a control block
Each PWM generator block has the following features: Provides low-latency shutdown and prevents
damage to the motor being controlled One 16-bit counter Two PWM comparators PWM signal generator Dead-band generator
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Pulse Width Modulator (PWM)
The control block determines the polarity of the PWM signals and which signals are passed through to the pins
The PWM control block has the following options: PWM output enable of each PWM signal Optional output inversion of each PWM signal Optional fault handling for each PWM signal Synchronization of timers/comparators/PWM generators
across the PWM generator blocks Interrupt status summary of the PWM generator blocks Extended fault capabilities with multiple fault signals,
programmable polarities, and filtering
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Block Diagram
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PWM Module Block Diagram
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Functional Description
PWM Timer In Count-Down mode:
The timer counts from the load value to zero Goes back to the load value, and continues to count
down In Count-Up/Down mode:
The timer counts from zero up to the load value Counts down to zero Counts up to the load value, and so on
Count-Down mode is used for generating left- or right-aligned PWM signals, while the Count-Up/Down mode is used for generating center-aligned PWM signals
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Functional Description
PWM Timer Outputs three signals that are used in the PWM
generation process: The direction signal (“dir” signal): “low” when
counting down, and “high” when counting up A single-clock-cycle-width High pulse when the
counter is zero (“zero” signal) A single-clock-cycle-width High pulse when the
counter is equal to the load value (“load” signal)
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Functional Description
PWM Comparators Each PWM generator has two comparators that
monitor the value of the counter When either comparator matches the counter,
they output a single-clock-cycle-width High pulse, "cmpA" and "cmpB”
These qualified pulses are used in the PWM generation process
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Signals Used in PWM Generation
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Signals Used in PWM Generation
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Functional Description
PWM Signal Generator takes the “load”, “zero”, “cmpA”, and “cmpB”
pulses (qualified by the dir signal) generates two internal PWM signals, “pwmA” and
“pwmB” In Count-Down mode: zero, load, match A down,
and match B down In Count-Up/Down mode: zero, load, match A
down, match A up, match B down, and match B up
For each event, the effect on each output PWM signal is programmable
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PWM Generation Example In Count-Up/Down Mode
pwmA is set to drive High on match A up, drive Low on match A down, and ignore the other four events
pwmB is set to drive High on match B up, drive Low on match B down, and ignore the other four events
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Functional Description
Dead-Band Generator The generated pwmA and pwmB signals can be
passed to the dead-band generator If the dead-band generator is disabled, pwmA and
pwmB signals will not be modified If the dead-band generator is enabled, the pwmB
signal is lost and two PWM signals are generated based on the pwmA signal, pwmA’ and pwmB’
pwmA’ is pwmA with the rising edge delayed pwmB’ is the iversion of pwmA with a delay
added between the falling edge of pwmA and the rising edge of pwmB’
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PWM Dead-Band Generator
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Functional Description
Interrupt/ADC-Trigger Selector The same four (or six) counter events can be
used to generate an interrupt Any of these events or a set of these events can
be selected Different or the same events can be selected to
generate an ADC trigger
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Functional Description
Synchronization Four PWM generators providing eight PWM
outputs Unsynchronized: each PWM generator and
its two output signals are used alone, independent of other PWM generators
Synchronized: The PWM generator and its two outputs signals are used in conjunction with other PWM generators using a common and unified time base Set the “SYNCn” bits in the PWMSYNC
register will cause corresponding PWM generators reset their counter together
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Functional Description
Fault Conditions When fault conditions happen, the PWM function must
be stopped and the PWMn signals should be set to a safe state
Two basic situations cause fault conditions: The microcontroller is stalled and cannot perform the
necessary computation in the time required for motion control
An external error or event is detected The following inputs can be used to generate a fault
condition FAULTn fault input pins A stall of the controller generated by the debugger The trigger of an ADC digital comparator
Fault conditions are calculated on a per-PWM generator basis
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Functional Description
Output Control Block Takes care of the final conditioning of the pwmA'
and pwmB' signals before they go to the pins as the PWMn signals.
The set of PWM signals that are actually enabled to the pins can be modified via the PWNENABLE register
During fault conditions, PWMn usually must be driven to safe values Use PWMFAULT register to specify whether the output
continues to use the generated signal or an encoding specified in the PWMFAULTVAL register
A final inversion can be applied to any of the PWMn signals using the PWMINVERT register
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Initialization and Configuration
The following example shows how to initialize PWM Generator 0 with a 25-kHz frequency, a 25% duty cycle on the PWM0 pin, and a 75% duty cycle on the PWM1 pin, assuming the system clock is 20 MHz1. Enable the PWM clock by writing a value of 0x0010.0000
to the RCGC0 register2. Enable the clock to the appropriate GPIO module via the
RCGC2 register3. In the GPIO module, enable the appropriate pins for their
alternate function using the GPIOAFSEL register4. Configure the PMCn fields in the GPIOPCTL register to
assign the PWM signals to the appropriate pins5. Configure the RCC register in the System Control module
to use the PWM divide (USEPWMDIV) and set the divider (PWMDIV) to divide by 2 (000).
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Recall: Clock Control
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Initialization and Configuration
6. Configure the PWM generator for countdown mode with immediate updates to the parameters1. Write the PWM0CTL register with a value of
0x0000.00002. Write the PWM0GENA register with a value of
0x0000.008C3. Write the PWM0GENB register with a value of
0x0000.080C
7. Set the period: for a 25-KHz frequency, the period = 1/25,000, or 40 microseconds. The PWM clock source is 10MHz. Thus, there are 400 clock ticks per period. Use this value to set the PWM0LOAD register. In Count-Down mode, set the LOAD field in the PWM0LOAD register to the requested period minus one1. Write the PWM0LOAD register with a value of
0x0000.018F
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Initialization and Configuration
8. Set the pulse width of the PWM0 pin for a 25% duty cycle: Write the PWM0CMPA register with a value of 0x0000.012B
9. Set the pulse width of the PWM1 pin for a 75% duty cycle: Write the PWM0CMPB register with a value of 0x0000.0063
10.Start the timers in PWM generator 0 : Write the PWM0CTL register with a value of 0x0000.0001
11.Enable PWM outputs: Write the PWMENABLE register with a value of 0x0000.0003
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Register Map & Description
Sub-Chapter 22.5 and 22.6
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Key Registers: PWMnCTL
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Key Registers: PWMnGENA, PWMnGENB
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Key Registers: PWMnLOAD
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Key Registers: PWMnCMPA, PWMnCMPB
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Key Registers: PWMENABLE