lecture 3: challenges and opportunities in system lsi (2...

© T. Kuroda (1/50)

Lecture 3: Challenges and Opportunities in System LSI (2) Application and Business

Tadahiro KurodaVisiting MacKay ProfessorDepartment of EECSUniversity of California, [email protected], [email protected]://bwrc.eecs.berkeley.edu/Classes/ee290c_s07http://www.kuroda.elec.keio.ac.jp/

EE290c Spring 2007, Tues & Thurs 9:30-11:00, 212 Cory UCB

© T. Kuroda (2/50)

Challenges and OpportunitiesDevice Level (Physics)

Leakage Problem

Integrated Circuit Level (Electronics)Powerwall (power vs. speed)Variations

Business Level (Economics)Post PC ApplicationsSoC vs. SiP

© T. Kuroda (3/50)

Ten TipsTip 1: Optimize and control VDD and VTH.Tip 2: Total power is minimum when Pleakage/Pactive = 30/70.Tip 3: If you don’t need to hustle, relax and save power.Tip 4: Utilize surplus timing with multiple VDD’s and VTH’s.Tip 5: Total power is minimum when VDDL/VDDH =0.7.Tip 6: Two types are sufficient. Tip 7: Adapt to the change with variable VDD and VTH. Tip 8: Two levels are sufficient. Tip 9: Cooperate across various levels of design hierarchy. Tip 10: Right circuit for the right job.

T. Kuroda, DAC’03 tutorial

© T. Kuroda (4/50)

Tip 1: Optimize and control VDD and VTH

0 0.5 10

0.5

1

Nor

mal

ized

pow

er

VDD [V]

PDYNAMIC

1

2

3

4

5

0N

orm

aliz

ed d

elay

Delay

PSUBTHRESHOLD LEAK

PGATE LEAK

Drain Induced Barrier Lowering (DIBL)

Long L

Increase Drainvoltage

S D

Bar

rier h

eigh

tShort L

S D

Increase Drainvoltage

Courtesy: S. Narendra

© T. Kuroda (5/50)

Trade-off between Power and Delay

012345x 10-7

0

10

20

0.30.50.7-0.1

0.10.3VDD [V] V TH [V

]

Pow

er [W

/gat

e]

Del

ay [p

s]

DDs

V

DD VIVCfaPowerTH

⋅⋅+⋅⋅⋅=−

1002

0.30.50.7-0.1

0.10.3VDD [V] V TH [V

]

( ) 31 .THDD

DD

VVVCDelay

−⋅

∝

Equi-delay

50nm node, FO3 INV

(+ other leakage)

© T. Kuroda (6/50)

Tip 2: Total power is minimum when Pleakage/Pactive = 30/70

0.3 0.5 0.7 0.9 1.1 1.3 1.5

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

V TH

(V)

DD (V)V

Equi-power (solid-lines)0.05 0.1 0.2 0.3 0.4 0.5 0.7 =1.0κ 1.2P

1.3

1.4

PleakagePtotal

=30%

κ S =1.00.9

0.8

0.7

0.6

0.5

1.1

1.2

1.3

Equi-speed (brokenlines)

PS

VDD

P

Pactive ∝ VDD2

30%

70%

Ptotal

Pleakage ∝ 10 VDD

-VTHs

VDD

P

Pactive ∝ VDD2

30%

70%

Ptotal

Pleakage ∝ 10 VDD

-VTHsPleakage ∝ 10 VDD

-VTHs

-VTHs

© T. Kuroda (7/50)

Pleakage/Pactive = 30/70IBM Power5 Intel Pentium4

Pleak

Pleak

© T. Kuroda (8/50)

Saving Energy by Working as Slowly as Possible

Active

Active

Sleep

E=CVH2

E=CVL2

Cycle

© T. Kuroda (9/50)

Tip 4: Utilize surplus timing with multiple VDD’s and VTH’s

1.0

0.5

Supp

ly V

olta

ge R

atio

1.0

0.4

0.5 1.0 1.5V1 (V)

Pow

er D

issi

patio

n R

atio

V2/V1

P2/P1

{ V1, V2 }

V2/V1

V3/V1

{ V1, V2, V3 }

0.5 1.0 1.5V1 (V)

P3/P1

V2/V1

V3/V1

V4/V1

0.5 1.0 1.5V1 (V)

P4/P1

{ V1, V2, V3, V4 }

Tip 4: Utilize surplus timing with multiple VDD’s and VTH’s.Tip 5: Total power is minimum when VDDL/VDDH =0.7.

© T. Kuroda (10/50)

Tip 7: Adapt to the change with variable VDD and VTH

Montecito (90nm) 1.5-2X performance0.8X powerof Madison-9M (130nm)

IIR DAC

ADC

ADCCalc

-+Plimit

Pcalc

Rpackage

Vdie

Vconnector

IIR DAC

ADC

ADCCalc

-+Plimit

Pcalc

Rpackage

Vdie

Vconnector

Power -> VDDTemp. -> VDDVDD -> f

© T. Kuroda (11/50)

Challenges and OpportunitiesDiscuss challenges and opportunities in 3 levels :

1) Device Level (Physics) Leakage Problem

2) Integrated Circuit Level (Electronics)Powerwall (power vs. speed)Variations

3) Application and Business Level (Economics)Post PC ApplicationsSoC vs. SiP

© T. Kuroda (12/50)

1950 1960 1970 1980 1990 2000 2010

Year

Mainframe

Minicon

EWS

PC

Mobile

ENIAC

100$

1M$

Pric

e of

Com

pute

r Sys

tem

Vacuum Tube

Transistor

IC (Bip.)

LSI (NMOS)

ULSI (Low-Power CMOS)

Military

Science

Science

Engineering

OA

Digital Consumer

Downsizing

VLSI (CMOS)

Everybody

Everywhere

© T. Kuroda (13/50)

Downsizing In FutureComputer：

PC -> Portable -> Wearable -> Implantable（$2,000）（$200）（$20）（$2~$0.2）

OA-> Personal (Quality of Life)General Purpose -> Dedicated

Communications：Office LAN -> Home LAN -> PAN -> BAN

-> Close-range -> Proximity Wired -> (Short-range) Wireless

Ubiquitous ComputingComputer & Communications for Consumer applications

© T. Kuroda (14/50)

Wearable Computer

http://www.cs.cmu.edu/~wearable/http://lcs.www.media.mit.edu/projects/wearables/http://www.microopticalcorp.com/

Digital Ink

© T. Kuroda (15/50)

Implantable Computer（Human Body）

Prof. Wentai LIU, NC State Univ.http://www.ece.ncsu.edu/erl/erl_eye.html

Non-power-aware designwould cause bulge at eyeball, and heartburn in stomach.

SiliconImaging

Chip

Antenna

RetinalChip

Eyeball

Swallow a ball-semiconductor chip to collect pictures of internal organs.

http://www.ballsemi.com

sight-impaired person

© T. Kuroda (16/50)

Implantable Computer (Things)

TicketingCheck-out counterWarehouse managementShipping verificationSecurity Admission control (office, school, hospital …)Logistics managementGate for ski lift, parkExhibition (explanation)Check-in baggage control…

RF-ID, RF-TAG, IC card, sensor network…

© T. Kuroda (17/50)http://www.research.philips.com/InformationCenter/Global/FArticleSummary.asp?lNodeId=712

Ambient Intelligence

© T. Kuroda (18/50)

Ubiquitous Computing

High-endServer

Internet Broadband

Things that think and talkfor better HCI

Wearable,Implantable

Backbone <<upgrading>>

Low power Low cost

Wireless

Access Network<<downsizing>>

Invisible Computers*

* “The most profound technologies are those that disappear. They weave themselves into the fabric of everyday life until they are indistinguishable from it.”Mark Weiser, “The Computer for the 21st Century,”Scientific American, 265 (3), pp.94-104, 1991.

© T. Kuroda (19/50)

Research Scope

© T. Kuroda (20/50)

Computer Recognizes HumansCamera detects human: AF, AE, AZ, Security …

Genetic Algorithm (SW) and Dedicated LSI (HW)

Y. Hori and T. Kuroda et al., Symp. On VLSI Circuits 2006

© T. Kuroda (21/50)

Head Counting (Passers-by)

Answer: 15 people

© T. Kuroda (22/50)

Head Counting (Crowd)

Answer: 499 people

© T. Kuroda (23/50)

ApplicationsAutomatic focus, exposure, zoom in digital still/video camera for shooting beautiful photo/video.Automatic recoding in an Exif file who’s in picture for enabling search.Homing still/video camera e.g. in an athletic festival.Head counting of passers-by for collecting marketing information and security usages.Remote control of digital consumer products by using finger sign.Sign language translation.Ideal airbag opening by calculating acceleration of people in collision accident.

© T. Kuroda (24/50)

Ubiquitous ElectronicsPr

oces

sor c

ount

per

per

son

1950 1960 1970 1980 1990 2000 2020Year

Large scale

Office / middle

WS

PC

historicalVac. tube

Transistor

IC

LSI

VLSI

0.001

0.01

0.1

1

10

100

Embedded

UbiquitousComputing

System LSI

1000SiP

Electronics is part of environments enhancing convenience and security of daily life.

People use electronics consciously.

AmbientElectronics

Ubiquitous devices

2010

Everybody

Everywhere

Unaware

© T. Kuroda (25/50)

Sensor Network

MIT Media Lab Responsive Environment (Joseph Paradiso)Ambient Intelligence Group (Pattie Maes)Human Dynamics (Sandy Pentland)Affective Computing (Rosalind Picard)

ESP (Emotional Social Intelligence Prosthesis)

© T. Kuroda (26/50)

Sensor-Net

Life microscope

出典：矢野和男「センサとは何か」ウェブを越えるそのインパクトwww.hitachihyoron.com/2006/09/pdf/09_Professional.pdf

© T. Kuroda (27/50)

Computing Paradigm ShiftShift toward fine-grained, distributed interfaces

• Ubiquitous Computing (PARC/Weiser) • Things That Think (MIT)• Disappearing Computer (EU)• Invisible Computing (Microsoft)• Pervasive Computing (IBM)• Paintable Computing (MIT)• Pushpin Computing (MIT)

© T. Kuroda (28/50)

Decentralized Information Exchange by Aroma

50m

Cs

Cn1

②

30m

60m

①

③

④

Cn2

S. Miura, T. Kuroda et al., "Evaluation of Parking Search using Sensor Network," IEEE International Symposium on Wireless Pervasive Computing, Jan. 2006.

8

0 60 120 180 240 300 360 420 480 540

6

4

2

10

Cars

Sear

ch T

ime

(min

)

8

With Aroma

0 60 120 180 240 300 360 420 480 540

6

4

2

10

Random Search

Cars

Sear

ch T

ime

(min

)With Volatile Aroma

© T. Kuroda (29/50)

CMOS Impulse Radio (1Mbps, 1mW)

Transmitter

LNA & clocked correlator

Delay controller

Technology: 0.18µm CMOSLayout area

Transmitter: 0.04mm2

Receiver: 0.38mm2

Transmitter

Receiver

DataClock

ImpulseGenerator

DataClock

ImpulseGenerator

Clocked CorrelatorData

ClockRanging

LNA∫

TemplateGenerator

DelayController

Data

ClockRanging

LNA∫

TemplateGenerator

DelayController

All digital

T. Terada et al., “A CMOS Impulse Radio Ultra-Wideband Transceiver for 1Mb/s Data Communications and ±2.5cm Range Findings ” Symp. on VLSI circuits, 2005.

Tx:Buffer

LNA

mixer and amplifier

Total0.82mW

Total5.3mW

Continuous

On-Off

Tx:Buffer

LNA Switching

SignalV

V

ON OFF ON

92ns8ns 8ns

LNA

mixer and amplifier

Total5.3mW

© T. Kuroda (30/50)

Extremely Low Power Radio Station

(b) Measured spectrum of received signals

(a) Measured waveforms of transmitted and received signals

Transmitted signal Received signal

Elec

tric

field

inte

nsity

(V/m

)

Frequency (GHz)

10-6

10-5

10-4

10-3

0 0.5 1

Regulation forthe extremely low power radio station

2ns

20mV

2ns

800mV

(b) Measured spectrum of received signals

(a) Measured waveforms of transmitted and received signals

Transmitted signal Received signalTransmitted signal Received signal

Elec

tric

field

inte

nsity

(V/m

)

Frequency (GHz)

10-6

10-5

10-4

10-3

0 0.5 1


Elec

tric

field

inte

nsity

(V/m

)

Frequency (GHz)

10-6

10-5

10-4

10-3

0 0.5 1


2ns

20mV

2ns

800mV

10-4

10-2

10-0

60 80 100 120Distance (cm)

Bit e

rror

rate

10-6

VDD.TX=2.5VVDD.TX=1.8V

10-4

10-2

10-0

60 80 100 120Distance (cm)

Bit e

rror

rate

10-6

VDD.TX=2.5VVDD.TX=1.8V

Rea

l dis

tanc

e–

mea

sure

d di

stan

ce (c

m)

Real distance (cm)

-3

0

3

80 1006040200

+2.5cm

-2.5cm

Rea

l dis

tanc

e–

mea

sure

d di

stan

ce (c

m)

Real distance (cm)

-3

0

3

80 1006040200

+2.5cm

-2.5cm

±2.5cm Range Findings, 0.7nJ

© T. Kuroda (31/50)

Historic Change in 100 YearMarconi's first transatlantic wireless experiment by spark gap: Baseband pulse steamsAdvanced electronics carrier modulationAfter one century, back to the pulse-based communication

Heinrich Rudolph Hertz

Hertz’s Experiment, Karlsruhe Univ. 1888

Guglielmo Marconi

Marconi's First Transatlantic Wireless Experiment 12/12/1901

St. John's, Newfoundland, USA

© T. Kuroda (32/50)

Short-Range Wireless (10cm-10µm)

Intelligent Tires Wireless Assembly

Giant Window of Opportunity

Source: Jan Rabaey, UCB

© T. Kuroda (33/50)

Memory Bus

Trend of Chip Performance and Pin Bandwidth

Chip Performance

Year70 80 90 00 10

4004

8086

286

Intel386

Intel486

Pentium

Pentium4

X1.70 / year

100

MIP

S [i

nstr

uctio

n/s]

0.01

0.1

1

10

1000

10000

100000

1000000

Pin Bandwidth Data R

ate [MB

/s]

1

10

100

1000

10000

Bus on BoardATA (HDD)

Ethernet

ISA

PCI

PCI-EXSerial ATA

X1.44 / year

Fast Ethernet

Courtesy: Intel, Fujitsu Lab

© T. Kuroda (34/50)

The Gap Is Caused by Topological Difference

TRANSISTOR Scaling Per yearGate length [x] 0.87Voltage [V] 0.87Capacitance [c]~[x2/x] 0.87Current [i]~[v2/x] 0.87Speed [i/cv] 1.15

WIREWire pitch [x] 0.87Chip size [s] 1.06Tracks [t]~[s/x] 1.22Grids [g]~[t2] 1.49

Rent’s rule:Bandwidth demand from a module withcapacity C (grids*speed) grows as C0.7.Required pin bandwidth: x1.45/year

Pin bandwidth1.15 (Speed) x 1.11 (Pin #) = x1.28/year

Periphery

Chip performance1.15 (Speed) x 1.49 (Grids) = x1.71/year

Area

Moore’s Law

Chip perform

ance : 1.71/year

Pin bandwidth : 1.45/year

Scaling:1.28/year

circuitinnovation

Year

Dat

a R

ate

© T. Kuroda (35/50)

Challenges in Wireline Link

’96 ’98 ’00 ’02 ’04 ’06

100G

1T

Dat

a R

ate

[b/s

]

Year’ ’ ’ ’ ’ ’’ ’ ’ ’ ’ ’’ ’ ’ ’ ’ ’

1G

10G

Speed-wall

Stanford (1ch)

Stanford (1ch)

NEC (1ch)

Power/Area-wall

Toshiba(4ch,4W)

Rambus(26ch)

NTT(16ch,8W)

Hotrail(32ch)

NEC (4ch,5W)

NEC (21ch,3W)

NEC (20ch,8W)

TI (20ch,6W)

Intel (32ch,15W)

IBM,Sony,Toshiba (48ch,6W)

Hitachi(1024ch,12W)

© T. Kuroda (36/50)

SoC Improves I/O PerformanceSeparate

chips 891mW

240mW

DRAMLogic & memory

Embedded

DRAMPower 16Mbit

DRAM

Speech codec

Multiplexer

MPEG-4 VideoCodec

HostI/F

DRAM

I/F

PLLCamI/F

DisplayI/F

Pre-filter

VTVT

VT VT

MPEG4 codec

DRAM - logic interface

70% power reduction by DRAM embedding technology

Courtesy: Toshiba

© T. Kuroda (37/50)

DRAM

PC Board

Package

PCBDRAM

SRAM

Analog

CPU

Connection

DRAM

PC Board

Package

PCBDRAM

SRAM

Analog

CPU

Connection DRAM SRAM

Analog CPU

DRAM SRAM

Analog CPU

From SoC to SiPSystem-on-a-Board

CPU

SRAM DRAM

Analog

CPU

SRAM DRAM

Analog

Lower Cost, QTAT

Low power, High speed

System-in-a-Package (SiP)

System-on-a-Chip (SoC)

Mas

k Se

t Cos

t [M

$]

0

0.5

1

1.5

2

2.5

0.4 0.25 0.2 0.180.15 0.13 90n65n0

0.5

1

1.5

2

2.5

0.4 0.25 0.2 0.180.15 0.13 90n65n0

0.5

1

1.5

2

2.5

0.4 0.25 0.2 0.180.15 0.13 90n65n

Generation [µm]Source: Intel

ASIC

ASSP

02000400060008000100001200014000

2000 2001 2002Year

Des

ign

star

ts

ASIC

ASSP

02000400060008000100001200014000

2000 2001 2002Year

Des

ign

star

ts

Number of design starts is declining from 1997.

Source: EE Times

© T. Kuroda (38/50)

CANDE Prediction in 2010CANDE 5-Year predictions from 2005 (to be reviewed in 2010) were: 1) IC-Package CAD will be a part of standard design flow 2) India and China will have more EDA startups than U.S.3) Analog Designers will still resist high-level models and languages 4) A complete Open Source RTL-GDS tool flow will exist5) Nearly all EDA tools will take advantage of multi-processors 6) Fewer than 200 commercial chips released in 45 nm technology7) No practical nanotech computing products 8) SPICE-type simulators will still be the workhorse of analog designs 9) Moore's law will be dead

10) System in Package will boom

The CANDE （Computer-Aided Network DEsign）Committee is a technical activity of the IEEE Circuits and Systems Society and IEEE Council on Electronic Design Automation which acts as a working group for electronic computer-aided design. The first CANDE Workshop was held in 1972, organized by Steve Director.http://www.ics.uci.edu/%7Ergupta/cande/predictions.html

© T. Kuroda (39/50)

CANDE Prediction : Actual PerformanceCANDE PREDICTIONS – as rated at the 2001 CANDE WorkshopResults: 19 came true, 4 partially, 15 did notKey: Blue – Correct (not necessarily in 5 years) Green – Did occur partially Red – Did not occur

1986 (6 came true, 1 partially, 3 did not)○ 1. UNIX will be the dominant operating system× 2. General Purpose Parallel machines will replace today’s computers; they will be

designed for high performance on major CAD algorithms (e.g. SPICE, Logic Synthesis, Fault Simulation, Simulated Annealing, Device Simulation)

△ 3. The big problem for CAD will become the validation of specifications× 4. The major developments in CAE/CAD will be in the environments for users○ 5. The test problem will still be considered NP-hard, boring, and unsolved○ 6. Many CAD tools will finally use hierarchy effectively× 7. General silicon compiler not developed yet but targeted silicon compiler for DSP

and other specific applications will be in general use○ 8. SPICE will still be the standard circuit simulator○ 9. CAD Tools will increasingly take into account statistical fluctuations in the

manufacturing process○ 10. Full hand-crafted custom will still be an important part of design

1979 (4 came true, 1 partially, 3 did not)× 1. Design System will be a Network Formed With Dedicated Processors For

Specific Functions× 2. Heavy Emphasis on Testability and Test Generation During the Design Phase○ 3. Integrated Verification Tools for Checking at Each Step in the Design Cycle○ 4. Much Greater Use of Canonical Circuit Forms (PLA, ROM) Via Design Aids○ 5. The Design Station is Highly Interactive for all Phases and Includes Graphics△ 6. Sets of Compatible Software will be Used for Design and Verification△ 7. Circuit and Process Simulation Programs are Closely Linked to an Ongoing

Process Data Storage System× 8. Layout will be Manipulated in Symbolic Form

1996 (4 came true, 1 partially, 5 did not)× 1. Windows NT will be the only OS for commercially viable CAD applications× 2. X86 machines will ship as more than 50% of EDA platforms× 3. More than 80% of the CAD effort will be directed toward software and “FPGA”-based

programmable hardware○ 4. EDA companies will distribute all their products (tools, libraries, etc,) on the Internet△ 5. The hardware/software co-design problem will have become the driving system-level

problem× 6. “Pay per use” EDA tools will be in widespread use○ 7. Tool suites for mainstream designers will be a significant fraction of total EDA○ 8. Portable voltage will be 1.8 – 1.2 V, driving significant new circuit design and EDA

challenges× 9. The IP crisis will be solved by an open IP industry and a mix-and-match standard○ 10. Software will have become 60 to 80 % of the overall cost of an embedded system

1991 (5 came true, 1 partially, 4 did not)○ 1. Hardware/software co-design will be one of the most important design problems○ 2. Support will still be the biggest hidden cost for both CAD vendors and customers× 3. MCM CAD becomes a reality× 4. MCM will enable new CAD and semiconductor businesses△ 5. Internal CAD will make a come-back○ 6. There will be tools for validation of specifications× 7. Partitioning will emerge as a commercial product○ 8. The telecommunications industry will provide the most challenging problems in CAD○ 9. SPICE algorithms still dominate circuit simulation× 10. Frameworks will be provided by computer vendors

http://www.ics.uci.edu/%7Ergupta/cande/predictions.html

© T. Kuroda (41/50)

From Periphery to Area

MPU

Memories

Sensor / RF / Analog

Bonding (Conv.) Through Si Via (Future)(+) area contact：

large # of connections（~10000）short distance（~0.1mm）

(-) expensive process / reliability issue(-) low yield due to Known Good Die

issue : difficult to test in fine pitch(-) scaling limit due to mechanical

contacts （~10µm pitch）

(+) low cost, practical(-) peripheral contact：

small # of connections（~100）

long distance（~10mm）

© T. Kuroda (42/50)

From Mechanical to Electrical

TSV Wireless Interface

Proposalwireless transceiver arrays

(-) process(-) KGD(-) scaling limit

(+) no addition in process, no reliability issue(+) KGD solvable : easy to attach and remove(+) high density channels (below 10µm pitch)(+) 3D scaling scenario (thinning a chip)(+) channels through active devices (+) low power : no ESD protection required

© T. Kuroda (43/50)

Communication Bottleneck Resolved in SiP

DRAM

SRAMAnalog CPU

DRAM

SRAMAnalog CPU

DRAM

PC Board

Package

PCB

DRAM

SRAM

Analog

CPU

Connection

DRAM

PC Board

Package

PCB

DRAM

SRAM

Analog

CPU

Connection

Chip perform

ance : 1.71/year


Scaling:1.28/year

circuitinnovation

Year

Dat

a R

ate

Chip perform

ance : 1.71/year


Year

Dat

a R

ate

Electrical Area Interface for 3D Integrati

© T. Kuroda (44/50)

Area Interface for 3D Integration

Thru

Si V

iaCapacitiveCoupling [3]

Wired Wireless2

Chi

ps(F

ace-

to-F

ace)

Ove

r 3-S

tack

ed

Chi

ps

[2][1] Ezaki (ISSCC’04) [2] Burns (ISSCC’01) [3] Kanda (ISSCC’03) [4]Mizoguchi (ISSCC’04)

Micro-Bump [1]

InductiveCoupling [4]

© T. Kuroda (45/50)

Infinitive Possibility in LSIIntegration 4x / 3yrs

0.3B transistor in 2003 (> American Population: 0.3B)7.5B transistor in 2007 (> World Population: 6B)30B transistor in 2010 (> Neuron in Human Brain: 14B)

LSI will evolve beyond your imagining and create future society and civilization. The real thrill in investigating LSI can be found in making dreams of future civilization come true. Although LSI is called as “rice of industry”, market size of semiconductor industry is still only 0.5% of GWP (cf. 3% in automotive industry). Percentage of market size of semiconductors in electronic equipments is less than 20%. Semiconductor is a new technology, only 50 year old from establishment of Feachild by R.Noyce and G.Moore. The market has not digested it yet. Even if CMOS scaling will slow down, there is large room for semiconductor industry to continue to develop.

© T. Kuroda (46/50)

“Optimism is an essential ingredient for innovation. How else can the individual welcome change over security, adventure over staying in safe place?”

Robert Noyce

“The best way to predict the future is to invent it.”

Alan Kay

Create Bright Future

© T. Kuroda (47/50)

Demand of New AgeKnow How -> Know What -> Know Who

’90s : Know how to make (craftsman)’00s : Know what to make (visionary)Future : Know who to work together (producer)

human circuit will be valuableDevice -> Circuit / System -> Business

System design (total design) Business power (for plan and proposal)

Role of AcademiaSpecialize and segmentalized disciplines -> Interdisciplinary and integrated knowledge

© T. Kuroda (48/50)

Summary (1)Challenges and opportunities in system LSI are discussed in 3 perspectives: device, integrated circuit, application and business.Scaling of CMOS integrated circuits is becoming very difficult, due to rapid increase in power dissipation.Post-CMOS device for mass production is not on the horizon. Even though speed of technologyimprovement may be slowed down compared to that before, the semiconductor industry and technology will continue to develop and improve remarkably. We will be entering the golden era of opportunities for both technology and industry.10 tips for low-power CMOS design are introduced.(revisit in Lecture 4 and 5)

© T. Kuroda (49/50)

Summary (2)Computers and communications will be scaled further, merged together, and materialized in consumer (human centric) applications.Computers will be small terminals that are implanted in every thing. They will be connected to a network by short-range wireless technologies. In order to make this ubiquitous electronics possible, intelligent interface based on low-power, high-speed CMOS design is inevitable.Conventional CMOS interface is facing speed-wall, power-wall, and area-wall.Opportunity in CMOS impulse radio for short-range communications (historical change) is discussed.

© T. Kuroda (50/50)

Summary (3)Inductive/capacitive-coupling inter-chip link for 3D SiP integration is introduced as emerging technology.(further discussion in Lecture 6 & 7)Integrated design engineering through system, circuit, device, process, lithography, and packaging, will be essential, as well as extended learning and knowledge. The era transited from ‘Know-How (craftsman’s age)’ to ‘Know-What (visionary’s age)’, and will transit to ‘Know-Who (producer’s age)’.

lecture 3: challenges and opportunities in system lsi (2...

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