lecture 3 inverters and combinational logiccas.ee.ic.ac.uk/people/kostas/web page material/lecture...
TRANSCRIPT
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Lecture 3 - 1Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Lecture 3
Inverters and Combinational Logic
Konstantinos MasselosDepartment of Electrical & Electronic Engineering
Imperial College London
URL: http://cas.ee.ic.ac.uk/~kostasE-mail: [email protected]
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Lecture 3 - 2Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Based on slides/material by…
P. Cheung http://www.ee.ic.ac.uk/pcheung/teaching/ee4_asic/index.html
J. Rabaey http://bwrc.eecs.berkeley.edu/Classes/IcBook/instructors.html“Digital Integrated Circuits: A Design Perspective”, Prentice Hall
D. Harris http://www.cmosvlsi.com/coursematerials.htmlWeste and Harris, “CMOS VLSI Design: A Circuits and Systems Perspective”, Addison Wesley
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Lecture 3 - 3Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Recommended Reading
J. Rabaey et. al. “Digital Integrated Circuits: A Design Perspective”: Chapter 5 (5.1 – 5.3), Chapter 6
Weste and Harris, “CMOS VLSI Design: A Circuits and Systems Perspective”: Chapter 2 (2.5), Chapter 6 (6.1, 6.2)
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Lecture 3 - 4Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Outline
CMOS Inverter• response• delays
Logic gates• Static CMOS
Conventional Static CMOS LogicRatioed LogicPass Transistor/Transmission Gate Logic
• Dynamic CMOSDominonp-CMOS
Tristates and Multiplexers
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Lecture 3 - 5Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
The CMOS Inverter: A First Glance
VDD
Vin Vout
CL
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Lecture 3 - 6Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
CMOS Inverters
Polysilicon
InOut
Metal1
VDD
GND
PMOS
NMOS
1.2 μm=2λ
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Lecture 3 - 7Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Inverter DC Response
DC Response: Vout vs. Vin for a gateInverter• When Vin = 0 -> Vout = VDD
• When Vin = VDD -> Vout = 0In between, Vout depends on transistor size and currentBy KCL, must settle such that Idsn = |Idsp|Transfer function can be found by solving equations, but graphical solution gives more insightCurrent depends on region of transistor behavior (cutoff, linear, saturation)
Idsn
Idsp Vout
VDD
Vin
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Lecture 3 - 8Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
nMOS Operation
Cutoff Linear Saturated
Vgsn < Vtn
Vin < Vtn
Vgsn > Vtn
Vin > Vtn
Vdsn < Vgsn – Vtn
Vout < Vin - Vtn
Vgsn > Vtn
Vin > Vtn
Vdsn > Vgsn – Vtn
Vout > Vin - Vtn
Idsn
Idsp Vout
VDD
Vin
Vgsn = Vin
Vdsn = Vout
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Lecture 3 - 9Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
pMOS Operation
Cutoff Linear Saturated
Vgsp > Vtp
Vin > VDD + Vtp
Vgsp < Vtp
Vin < VDD + Vtp
Vdsp > Vgsp – Vtp
Vout > Vin - Vtp
Vgsp < Vtp
Vin < VDD + Vtp
Vdsp < Vgsp – Vtp
Vout < Vin - Vtp
Idsn
Idsp Vout
VDD
Vin
Vgsp = Vin - VDD
Vdsp = Vout - VDD
Vtp < 0
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Lecture 3 - 10Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Operating Regions
CVout
0
Vin
VDD
VDD
A B
DE
Vtn VDD/2 VDD+Vtp
Region nMOS pMOSA Cutoff Linear
B Saturation Linear
C Saturation Saturation
D Linear Saturation
E Linear Cutoff
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Lecture 3 - 11Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Load Line Analysis
Current vs Vout, VinFor a given Vin:• Plot Idsn, Idsp vs. Vout
• Vout must be where |currents| are equal in
Vin5
Vin4
Vin3
Vin2Vin1
Vin0
Vin1
Vin2
Vin3Vin4
Idsn, |Idsp|
VoutVDD
Idsn
Idsp Vout
VDD
Vin
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Lecture 3 - 12Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
DC Transfer Curve
Transcribe points onto Vin vs. Vout plot
Vin5
Vin4
Vin3
Vin2Vin1
Vin0
Vin1
Vin2
Vin3Vin4
VoutVDD
CVout
0
Vin
VDD
VDD
A B
DE
Vtn VDD/2 VDD+Vtp
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Lecture 3 - 13Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Beta Ratio
Exact switching point depends on βp / βn
If βp / βn ≠ 1, switching point will move from VDD/2Otherwise:
Vout
0
Vin
VDD
VDD
0.51
2
10p
n
ββ
=
0.1p
n
ββ
=
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Lecture 3 - 14Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Noise Margins
How much noise can a gate input see before it does not recognize the input?
IndeterminateRegion
NML
NMH
Input CharacteristicsOutput Characteristics
VOH
VDD
VOL
GND
VIH
VIL
Logical HighInput Range
Logical LowInput Range
Logical HighOutput Range
Logical LowOutput Range
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Lecture 3 - 15Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Logic Levels
To maximize noise margins, select logic levels at • unity gain point of DC transfer characteristic
VDD
Vin
Vout
VOH
VDD
VOL
VIL VIHVtn
Unity Gain PointsSlope = -1
VDD-|Vtp|
βp/βn > 1
Vin Vout
0
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Lecture 3 - 16Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Transient Response
DC analysis tells us Vout if Vin is constantTransient analysis tells us Vout(t) if Vin(t) changes• Requires solving differential equations
Input is usually considered to be a step or ramp• From 0 to VDD or vice versa
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Lecture 3 - 17Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Inverter Step Response
Ex: find step response of inverter driving load cap
0
0
( )( )
( )
(
(
)
)
DD
DD
loa
d
ou
i
d
t
o
n
ut sn
VV
u t t Vt t
V tV
ddt C
t
I t
= −=
= −
<
( )0
22
0
2)
)( ( )
( DD DD t
DD
out
outout out D t
n
t
ds
D
I V
t t
V V V V
V V V VV
tV t V t
β
β
⎧≤⎪
⎪= − > −⎨⎪ ⎛ ⎞− − < −⎪ ⎜ ⎟
⎝ ⎠⎩
Vout(t)
Vin(t)
t0t
Vin(t) Vout(t)Cload
Idsn(t)
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Lecture 3 - 18Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Ideal Inverter
Vin
Vout
g=−∞
Ri = ∞
Ro = 0
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Lecture 3 - 19Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Voltage Transfer Characteristic of Real Inverter
0.0 1.0 2.0 3.0 4.0 5.0Vin (V)
1.0
2.0
3.0
4.0
5.0V
out (
V)
VMNMH
NML
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Lecture 3 - 20Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Outline
CMOS Inverter• response• delays
Logic gates• Static CMOS
Conventional Static CMOS LogicRatioed LogicPass Transistor/Transmission Gate Logic
• Dynamic CMOSDominonp-CMOS
Tristates and Multiplexers
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Lecture 3 - 21Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Delay Definitions
tpHL tpLH
t
t
Vin
Vout
50%
50%
tr
10%
90%
tf
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Lecture 3 - 22Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Impact of Rise Time on Delay
t pH
L(ns
ec)
0.35
0.3
0.25
0.2
0.15
trise (nsec)10.80.60.40.20
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Lecture 3 - 23Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Simulated Inverter Delay
Solving differential equations by hand is too hardSPICE simulator solves the equations numerically• Uses more accurate I-V models too!
But simulations take time to write
(V)
0.0
0.5
1.0
1.5
2.0
t(s)0.0 200p 400p 600p 800p 1n
tpdf = 66ps tpdr = 83psVin Vout
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Lecture 3 - 24Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Delay Estimation
Need to easily estimate delay• Not as accurate as simulation• But easier to ask “What if?”
The step response usually looks like a 1st order RC response with a decaying exponential.Use RC delay models to estimate delay• C = total capacitance on output node• Use effective resistance R• So that tpd = RC
Characterize transistors by finding their effective R• Depends on average current as gate switches
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Lecture 3 - 25Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
RC Delay Models
Use equivalent circuits for MOS transistors• Ideal switch + capacitance and ON resistance• Unit nMOS has resistance R, capacitance C• Unit pMOS has resistance 2R, capacitance C
Capacitance proportional to widthResistance inversely proportional to width
kgs
dg
s
d
kCkC
kCR/k
kgs
dg
s
d
kC
kC
kC
2R/k
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Lecture 3 - 26Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Computing the Capacitances
VDD VDD
VinVout
M1
M2
M3
M4Cdb2
Cdb1
Cgd12
Cw
Cg4
Cg3
Vout2
Fanout
Interconnect
VoutVin
CLSimplified
Model
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Lecture 3 - 27Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Computing the Capacitances
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Lecture 3 - 28Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Delay as a function of VDD
0
4
8
12
16
20
24
28
2.00 4.001.00 5.003.00
Nor
mal
ized
Del
ay
VDD (V)
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Lecture 3 - 29Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Outline
CMOS Inverter• response• delays
Logic gates• Static CMOS
Conventional Static CMOS LogicRatioed LogicPass Transistor/Transmission Gate Logic
• Dynamic CMOSDominonp-CMOS
Tristates and Multiplexers
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Lecture 3 - 30Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Digital Gates Fundamental Parameters
FunctionalityReliability, RobustnessAreaPerformance• Speed (delay)• Power Consumption• Energy
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Lecture 3 - 31Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Fan-in and Fan-out
N
M
(a) Fan-out N
(b) Fan-in M
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Lecture 3 - 32Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Combinational vs. Sequential Logic
Logic
Circuit
Logic
CircuitOut
OutInIn
(a) Combinational (b) Sequential
State
Output = f(In) Output = f(In, Previous In)
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Lecture 3 - 33Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Outline
CMOS Inverter• response• delays
Logic gates• Static CMOS
Conventional Static CMOS LogicRatioed LogicPass Transistor/Transmission Gate Logic
• Dynamic CMOSDominonp-CMOS
Tristates and Multiplexers
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Lecture 3 - 34Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Static CMOS Circuit
At every point in time (except during the switching transients) each gate output is connected to either Vdd or Vss via a low-resistive path. The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.
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Lecture 3 - 35Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Static CMOS
VDD
VSS
PUN
PDN
In1In2In3
F = G
In1In2In3
PUN and PDN are Dual Networks
PMOS Only
NMOS Only
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Lecture 3 - 36Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
NMOS Transistors in Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signalNMOS switch closes when switch control input is high
X Y
A B
Y = X if A and B
X Y
A
B Y = X if A OR B
NMOS Transistors pass a “strong” 0 but a “weak” 1
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Lecture 3 - 37Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
PMOS Transistors in Series/Parallel Connection
X Y
A B
Y = X if A AND B = A + B
X Y
A
B Y = X if A OR B = AB
PMOS Transistors pass a “strong” 1 but a “weak” 0
PMOS switch closes when switch control input is low
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Lecture 3 - 38Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Complementary CMOS Logic Style Construction
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Lecture 3 - 39Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
NAND Gate
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Lecture 3 - 40Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
NOR Gate
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Lecture 3 - 41Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Complex Gates
VDD
AB
C
D
DA
B C
OUT = D + A• (B+C)
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Lecture 3 - 42Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
4-input NAND Gate
In3
In1
In2
In4
In1 In2 In3 In4
VDD
Out
In1 In2 In3 In4
Vdd
GND
Out
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Lecture 3 - 43Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Standard Cell Layout Methodology
VDD
VSS
Well
signalsRouting Channel
metal1
polysilicon
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Lecture 3 - 44Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Two Versions of (a+b).c
a c b a b c
xx
GND
VDDVDD
GND
(a) Input order {a c b} (b) Input order {a b c}
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Lecture 3 - 45Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Logic Graph
VDD
c
a
x
b
ca
b
GND
x
VDDx
c
b a
i
j
i
jPDN
PUN
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Lecture 3 - 46Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Consistent Euler Path
GND
x
VDDx
c
b a
i
j
{ a b c}
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Lecture 3 - 47Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Example: x = ab+cd
GND
x
a
b c
d
VDDx
GND
x
a
b c
d
VDDx
(a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d}
a c d
x
VDD
GND
(c) stick diagram for ordering {a b c d}b
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Lecture 3 - 48Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Properties of Complementary CMOS Gates
High noise margins: VOH and VOL are at VDD and GND, respectively.
No static power consumption:There never exists a direct path between VDD and VSS (GND) in steady-state mode.
Comparable rise and fall times:(under the appropriate scaling conditions)
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Lecture 3 - 49Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Transistor Sizing
VDD
AB
C
D
DA
B C
12
22
6
612
12
F
• for symmetrical response (dc, ac)• for performance
Focus on worst-case
Input Dependent
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Lecture 3 - 50Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Propagation Delay Analysis - The Switch Model
VDDVDDVDD
CL
F CL
CL
F
F
RpRp Rp Rp
Rp
Rn
Rn
Rn Rn Rn
AA
A
AA
A
B B
B
B
(a) Inverter (b) 2-input NAND (c) 2-input NOR
tp = 0.69 Ron CL
(assuming that CL dominates!)
= RON
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Lecture 3 - 51Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
What is the Value of Ron?
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Lecture 3 - 52Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Analysis of Propagation Delay
VDD
CL
F
Rp Rp
Rn
Rn
A
A B
B
2-input NAND
1. Assume Rn=Rp= resistance of minimum sized NMOS inverter
2. Determine “Worst Case Input” transition(Delay depends on input values)
3. Example: tpLH for 2input NAND- Worst case when only ONE PMOS Pulls
up the output node- For 2 PMOS devices in parallel, the
resistance is lower
4. Example: tpHL for 2input NAND- Worst case : TWO NMOS in series
tpLH = 0.69RpCL
tpHL = 0.69(2Rn)CL
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Lecture 3 - 53Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Design for Worst Case
VDD
CL
F
A
A B
B
2
2
1 1
VDD
AB
C
D
DA
B C1
2
22
2
24
4
F
Here it is assumed that Rp = Rn
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Lecture 3 - 54Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Influence of Fan-In and Fan-Out on Delay
VDD
A B
A
B
C
D
C D
tp a1FI a2FI2 a3FO+ +=
Fan-Out: Number of Gates Connected2 Gate Capacitances per Fan-Out
FanIn: Quadratic Term due to:
1. Resistance Increasing2. Capacitance Increasing(tpHL)
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Lecture 3 - 55Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
tp as a function of Fan-In
1 3 5 7 9fan-in
0.0
1.0
2.0
3.0
4.0
t p (n
sec)
tpHL
tp
tpLHlinear
quadratic
AVOID LARGE FAN-IN GATES! (Typically not more than FI < 4)
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Lecture 3 - 56Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Fast Complex Gate - Design Techniques
• Transistor Sizing: As long as Fan-out Capacitance dominates
• Progressive Sizing:
CL
In1
InN
In3
In2
Out
C1
C2
C3
M1 > M2 > M3 > MN
M1
M2
M3
MN
Distributed RC-line
Can Reduce Delay with more than 30%!
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Lecture 3 - 57Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Fast Complex Gate - Design Techniques (2)
In1
In3
In2
C1
C2
CL
M1
M2
M3
In3
In1
In2
C3
C2
CL
M3
M2
M1
(a) (b)
• Transistor Ordering
critical pathcritical path
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Lecture 3 - 58Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Fast Complex Gate - Design Techniques (3)
• Improved Logic Design
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Lecture 3 - 59Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Fast Complex Gate - Design Techniques (4)
• Buffering: Isolate Fan-in from Fan-out
CLCL
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Lecture 3 - 60Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Ratioed Logic
VDD
VSS
PDNIn1In2In3
F
RLLoad
VDD
VSS
In1In2In3
F
VDD
VSS
PDNIn1In2In3
FVSS
PDN
Resistive DepletionLoad
PMOSLoad
(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS
VT < 0
Goal: to reduce the number of devices over complementary CMOS
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Lecture 3 - 61Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Pseudo-NMOS
The pull-up p-channel transistor is always conducting. • Disadvantages: high d.c. dissipation & slow rise time.
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Lecture 3 - 62Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Pseudo-NMOS NAND Gate
VDD
GND
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Lecture 3 - 63Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Improved Loads
VDD
VSS
PDN1
Out
VDD
VSS
PDN2
Out
AABB
M1 M2
Dual Cascode Voltage Switch Logic (DCVSL)
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Lecture 3 - 64Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Pass-Transistor LogicIn
puts Switch
Network
OutOut
A
B
B
B
• N transistors• No static consumption
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Lecture 3 - 65Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
NMOS-only switch
A = 5 V
B
C = 5 V
CL
A = 5 V
C = 5 V
BM2
M1
Mn
Threshold voltage loss causesstatic power consumption
VB does not pull up to 5V, but 5V - VTN
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Lecture 3 - 66Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Pass Transistor Logic with feedback
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Lecture 3 - 67Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Complementary Pass Transistor Logic
A
B
A
B
B B B B
A
B
A
B
F=AB
F=AB
F=A+B
F=A+B
B B
A
A
A
A
F=A⊕ΒÝ
F=A⊕ΒÝ
OR/NOR EXOR/NEXORAND/NAND
F
F
Pass-TransistorNetwork
Pass-TransistorNetwork
AABB
AABB
Inverse
(a)
(b)
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Lecture 3 - 68Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
4 Input NAND in CPL
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Lecture 3 - 69Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Transmission Gate
A B
C
C
A B
C
C
BCL
C = 0 V
A = 5 V
C = 5 V
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Lecture 3 - 70Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Pass Transistor XOR gate
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Lecture 3 - 71Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Outline
CMOS Inverter• response• delays
Logic gates• Static CMOS
Conventional Static CMOS LogicRatioed LogicPass Transistor/Transmission Gate Logic
• Dynamic CMOSDominonp-CMOS
Tristates and Multiplexers
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Lecture 3 - 72Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Dynamic Logic
Mp
Me
VDD
PDN
φ
In1In2In3
OutMe
Mp
VDD
PUN
φ
In1In2In3
φ
φ
Out
CL
CL
φp networkφn network
2 phase operation:• Evaluation
• Precharge
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Lecture 3 - 73Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Example
Mp
Me
VDD
φOut
φ
A
B
C
• N + 1 Transistors
• Ratioless
• No Static Power Consumption
• Noise Margins small (NML)
• Requires Clock
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Lecture 3 - 74Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Dynamic 4 Input NAND Gate
In1In2In3In4
Out
VDD
GNDφ
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Lecture 3 - 75Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Cascading Dynamic Gates
Mp
Me
VDD
φ
φ
Mp
Me
VDD
φ
φ
In
Out1 Out2
φ
Out2
Out1
In
V
t
ΔV
VTn
(a) (b)
Only 0→1 Transitions allowed at inputs!
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Lecture 3 - 76Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Domino Logic
Mp
Me
VDD
PDN
φ
In1In2In3
Out1
φ
Mp
Me
VDD
PDN
φ
In4
φ
Out2
Mr
VDD
Static Inverterwith Level Restorer
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Lecture 3 - 77Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Domino Logic - Characteristics
• Only non-inverting logic
• Very fast - Only 1->0 transitions at input of invertermove VM upwards by increasing PMOS
• Adding level restorer reduces leakage andcharge redistribution problems
• Optimize inverter for fan-out
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Lecture 3 - 78Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
np-CMOS
Mp
Me
VDD
PDN
φ
In1In2In3
φ
Me
Mp
VDD
PUN
φ
In4
φOut1
Out2
Only 1→0 transitions allowed at inputs of PUN
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Lecture 3 - 79Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
CMOS Circuit Styles - Summary
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Lecture 3 - 80Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Outline
CMOS Inverter• response• delays
Logic gates• Static CMOS
Conventional Static CMOS LogicRatioed LogicPass Transistor/Transmission Gate Logic
• Dynamic CMOSDominonp-CMOS
Tristates and Multiplexers
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Lecture 3 - 81Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Tristates
Tristate buffer produces Z when not enabled
EN A Y
0 0 Z
0 1 Z
1 0 0
1 1 1
A Y
EN
A Y
EN
EN
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Lecture 3 - 82Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Multiplexers
2:1 multiplexer chooses between two inputs
S D1 D0 Y
0 X 0 0
0 X 1 1
1 0 X 0
1 1 X 1
0
1
S
D0
D1Y
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Lecture 3 - 83Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Gate Level Mux Design
How many transistors are needed? 20
1 0 (too many transistors)Y SD SD= +
44
D1
D0S Y
4
2
22 Y
2
D1
D0S
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Lecture 3 - 84Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Transmission Gate Mux
Mux uses two transmission gates• Only 4 transistors
S
S
D0
D1YS
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Lecture 3 - 85Introduction to Digital Integrated Circuit DesignInverters and Combinational Logic
Summary
Inverter response and delays• Three main operating regions (cutoff, linear, saturation)• Noise margins• tpHL, tpLH, tf, tr
Logic design styles• Static (ignores transient effects during switching)
Conventional static CMOS (PUP, PDN networks)Ratioed logic (resistive load on top of PDN network)Pass transistors/transmission gates (one transistor per input/good 0 and 1 values)
• Dynamic (temporary stores signal values on capacitances of circuit nodes) Domino (cascaded dynamic gates connected through inverters) np-CMOS (cascaded dynamic gates with alternating networks)