lecture 30 perspectives -...

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Digital Integrated Circuits © Prentice Hall 2000Perspectives

Lecture 30

Perspectives


Administrivia

Final on Friday December 14, 2001 – 8 amLocation: 180 Tan HallTopics – all what was covered in class. Review Session - TBALab and hw scores to be posted on the web – please check if correct or if something is missingSuperb Job on Posters! FEEDBACK ON COURSE EXTREMELY WELCOME!

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Transistor Count

400480088080

8085 8086286

386486 Pentium ® proc

P6

0.001

0.01

0.1

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Tran

sist

ors

(MT)

900M

1.8B

425M200M

200M--1.8B transistors on the Lead Microprocessor

S. Borkar


18nm FinFETDouble-gate structure + raised source/drain

BOX Si fin - Body!

DrainSource

Gate

X. Huang, et al, 1999 IEDM, p.67~70

Gate

Silicon Fin

050

100150200250300350400

-1.5 -1.0 -0.5 0.0Vd [V]

I d[u

A/u

m]

-1.50 V

-1.00 V

-0.75 V

-0.50 V

-0.25 V

-1.25 V

3


Power DensityWith Vdd ~1.2V, these devices are quite fast. FO4 delay is <5psIf we continue with today’s architectures, we could run digital circuits at 30GHz

But - we will end up with 20kW/cm2 power density.Lower supply – to 0.6V, we are down to 5kW/cm2.Speeds will be a bit lower, too, FO4 = 10ps, lowering the frequencies to ~10GHz [Tang, ISSCC’01], and lowering powerAssume that a high performance DG or bulk FET can be designed with 1kW/cm2, with FO4 = 10ps [Frank, Proc IEEE, 3/01]


Power will be a problem

5KW 18KW

1.5KW 500W

4004800880808085

8086286

386486

Pentium® proc

0.1

1

10

100

1000

10000

100000

1971 1974 1978 1985 1992 2000 2004 2008Year

Pow

er (W

atts

)

Power delivery and dissipation will be prohibitive

S. Borkar

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Power is a Limiting Factor

If we have 2cm x 2cm die in a high-performance microprocessor, we will end up with 4kW power dissipation.If our power has to be limited to 180W, we can afford to have only 4.5% of these devices with 0.6V supply on the die, given that nothing else dissipates power.


Possible Scenario

Example: 0.5 % of devices will be of highest performance35% is leakage (assume: 20% drain, 10% gate, 5% drain-to-body)65% is active power, if just 0.5% of these CV2 = 13W, leakage 7WHow would other 99.5% devices that populate the 2cmx2cm die look like?

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Microprocessors

Today → 20nm

µPCore2GHz

Cache

µPCore

Cache

DedicatedLogic

7-10 GHz


Microprocessor DesignCore datapath will be running at 7 - 10GHzRequires fast devices, low thresholds with 0.5-0.6V suppliesLowest NMOS VTh ~ -0.1V to get swing in CMOS. Assume threshold of 0 – 0.1V. The devices will be very leaky, will use second threshold to control leakage power.With second threshold set to have 10x less leakage, 90% of devices off critical paths can be made high-threshold. Power limits the size of the µP core to 5-10% die (today’s transistor count, just shrunk), 30-50% of total power budget.

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Add Dedicated Datapath

Will run at 10x lower frequency, at 0.5-0.7 of the processor VDD= 0.25 - 0.35VThresholds for critical paths VTh = 150mVNeed leakage power management – another threshold or control of VT

Logic BlockFreq = 1Vdd = 1Throughput = 1Power = 1Area = 1 Pwr Den = 1

Vdd

Logic BlockFreq = 0.5Vdd = 0.5Throughput = 1Power = 0.25Area = 2Pwr Den = 0.125Leakage Curr. = 2

Vdd/2

Logic Block

Can execute e.g. DIVX decoder, graphics


180W Gives Us:

Power Area

µP Core

Dedicated datapath

Dedicated datapath

µP Core

Memory

Memory

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Memory

Density is the key requirementWill occupy 70-80% of the dieLow leakageLow activity – Inherently low active power, low power density (at least 10x less than logic)Need higher VTh ~ 0.5V, and higher supply 0.8-1V (?)


Systems-on-a-ChipToday → 20nm

Radio(60GHz (?), CMOS ?)

25M transistors, 3MB embedded SRAMMIPS core @ 100MHz, DSP @ 144MHz7 PLLs, 12 ADC, DACs, 100 clocks, 1.4W

Broadcom set-top box

2W

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Transistor Requirements

Will need different kinds of transistors:» Datapaths (speed, leakage)» Dedicated DSP (power, leakage)» Memory (density is main concern)» Analog (?)

Power and leakage determine the size ratios between these blocksNumber of different transistors types is determined by parameterspreadLess devices could solve the problem, but, need control of the threshold (4th terminal), with strong transfer function.


Today’s Design MethodologiesWill Not Scale Much Further

The Deep Sub-Micron (DSM) Effect (≤ 0.25µ)

“Microscopic Problems”• Wiring Load Management• Noise, Crosstalk• Reliability, Manufacturability• Complexity: LRC, ERC• Accurate Power Prediction• Accurate Delay Prediction• etc.

Everything Looks a Little Different

“Macroscopic Issues”• Time-to-Market• Millions of Gates• High-Level Abstractions• Reuse & IP: Portability• Predictability• etc.

…and There’s a Lot of Them!

∝ DSM ∝ 1/DSM

?

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The Productivity Gap

1Logi

c Tra

nsist

ors p

er C

hip

(K)

Prod

uctiv

ityTr

ans ./

Sta f

f -Mo

nth

10

100

1,000

10,000

100,000

1,000,000

10,000,000

10

100

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000Logic Transistors/Chip

Transistor/Staff Month

58%/Yr. compoundComplexity growth rate

21%/Yr. compoundProductivity growth rate

Source: SEMATECH

198 1

198 3

198 5

198 7

198 9

199 1

199 3

199 5

199 7

199 9

200 3

200 1

200 5

200 7

200 9

xx xx x

x

x

2.5µ

.10µ

.35µ


Implementation Methodologies

Digital Circuit Implementation Approaches

Custom Semi-custom

Cell-Based Array-Based

Standard Cells Macro Cells Pre-diffused Pre-wired(FPGA)Compiled Cells (Gate Arrays)

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Custom Design –Layout Editor

Magic Layout Editor(UC Berkeley)


Standard Cell - Example

3-input NAND cell(from Mississippi State Library)characterized for fanout of 4 andfor three different technologies

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Synthesis

1. Describe your circuit in HDL (VHDL, Verilog)2. Syntehsis programs map it into a standard cell

library. Set the constraints (timing, area)3. Get a gate level netlist – automatic place and route4. Insert clock5. Extract the netlist from layout6. Does it meet constraints? – go back to 1, 2, 3, 4.Called ‘Design closure’ – timing closure, power closure.


Gate Array — Sea-of-gates

rows of

cells

routing channel

uncommitted

VDD

GND

polysilicon

metal

possiblecontact

In1 In2 In3 In4

Out

UncommitedCell

CommittedCell(4-input NOR)

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Sea-of-gate Primitive Cells

NMOS

PMOS

Oxide-isolation

PMOS

NMOS

NMOS

Using oxide-isolation Using gate-isolation


Sea-of-gates

Random Logic

MemorySubsystem

LSI Logic LEA300K(0.6 µm CMOS)

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Prewired Arrays

Categories of prewired arrays (or field-programmable devices):Fuse-based (program-once)Non-volatile EPROM basedRAM based


Programmable Logic Devices

PLA PROM PAL

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EPLD Block Diagram

Macrocell

Courtesy Altera Corp.

Primary inputs


Field-Programmable Gate ArraysFuse-based

I/O Buffers

Program/Test/Diagnostics

I/O Buffers

I/O B

uffe

rs

I/O B

uffe

rs

Vertical routes

Rows of logic module sRouting channels

Standard-cell likefloorplan

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Interconnect

Cell

Horizontaltracks

Vertical tracks

Input/output pin

Antifuse

Programmed interconnection

Programming interconnect using anti-fuses


Field-Programmable Gate ArraysRAM-based

CLB CLB

CLBCLB

switching matrixHorizontalroutingchannel

Vertical routing channel

Interconnect point

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RAM-based FPGABasic Cell (CLB)

RQ1D

CE

RQ2D

CE

F

G

F

G

F

G

RDin

Clock

CE

F

G

AB/Q1/Q2C/Q1/Q2

D

AB/Q1/Q2C/Q1/Q2

D

E

Combinationa l logic Storage elements

An y function of up to 4 variab le s

An y function of u p to 4 variable s

Courtesy of Xilinx


RAM-based FPGA

Xilinx XC4025

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Addressing the Design Complexity IssueArchitecture Reuse

Reuse comes in generationsGe ne ration Re us e e le me nt Status

1s t Standard c e lls We ll e s tablis he d

2nd IP bloc ks Be ing introduc e d

3rd Arc hite c ture Eme rg ing

4th IC Early re s e arc h

Source: Theo Claasen (Philips) – DAC 00


Architecture ReUse

Silicon System Platform» Flexible architecture for hardware and software» Specific (programmable) components» Network architecture» Software modules» Rules and guidelines for design of HW and SW

Has been successful in PC’s» Dominance of a few players who specify and control architecture

Application-domain specific (difference in constraints)» Speed (compute power)» Dissipation» Costs» Real / non-real time data

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Platform-Based Design

A platform is a restriction on the space of possible implementation choices, providing a well-defined abstraction of the underlying technology for the application developerNew platforms will be defined at the architecture-micro-architecture boundaryThey will be component-based, and will provide a range of choices from structured-custom to fully programmable implementationsKey to such approaches is the representation of communication in the platform model

“Only the consumer gets freedom of choice;designers need freedom from choice”

(Orfali, et al, 1996, p.522)

Source:R.Newton


Design at a crossroadSystem-on-a-Chip

RAM

500 k Gates FPGA+ 1 Gbit DRAMPreprocessing

Multi-SpectralImager

µCsystem+2 GbitDRAMRecog-nition

Ana

log

64 SIMD ProcessorArray + SRAM

Image Conditioning100 GOPS

Embedded applications where cost, performance, and energy are the real issues!DSP and control intensiveMixed-modeCombines programmable and application-specific modulesSoftware plays crucial role

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EE 141 Summary

Digital CMOS design is well and kickingSome major challenges down the road caused by Deep Sub-micron» Super GHz design» Power consumption!!!!» Reliability – making it work» Device variationsSome new circuit solutions are bound to emerge

Who can afford design in the years to come? Some major design methodology change in the making!

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