lecture 5: pipelining implementation kai bu [email protected]
TRANSCRIPT
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Lab 1 Report Submissionhttp://10.78.18.200:8080/Platform/ Register with @zju.edu.cn email addrReport Due Date: March 28
Demo 70% + Report 30%
report template: http://list.zju.edu.cn/kaibu/comparch/Lab_report_template.doc
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Appendix C.3-C.4
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Data PathUnderneath Pipelining
IF ID EX MEM WB
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Outline
• Unpipelined MIPS• Pipelined MIPS• Other Pipelining Challenges
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Outline
• Unpipelined MIPS• Pipelined MIPS• Other Pipelining Challenges
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MIPS Instruction
• at most 5 clock cycles per instruction• IF ID EX MEM WB
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MIPS Instruction
IF ID EX MEM WB• Instruction Fetch cycle
IR ← Mem[PC];NPC ← PC + 4;
IR: instruction registerNPC: next sequential PC
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MIPS Instruction
IF ID EX MEM WB• Instruction Decode/register fetch
A ← Regs[rs];B ← Regs[rt];Imm ← sign-extended
immediate field of IR (lower 16 bits)
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MIPS Instruction
IF ID EX MEM WB• Execution/effective address cycle
ALU operates on the operands from ID:4 functions depending on the instr type -MMemory referenceemory reference-Register-register ALU instructionRegister-register ALU instruction-Register-immediate ALU instructionRegister-immediate ALU instruction-BranchBranch
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MIPS Instruction
IF ID EX MEM WB• Execution/effective address cycle
-Memory referenceMemory referenceALUOutput ← A + Imm;
ALU adds the operands
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MIPS Instruction
IF ID EX MEM WB• Execution/effective address cycle
-Register-register ALU instrRegister-register ALU instrALUOutput ← A func B;
ALU performs the operationspecified by function code on the value in register Aand on the value in register B
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MIPS Instruction
IF ID EX MEM WB• Execution/effective address cycle
-Register-Immediate ALU InstrRegister-Immediate ALU InstrALUOutput ← A op Imm;
ALU performs the operationspecified by opcode on the value in register Aand on the value in register Imm
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MIPS Instruction
IF ID EX MEM WB• Execution/effective address cycle
-BranchBranchALUOutput ← NPC + (Imm<<2);Cond ← (A == 0);
ALUOutput -> branch targetBEQZ: comparison against 0
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MIPS Instruction
IF ID EX MEM WB• MEMory access/branch completion
update PC for all instr: PC ← NPC;-Memory AccessMemory AccessLMD ← Mem[ALUOutput]; loadMem[ALUOutput] ← B; store-BranchBranchif (cond) PC ← ALUOutput;
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MIPS Instruction
IF ID EX MEM WB• Write-Back cycle
-Register-register ALU instructionRegister-register ALU instructionRegs[rd] ← ALUOutput;
-Register-immediate ALU instructionRegister-immediate ALU instructionRegs[rt] ← ALUOutput;
- Load instructionLoad instructionRegs[rt] ← LMD; LLoad MMemory DData reg
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Put It All Together
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MIPS Instruction
IF ID EX MEM WB
IR ← Mem[PC];NPC ← PC + 4;
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MIPS Instruction
IF ID EX MEM WB
A ← Regs[rs];B ← Regs[rt];Imm ← sign-extended immediate field of IR (lower 16 bits)
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MIPS Instruction
IF ID EX MEM WB
ALUOutput ← A + Imm;
ALUOutput ← A func B;
ALUOutput ← A op Imm;
ALUOutput ← NPC + (Imm<<2);Cond ← (A == 0);
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MIPS Instruction
IF ID EX MEM WB
LMD ← Mem[ALUOutput]; Mem[ALUOutput] ← B;
if (cond) PC ← ALUOutput;
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MIPS Instruction
IF ID EX MEM WB
Regs[rd] ← ALUOutput;
Regs[rt] ← ALUOutput;
Regs[rt] ← LMD;
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MIPS Instruction Demo
• Prof. Gurpur Prabhu, Iowa State Univ http://www.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/DLXimplem.html
• Load, Store• Register-register ALU• Register-immediate ALU• Branch
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Load
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Load
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Load
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Load
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Load
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Load
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Store
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Store
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Store
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Store
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Store
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Store
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Register-Register ALU
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Register-Register ALU
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Register-Register ALU
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Register-Register ALU
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Register-Register ALU
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Register-Register ALU
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Register-Immediate ALU
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Register-Immediate ALU
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Register-Immediate ALU
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Register-Immediate ALU
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Register-Immediate ALU
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Register-Immediate ALU
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Branch
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Branch
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Branch
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Branch
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Branch
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Branch
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Outline
• Unpipelined MIPS• Pipelined MIPS• Other Pipelining Challenges
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Pipelined MIPS
NPCIR
ABIMM
CondALUOutput
LMDPipelineRegisters/Latches
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Instruction Type decidesactions on a pipeline stage
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Pipelined MIPS: IF, ID
• The first two stages are independent of instruction type because the instruction is not decoded until the end of ID;
• PC update
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Pipelined MIPS: EX, MEM, WB
Any value needed on a later pipeline stage must be placed in a pipeline register,and copied from one pipeline register to the next,until it is no longer needed.
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Data Hazard
• Instruction Issue: ID -> EX• If a data hazard exists, the instruction
is stalled before it is issued.• For integer pipeline, data hazards and
forwarding can be checked during ID• Detect hazards by comparing the
destination and sources of adjacent instruction
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Data Hazard Example
• Data hazards from LoadComparison between the destination of Loadand the sources on the following two instr
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Stall
• Prevent instructions in IF and ID from advancing
• Change the control portion of ID/EX to be a no-op
• Recirculate the contents of IF/ID registers to hold the stalled instr
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Forwarding
• Data path: from the ALU or data memory output to the ALU input, the data memory input, or the zero detection unit.
• Compare the destination registers of EX/MEM.IR and MEM/WB.IR against the source registers of ID/EX.IR and EX/MEM.IR
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Example: forwarding result is an ALU input
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MEM
/WR
ID/E
X
EX
/MEM
DataMemory
ALU
mux
mux
Registe
rs
NextPC
Immediate
mux
Source sinkEX/Mem.ALUoutput ALU inputMEM/WB.ALUoutput ALU inputMEM/WB.LMD ALU input
Forwarding: hw change
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store
loadMEM/WB.LMD DM input
Forwarding: hw change
?
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Branch
• Move zero test to the ID stagewith an additional ADDer computing target address
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Outline
• Unpipelined MIPS• Pipelined MIPS• Other Pipelining Challenges
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Exceptions: Instruction Execution Order
• interrupt/fault/exception• When the normal execution order of
instruction is changed• May force CPU to abort the instructions
in the pipeline before they complete
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Exceptions
• TypeI/O device requestinvoking os service from user programtracing instruction executionbreakpointinteger arithmetic overflowFP arithmetic anomalypage faultmisaligned memory addressmemory protection violationusing undefined/unimplemented instructionhardware malfunctionspower failure
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Exceptions: Requirements
• Synchronous vs asynchronous• User requested vs coerced• User maskable vs user nonmaskable• Within vs between instructions• Resume vs terminate
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Instruction Set Complications
• Instruction set specific factors that make pipelining harder to implement
• PP. C-49 – C.51
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?