lecture 6 combinational arithmetic circuits

Lecture 6 Combinational Arithmetic

Circuits

Pradondet NilaguptaDepartment of Computer EngineeringKasetsart University

Wednesday, April 19, 2023 204222 Digital System Design

2

Acknowledgement

This lecture note is modified from EECC 341 – Introduction to Digital System for Computer Engineering from Dr. Muhammad Shaaban and ECE 303 Advanced Digital Design from Prof. Hai Zhouhttp://www.rit.edu/~meseec/eecc341-winter2001/http://www.ece.nwu.edu/~haizhou/ece303.html


3

Combinational Arithmetic Circuits

Addition:Half Adder (HA).

Full Adder (FA).

Carry Ripple Adders.

Carry Look-Ahead Adders.

Subtraction:Half Subtractor.

Full Subtractor.

Borrow Ripple Subtractors.

Subtraction using adders.

Multiplication:Combinational Array Multipliers.


4

Half AdderAdding two single-bit binary values, X, Y produces a sum S bit and a carry out C-out bit.

This operation is called half addition and the circuit to realize it is called a half adder.

X0011

Y0101

S0110

C-out 0 0 0 1

Half Adder Truth Table

Inputs Outputs

S(X,Y) = (1,2)S = X’Y + XY’S = X Y

C-out(x, y, C-in) = (3)C-out = XY

X

YSum S

C-out HalfAdder

X

Y

SC-OUT


5

Full Adder

Adding two single-bit binary values, X, Y with a carry input bit C-in produces a sum bit S and a carry out C-out bit.

X00001111

Y00110011

S01101001

C-out 0 0 0 1 0 1 1 1

C-in 0 1 0 1 0 1 0 1

Full Adder Truth Table

S(X,Y, C-in) = S (1,2,4,7)C-out(x, y, C-in) = S (3,5,6,7)

Inputs Outputs


6

Full AdderSum S

C-in

X

0 1

00 01 11 10

Y

C-in

XY

0

1

2

3

6

7

4

5

1

1 1

1

C-in

X

0 1

00 01 11 10

Y

C-in

XY

0

1

2

3

6

7

4

5

1

11 1

Carry C-out

S = X’Y’(C-in) + XY’(C-in)’ + XY’(C-in)’ + XY(C-in)S = X Y (C-in)

C-out = XY + X(C-in) + Y(C-in)


7

Full Adder Circuit Using AND-OR

XY

YC-in

C-outXC-in

X

X

Y

C-in

Y

C-in

Y Y’Y

X X’X

C-in C-in’C-in

X’Y’C-in

XY’C-in’

Sum SX’YC-in’

XYC-in

X’

X’

X

X

Y’

Y

Y

C-in

Y

C-in’

C-in’

C-in’

Full Adder

X Y

S

C-inC-out


8

Full Adder Circuit Using XOR

Full Adder

X Y

S

C-inC-out XY

YC-in

C-outXC-in

X

X

Y

C-in

Y

C-in

Sum S

X

Y

C-in


9

n-bit Carry Ripple Adders

An n-bit adder used to add two n-bit binary numbers can built by connecting in series n full adders.

Each full adder represents a bit position j (from 0 to n-1).

Each carry out C-out from a full adder at position j is connected to the carry in C-in of the full adder at the higher position j+1.

The output of a full adder at position j is given by:

Sj = Xj Yj Cj

Cj+1 = Xj . Yj + Xj . Cj + Y . Cj


10

n-bit Carry Ripple Adders

In the expression of the sum Cj must be generated by the full adder at the lower position j-1.

The propagation delay in each full adder to produce the carry is equal to two gate delays = 2

Since the generation of the sum requires the propagation of the carry from the lowest position to the highest position , the total propagation delay of the adder is approximately:

Total Propagation delay = 2 n


11

Full Adder

X1 Y1

S1

C-inC-out Full Adder

X0 Y0

S0

C-inC-out C0 =0 Full Adder

X2 Y2

S2

C-inC-out Full Adder

X3 Y3

S3

C-inC-outC1C2C3C4

Data inputs to be added

Sum output

4-bit Carry Ripple Adder

Adds two 4-bit numbers: X = X3 X2 X1 X0 Y = Y3 Y2 Y1 Y0 producing the sum S = S3 S2 S1 S0 , C-out = C4 from the most significant position j=3

4-bit Adder

X3X2X1X0

S3 S2 S1 S0

C-inC-outC4

Y3Y2Y1Y0

C0 =0

Inputs to be added

Sum Output

Total Propagation delay = 2 nD = 8D

or 8 gate delays


12

Larger AddersExample: 16-bit adder using 4, 4-bit adders

Adds two 16-bit inputs X (bits X0 to X15), Y (bits Y0 to Y15) producing a 16-bit Sum S (bits S0 to S15) and a carry out C16 from most significant position.

4-bit Adder

C-inC-out 4-bit Adder

C-inC-out C0 =0 4-bit Adder

C-inC-out 4-bit Adder

C-inC-outC4C8C12C16

Data inputs to be added X (X0 to X15) , Y (Y0-Y15)

Sum output S (S0 to S15)

Y3Y2Y1Y0X3X2X1X0Y3Y2Y1Y0X3X2X1X0Y3Y2Y1Y0X3X2X1X0Y3Y2Y1Y0X3X2X1X0

S3 S2 S1 S0S3 S2 S1 S0S3 S2 S1 S0S3 S2 S1 S0

Propagation delay for 16-bit adder = 4 x propagation delay of 4-bit adder = 4 x 2 n = 4 x 8 = 32 or 32 gate delays


13

Carry Look-Ahead Adders

The disadvantage of the ripple carry adder is that the propagation delay of adder (2 nD ) increases as the size of the adder, n is increased due to the carry ripple through all the full adders.

Carry look-ahead adders use a different method to create the needed carry bits for each full adder with a lower constant delay equal to three gate delays.

The carry out C-out from the full adder at position i or Cj+1 is given by:

C-out = C i+1 = Xi . Yi + (Xi + Yi) . Ci


14


By defining:Gi = Xi . Yi as the carry generate function for position i (one gate delay)

(If Gi =1 C i+1 will be generated regardless of the value Ci)

Pi = Xi + Yi as the carry propagate function for position i (one gate delay)

(If Pi = 1 Ci will be propagated to C i+1)


15


By using the carry generate function Gi and carry propagate function Pi , then C i+1 can be written as:

C-out = C i+1 = Gi + Pi . Ci

To eliminate carry ripple the term Ci is recursively expanded and by multiplying out, we obtain a 2-level AND-OR expression for each C i+1


16


For a 4-bit carry look-ahead adder the expanded expressions for all carry bits are given by:C1 = G0 + P0.C0

C2 = G1 + P1.C1 = G1 + P1.G0 + P1.P0.C0

C3 = G2 + P2.G1 + P2.P1.G0 + P2.P1.P0.C0

C4 = G3 + P3.G2 + P3.P2.G1 + P3 . P2.P1.G0 + P3.P2.P1.P0.C0

where Gi = Xi . Yi Pi = Xi + Yi


17


The additional circuits needed to realize the expressions are usually referred to as the carry look-ahead logic.

Using carry-ahead logic all carry bits are available after three gate delays regardless of the size of the adder.


18

Carry Look-Ahead Circuit

Ci = Gi-1 + Pi-1. Gi-2 + …. + Pi-1.P i-2. …P1 . G0 + P i-1.P i-2. …P0 . C0


19

Carry Lookahead Implementation

Adder with Propagate and Generate Outputs

Increasingly complex logic

Pi @ 1 gate delay

Ci Si @ 2 gate delays

BiAi

Gi @ 1 gate delay

C0C0

C0

C0P0P0

P0

P0

G0G0

G0

G0

C1

P1

P1

P1

P1

P1

P1 G1

G1

G1

C2P2

P2

P2

P2

P2

P2

G2

G2

C3

P3

P3

P3

P3

G3

C4


20

Cascaded Carry Lookahead Logic

Carry lookaheadlogic generatesindividual carries

sums computedmuch faster

A 0

B 0

C 0

S 0 @2

A 1

B 1

C 1 @3

S 1 @4

A 2

B 2

C 2 @3

S 2 @4

A 3

B 3

C 3 @3

S 3 @4

C 4 @3


21

Delay Analysis in Carry Lookahead

Assume a 4-stage adder with CLA

Propagate and generate signals available after 1 gate delays

Carry signals for slices 1 to 4 available after 3 gate delays

Sum signal for slices 1 to 4 after 4 gate delays


22

Carry Lookahead LogicCascaded Carry Lookahead

4 bit adders with internal carry lookahead

second level carry lookahead unit, extends lookahead to 16 bits

4-bit Adder

4 4

4

A [15-12] B [15-12] C 12 C 16

S [15-12]

P G 4-bit Adder

4 4

4

A [1 1-8] B [1 1-8] C 8

S [1 1-8]

P G 4-bit Adder

4 4

4

A [7-4] B [7-4] C 4

S [7-4]

P G 4-bit Adder

4 4

4

A [3-0] B [3-0] C 0

S [3-0]

P G

Lookahead Carry Unit C 0

P 0 G 0 P 1 G 1 P 2 G 2 P 3 G 3 C 3 C 2 C 1

C 0

P 3-0 G 3-0

C 4

@3 @2

@0

@4

@4 @3 @2 @5

@7

@3 @2 @5

@8 @8

@3 @2

@5

@5 @3

@0

C 16


23

Delay Analysis of Carry Lookahead

Consider a 16-bit adder

Implemented with four stages of 4-bit adders using carry lookahead

Carry in to the highest stage is available after 5 gate delays

Sum from highest stage available at 8 gate delays

COMPARE WITH 32 gate delays for a ripple carry adder

NOTE HOWEVER THIS ASSUMES ALL GATE DELAYS ARE SAME

Not true, delays depand on fan-ins and fan-out


24

Binary Arithmetic OperationsSubtraction

Two binary numbers are subtracted by subtracting each pair of bits together with borrowing, where needed.

Subtraction Example:

Borrow 0 0 1 1 1 1 1 0 0 X 229 1 1 1 0 0 1 0

1 Y - 46 - 0 0 1 0 1 1 1 0 183 1 0 1 1 0 1 1 1


25

Half SubtractorSubtracting a single-bit binary value Y from anther X (I.e. X -Y ) produces a difference bit D and a borrow out bit B-out.

This operation is called half subtraction and the circuit to realize it is called a half subtractor.

X0011

Y0101

D0110

B-out 0 1 0 0

Half Subtractor Truth Table

Inputs Outputs

D(X,Y) = (1,2)D = X’Y + XY’D = X Y

B-out(x, y, C-in) = (1)B-out = X’Y

HalfSubtractor

X

Y

DB-OUT

X

Y

Difference D

B-out


26

Full SubtractorSubtracting two single-bit binary values, Y, B-in from a single-bit value X produces a difference bit D and a borrow out B-out bit. This is called full subtraction.

X00001111

Y00110011

D01101001

B-out 0 1 1 1 0 0 0 1

B-in 0 1 0 1 0 1 0 1

Full Subtractor Truth Table

S(X,Y, C-in) = (1,2,4,7)C-out(x, y, C-in) = (1,2,3,7)

Inputs Outputs


27

Full Subtractor Difference D

B-in

X

0 1

00 01 11 10

Y

B-in

XY

0

1

2

3

6

7

4

5

1

1 1

1

B-in

X

0 1

00 01 11 10

Y

B-in

XY

0

1

2

3

6

7

4

5

1

11 1

Borrow B-out

S = X’Y’(B-in) + XY’(B-in)’ + XY’(B-in)’ + XY(B-in)S = X Y (C-in)

B-out = X’Y + X’(B-in) + Y(B-in)


28

Full Subtractor Circuit Using AND-OR

X’Y

YB-in

B-outX’B-in

X’

X’

Y

B-in

Y

B-in

Y Y’Y

X X’X

B-in B-in’B-in

X’Y’B-in

XY’B-in’

Difference DX’YB-in’

XYB-in

X’

X’

X

X

Y’

Y

Y

B-in

Y

B-in’

B-in’

B-in’

Full Subtractor

X Y

D

B-inB-out


29

Full Subtractor Circuit Using XOR

Difference D

X

Y

B-in

X’Y

YB-in

B-outX’B-in

X’

X’

Y

B-in

Y

B-in

Full Subtractor

X Y

D

B-inB-out


30

n-bit Subtractors

An n-bit subtracor used to subtract an n-bit number Y from another n-bit number X (i.e X-Y) can be built in one of two ways:

By using n full subtractors and connecting them in series, creating a borrow ripple subtractor:•Each borrow out B-out from a full subtractor at

position j is connected to the borrow in B-in of the full subtracor at the higher position j+1.


31

n-bit Subtractors

By using an n-bit adder and n inverters:•Find two’s complement of Y by:

– Inverting all the bits of Y using the n inverters.– Adding 1 by setting the carry in of the least

significant position to 1•The original subtraction (X - Y) now becomes

an addition of X to two’s complement of Y using the n-bit adder.


32

4-bit Borrow Ripple Subtractor

Subtracts two 4-bit numbers: Y = Y3 Y2 Y1 Y0 from X = X3 X2 X1 X0 Y = Y3 Y2 Y1 Y0 producing the difference D = D3 D2 D1 D0 , B-out = B4 from the most significant position j=3

4-bitSubtractor

X3X2X1X0

D3 D2 D1 D0

B-inB-outB4

Y3Y2Y1Y0

B0 =0

Inputs

Difference Output D

Full Subtractor

X1 Y1

D1

B-inB-out

X0 Y0

D0

B-inB-out B0 =0

X2 Y2

D2

B-inB-out

X3 Y3

D3

B-inB-outB1B2B3B4

Data inputs to be subtracted

Difference output D

Full Subtractor

Full Subtractor

Full Subtractor


33

4-bit Subtractor Using 4-bit Adder

4-bit Adder

X3 X2 X1 X0

D3 D2 D1 D0

C-inC-outC4

Y3 Y2 Y1 Y0

C0 = 1

Inputs to be subtracted

Difference Output

S3 S2 S1 S0


34

Adder/Subtractor

A - B = A + (-B) = A + B + 1

A B

CO

S

+ CI

A B

CO

S

+ CI

A B

CO

S

+ CI

A B

CO

S

+ CI

0 1

Add/Subtract

A 3 B 3 B 3

0 1

A 2 B 2 B 2

0 1

A 1 B 1 B 1

0 1

A 0 B 0 B 0

Sel Sel Sel Sel

S 3 S 2 S 1 S 0

Overflow


35

Binary Multiplication

Multiplication is achieved by adding a list of shifted multiplicands according to the digits of the multiplier.Ex. (unsigned)

11 1 0 1 1 multiplicand (4 bits)

X 13 X 1 1 0 1 multiplier (4 bits)-------- ------------------- 33 1 0 1 1 11 0 0 0 0______ 1 0 1 1 143 1 0 1 1 --------------------- 1 0 0 0 1 1 1 1 Product (8 bits)


36

Binary Multiplication

An n-bit X n-bit multiplier can be realized in combinational circuitry by using an array of n-1 n-bit adders where is adder is shifted by one position.For each adder one input is the multiplied by 0 or 1 (using AND gates) depending on the multiplier bit, the other input is n partial product bits. X3 X2 X1 X0

x Y3 Y2 Y1 Y0 __________________________ X3.Y0 X2.Y0 X1.Y0 X0.Y0 X3.Y1 X2.Y1 X1.Y1 X0.Y1 X3.Y2 X2.Y2 X1.Y2 X0.Y2 X3.Y3 X2.Y3 X1.Y3 X0.Y3_______________________________________________________________________________________________________________________________________________

P7 P6 P5 P4 P3 P2 P1 P0


37

4x4 Array Multiplier


38

Combinational Multiplier

Partial Product Accumulation

A0

B0

A0 B0

A1

B1

A1 B0

A0 B1

A2

B2

A2 B0

A1 B1

A0 B2

A3

B3

A2 B0

A2 B1

A1 B2

A0 B3

A3 B1

A2 B2

A1 B3

A3 B2

A2 B3A3 B3

S6 S5 S4 S3 S2 S1 S0S7


39

Partial Product Accumulation

Note use of parallel carry-outs to form higher order sums

12 Adders, if full adders, this is 6 gates each = 72 gates

16 gates form the partial products

total = 88 gates!

A 0 B 0 A 1 B 0 A 0 B 1 A 0 B 2 A 1 B 1 A 2 B 0 A 0 B 3 A 1 B 2 A 2 B 1 A 3 B 0 A 1 B 3 A 2 B 2 A 3 B 1 A 2 B 3 A 3 B 2 A 3 B 3

HA

S 0 S 1

HA

F A

F A

S 3

F A

F A

S 4

HA

F A

S 2

F A

F A

S 5

F A

S 6

HA

S 7


40

Combinational Multiplier

Another Representation of the Circuit

A3 B0

SC

A2 B0

SC

A1 B0

SC

A0 B0

SC

A3 B1

SC

A2 B1

SC

A1 B1

SC

A0 B1

SC

A3 B2

SC

A2 B2

SC

A1 B2

SC

A0 B2

SC

A3 B3

SC

A2 B3

S

A1 B3

S

A0 B3

S

B0

B1

B2

B3

P7 P6 P5 P4 P3 P2 P1 P0

A3 A2 A1 A0

Building block: full adder + and

4 x 4 array of building blocks

F A

X

Y

A B

S CI CO

Cin Sum In

Sum Out Cout


41

Full-adder array


42

Faster carry chain


43

Arithmetic Logic Unit DesignSample ALU

S1 0 0 1 1

S0 0 1 0 1

Function Fi = Ai

Fi = not Ai Fi = Ai xor Bi

Fi = Ai xnor Bi

Comment Input Ai transferred to output Complement of Ai transferred to output Compute XOR of Ai, Bi Compute XNOR of Ai, Bi

M = 0, Logical Bitwise Operations

M = 1, C0 = 0, Arithmetic Operations

0 0 1 1

0 1 0 1

F = A F = not A

F = A plus B F = (not A) plus B

Input A passed to output Complement of A passed to output Sum of A and B Sum of B and complement of A

M = 1, C0 = 1, Arithmetic Operations

0 0 1 1

0 1 0 1

F = A plus 1 F = (not A) plus 1

F = A plus B plus 1 F = (not A) plus B plus 1

Increment A Twos complement of A Increment sum of A and B B minus A

Logical and Arithmetic Operations

Not all operations appear useful, but "fall out" of internal logic


44


Traditional Design Approach

Truth Table & Espresso

23 product terms!

Equivalent to 25 gates

.i 6

.o 2

.ilb m s1 s0 ci ai bi

.ob fi co

.p 23111101 10110111 101-0100 101-1110 1010010- 1010111- 10-10001 10010-01 10-11011 10011-11 10--1000 100-1-00 10--0010 100-0-10 10-0100- 10001-0- 10-0001- 10000-1- 10-1-1-1 01--1-01 01--0-11 01--110- 01--011- 01.e

M 0

1

1

S1 0

0

1

1

0

0

1

1

0

0

1

1

S0 0

1

0

1

0

1

0

1

0

1

0

1

Ci X X X X X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1

Ai 0 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 0 1 1 0 0 1 1 01 0 1 0 0 1 1 0 0 1 1

Bi X X X X 0 1 0 1 0 1 0 1 X X X X 0 1 0 1 0 1 0 1 X X X X 0 1 0 1 0 1 0 1

Fi 0 1 1 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 1 0

Ci+1 X X X X X X X X X X X X X X X X 0 0 0 1 0 1 0 0 0 1 1 0 0 1 1 1 1 1 0 1


45


Multilevel Implementation

.model alu.espresso

.inputs m s1 s0 ci ai bi

.outputs fi co

.names m ci co [30] [33] [35] fi110--- 1-1-11- 1--01-1 1--00-0 1.names m ci [30] [33] co-1-1 1--11 1111- 1.names s0 ai [30]01 110 1.names m s1 bi [33]111 1.names s1 bi [35]0- 1-0 1.end 12 Gates

\S1

\Bi

[35]

[35] M

M

MS1Bi

[33][33]

[33]

[33]

S0Ai

[30]

[30]

[30]

[30]

[30]

Ci

Ci

Ci

Ci

Co

\Co

\Co

\Co

\[30]\[35]

Fi


46

Programmable Arrays of Logic Gates

Until now, we learned about designing Boolean functions using discrete logic gatesWe will now describe a technique to arrange AND and OR gates (or NAND and NOR gates) into a general array structureSpecific functions can be programmedCan use programmable logic arrays (PLA) or programmable array logic (PAL)


47

PALs and PLAsPre-fabricated building block of many AND/OR gates (or NOR, NAND)"Personalized" by making or breaking connections among the gates

Programmable Array Block Diagram for Sum of Products Form

Inputs

Dense array of AND gates Product

terms

Dense array of OR gates

Outputs


48

Programmable Logic Arrays (PLAs)

Any combinational logic function can be realized as a sum of products.Idea: Build a large AND-OR array with lots of inputs and product terms, and programmable connections.

n inputs• AND gates have 2n inputs -- true and complement of

each variable.m outputs, driven by large OR gates• Each AND gate is programmably connected to each

output’s OR gate.p AND gates (p<<2n)


49

Why PALs/PLAs Work

Example:F0 = A + B' C'F1 = A C' + A BF2 = B' C' + A BF3 = B' C + A

Equations

Personality Matrix

Key to Success: Shared Product Terms

1 = asserted in term0 = negated in term- = does not participate

1 = term connected to output0 = no connection to output

Input Side:

Output Side:

Outputs Inputs Product t erm

Reuse of

t erms

A 1 - 1 - 1

B 1 0 - 0 -

C - 1 0 0 -

F 0 0 0 0 1 1

F 1 1 0 1 0 0

F 2 1 0 0 1 0

F 3 0 1 0 0 1

A B B C A C B C A


50

Example of PALs and PLAsAll possible connections are available

before programming


51

Example of PALs and PLAs (Contd)

Unwanted connections are "blown"

Note: some array structureswork by making connections

rather than breaking them


52

Example: 4x3 PLA, 6 product terms


53

Alternative Representations

Short-hand notationso we don't have todraw all the wires!

Notation for implementingF0 = A B + A' B'F1 = C D' + C' D


54

Design Example

ABC

A

B

C

A

B

C

ABC

ABC

ABC

ABC

ABC

ABC

ABC

F1 F2 F3 F4 F5 F6

F1 = A B C

F2 = A + B + C

F3 = A B C

F4 = A + B + C

F5 = A xor B xor C

F6 = A xnor B xnor C

Multiple functions of A, B, C


55

Compact representation

Actually, closer to physical layout (“wired logic”).


56

Some product terms


57

PLA Electrical Design

-- wired-AND logic


58

Programmable Array Logic (PALs)

How beneficial is product sharing?Not enough to justify the extra AND array

PALs ==> fixed OR arrayEach AND gate is permanently connected to a certain OR gate.

Example: PAL16L8


59

10 primary inputs8 outputs, with 7 ANDs per output1 AND for 3-state enable6 outputs available as inputs

more inputs, at expense of outputstwo-pass logic, helper terms

Note inversion on outputsoutput is complement of sum-of-productsnewer PALs have selectable inversion


60

Design Example: BCD-to-Gray Code Converter

Truth TableK-maps

W = A + B D + B CX = B C'Y = B + CZ = A'B'C'D + B C D + A D' + B' C D'

Minimized Functions:

A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

W 0 0 0 0 0 1 1 1 1 1 X X X X X X

X 0 0 0 0 1 1 0 0 0 0 X X X X X X

Y 0 0 1 1 1 1 1 1 0 0 X X X X X X

Z 0 1 1 0 0 0 0 1 1 0 X X X X X X

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

0 0 X 1

0 1 X 1

0 1 X X

0 1 X X

K-map for W

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

0 1 X 0

0 1 X 0

0 0 X X

0 0 X X

K-map for X

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

0 1 X 0

0 1 X 0

1 1 X X

1 1 X X

K-map for Y

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

0 0 X 1

1 0 X 0

0 1 X X

1 0 X X

K-map for Z


61

Programmed PAL

4 product terms per each OR gate

A B C D

0

0

0

0

0

0


62

Designing with PALs

Compare number of inputs and outputs of the problem with available resources in the PAL.Write equations for each output using ABEL.Compile the ABEL program, determine whether minimimized equations fit in the available AND terms.If no fit, try modifying equations or providing “helper” terms.


63

Read-Only Memories


64

Why “ROM”?

Program storageBoot ROM for personal computersComplete application storage for embedded systems.

Actually, a ROM is a combinational circuit, basically a truth-table lookup.

Can perform any combinational logic functionAddress inputs = function inputsData outputs = function outputs


65

Logic-in-ROM example


66

Implementing Logic with ROMs

F0 = A' B' C + A B' C' + A B' C

F1 = A' B' C + A' B C' + A B C

F2 = A' B' C' + A' B' C + A B' C'

F3 = A' B C + A B' C' + A B C'

address outputs

A B C F 0 F 1 F 2 F 3

B 0 0 1 1 0 0 1 1

Address W ord Contents A 0 0 0 0 1 1 1 1

C 0 1 0 1 0 1 0 1

F 0 0 1 0 0 1 1 0 0

F 1 0 1 1 0 0 0 0 1

F 2 1 1 0 0 1 0 0 0

F 3 0 0 0 1 1 0 1 0

8x4 ROM


67

4x4 multiplier example


68

Internal ROM structure

PDP-11 boot ROM(64 words, 1024 diodes)


69

Today’s ROMs

256K bytes, 1M byte, or largerUse MOS transistors


70

EEPROMs, Flash PROMs

Programmable and erasable using floating-gate MOS transistors


71

Typical commercial EEPROMs


72

EEPROM programming

Apply a higher voltage to force bit changeE.g., VPP = 12 VOn-chip high-voltage “charge pump” in newer chips

Erase bitsByte-byteEntire chip (“flash”)One block (typically 32K - 66K bytes) at a time

Programming and erasing are a lot slower than reading (milliseconds vs. 10’s of nanoseconds)


73

Microprocessor EPROM application


74

ROM control and I/O signals


75

ROM timing


76

ROMs vs PLAs

Not unlike a PLAstructure with afully decoded

AND array!

Not unlike a PLAstructure with afully decoded

AND array!

ROM vs. PLA:ROM approach advantageous when (1) design time is short (no need to minimize output functions) (2) most input combinations are needed (e.g., code converters) (3) little sharing of product terms among output functions

ROM problem: size doubles for each additional input, can't use don't cares

PLA approach advantangeous when (1) design tool like espresso is available (2) there are relatively few unique minterm combinations (3) many minterms are shared among the output functions

PAL problem: constrained fan-ins on OR planes

Memory array

2 n words by m bits

m output lines

n address lines

Decoder 2 n word lines

lecture 6 combinational arithmetic circuits

Documents