lecture03-fpga

Courtesy Dr. C. Heer (12/2002) FPGA-lecture 19.11.2003

Reconfigurable hardware components: FPGA

• Classification

• FPGA• Basic logic cells • Routing strategies• Configuration methods

• PLA/PAL

• Design flow

• eFPGA

• Examples


Classification of digital integrated circuits (see Section 2.2.3 )

DSP

µP

µC

programmablestandardarchitectures

programmablelogic

Applicationspecific logic

(E)EPROM

(P)ROMPAL/PLA RAM CPLD

FPGA gatearray

standardcells

Semicustom Full

custom


Features of FPGA implementation against ASICs

Advantages• fast and cheap procedure for implementing hardware• fast functional verification• low cost of low-volume production• improved time-to-market• re-configurability in the field

Disadvantages• non-optimal utilisation of silicon area• signal delay and power consumption are high• routing problems could limit flexibility• potential clock-skew problems


Business/market models for FPGAs

OTP-architectures (one time programmable)• derivatives of standard devices• low cost of customisation for low quantities• fast time-to-market for low volume designs

Re-programmable architectures• prototyping and functional development on standard platforms• in-field customisation and updating• multiple-application hardware


Basic building blocks of FPGAs (see Section 2)

Logic blocks(CLB)

Memory blocks(configuration)

Wiring andinterconnect

Interface blocks


Basic architectures of FPGAs (see Section 2.1)

Symmetric matrix (a)

Row of cells (b)

Sea of cells (c)(no dedicated routing channels)

Hierarchical architecture (d)

(a) (b)

(c) (d)

Routingchannel Routing

channel

Routingchannel

Routing channels overlaidon logic modules

Logicmodule

Logicmodule

Logicmodule

Logic module


Basic elements of Configurable Logic Cells (CLC)

Logic elements• Transistors• Basic gates (NAND, XOR, ... )• Flip-flops• Multiplexers• Look-up tables (LUTs)• AND-OR arrays (sum-of-products)

The term granularity refers to a quantification of the complexity of the CLC andcan depend on the following:• Number of logical functions which may be implemented by each CLC• Number of equivalent NAND2 gates of each CLC• Total number of transistors that physically constitute the CLC


Granularity of FPGAs (see Section 2.2)

High granularity FPGAlow complexity CLCLarge number of CLCsComplex routing resources

Low granularity FPGAHigh complexity CLCSmaller number of CLCsSimpler routing resources

Transistor/Gate LUT PAL/PLA µP/ALU


Multiplexer based CLB (configurable logic block) (see Section 2.2.1 )

Multiplexer based CLB

example from Actel 40MK

8-input, 1-output cell

implements basic logicfunctions (and, or, nor, ..) with2,3, or 4 inputs


Look-up table (LUT) based CLB (see Section 2.2.2 )

LUT based CLB

depending on thecombination of the inputwords, a predefinedoutput value is assigned

Memory implementation:

input values =address of memory

predefined values =content of memory


Registered output based CLB

The output of the LUT may be registered or not, depending on thefunctional description (selection is implemented via multiplexers)


CLB with registered output


LUT output based CLB

LUT with four inputs

only three inputs are used

input D is a dont’care

Exercise:extract the logic function!

A B C D O/p

0 0 0 x 0

0 1 0 x 0

1 0 0 x 1

1 1 0 x 1

0 0 1 x 0

0 1 1 x 1

1 0 1 x 0

1 1 1 x 1


LUT based CLB

Example from ActelVaricore CLC:

LUT based

Multiplexer to decreaseLUT size

Registered output viamultiplexer selectable


LUT output based CLB

Example from XilinxXC3000:

Dual output complexCLB

registers selectable

large combinationalfunction with two outputs


Complex programmable logic device (CPLD) (see Section 2.2.3 )

Simpleprogrammable logicdevices (SPLD) areused to implementthe logic functions

PAL or PLA arrays


SPLD based on PAL implementation


PLA architecture (see Appendix A)

PLA consists of two ‘planes’:

the and-plane to build the min-terms

the or-plane to build the output values

the connections between input signalsand and-plane and between the planesare flexible

PAL is a PLA with fixed OR-plane


FPGA design flow (see Section 3)

Design Entry(VHDL, verilog, schematic)

Logic Synthesis(VHDL, verilog, schematic)

Floorplanning(VHDL, verilog, schematic)

Place and Route(VHDL, verilog, schematic)

Layout Verification(VHDL, verilog, schematic)

Macro Integration(VHDL, verilog, schematic)


Routing strategies for FPGAs (see Section 2.3)

Four types of routing networks are needed in an FPGA device:

• Power feeding network• Reset and multiple clock networks (local / global)• Signal network interconnecting all cells• Configuration lines

A strategy adopted by most manufacturers to different extent is the structuringof the device into some sort of hierarchy, by segmenting the array into groupsof CLCs. Routing lines interconnecting the cells could then be broadlyclassified into three different types:

• Local routing lines directly interconnecting neighbours• Interconnects to route signals within a cluster of cells• Global interconnects to transmit signals throughout the whole FPGA


Implementation of routing channels

Routing hierarchy:• global lines• double length lines• local lines

switching nodes toconnectneighbouringmodules

local switch for asingle bit with sixtransistors


Electrical model of FPGA routing track

Complex routing modelcrossing varioushierarchies of the FPGArequires very accurateelectrical modelling forplace & route


Configuration of FPGAs (see Section 2.4)

FPGA devices allow the configuration of all CLCs, I/O cells and interconnect resources.The gate of each configurable transistor is controlled by the contents of a 1-bit memorycell, with a logic '0' or logic '1' determining whether the gate is off or on. To reduce thewiring required for configuration, the memory cells can be connected in a chain and theconfiguration is then loaded using a shift operation. Depending on the physicalconfiguration mechanism, it is possible to classify FPGAs into three classes:

• One-time configurable devices• Non-volatile re-configurable devices• Volatile re-configurable devices

One-time programmable devices store configuration using fuses or anti-fuses. Theformer are normally closed structures, while the latter are normally open. A device basedon fuse technology is programmed by physically breaking the connections betweenappropriate structures. On the other hand, a device based on anti-fuses is programmedby melting interconnections between particular cells to generate contacts.


Implementation of FPGA configuration

Pass structure and tri-state buffer controlled by locally stored configurationinformation (SRAM cells)


Configurable output cell of a FPGA (see Section 2.6)

Example from XilinxXC4000C Series IO-cell


ATMEL AT94K field programmable system level integratedcircuit (FPSLIC)

5-40 Kgates FPGA

8-bit microcontroller

various peripheralunits


ATMEL AT94K FPSLIC: technical data

IC Characteristics AT94K05AL AT94K10AL AT94K40AL

Process Parameter (2�) 0.35� 0.35� 0.35�

Metallisation Layers 5 5 5

Supply Voltage 3.0 - 3.6 V 3.0 - 3.6 V 3.0 - 3.6 V

System SRAM Block Size 24K x 8 36K x 8 36K x 8

CISC or RISC RISC RISC RISCRegister Size 8 bits 8 bits 8 bitsClock Freq. 20 / 40 MHz 20 / 40 MHz 20 / 40 MHz

Embedded�PC

MIPS 19 / 30 19 / 30 19 / 30


ATMEL AT94K FPSLIC: technical data

FPGA Macro Architecture AT94K05AL AT94K10AL AT94K40AL

CLCs 256 576 2304CLC Type LUT LUT LUT

Registers / CLC 1 1 1

Array ofConfigurableLogical Cells

(CLCs) LUTs / CLC Size 2 8 x 1 2 8 x 1 2 8 x 1

Matrix Structure Symmetric Symmetric Symmetric

Equivalent ASIC Gate Count 5000 10000 40000

Max. I/O Lines Available to User 96 144 288

Typ. Core Power Consumption 6 mW / MHz 6 mW / MHz 6 mW / MHz

Method of Configuration Storage SRAM SRAM SRAM

Re-configurability Volatile Volatile Volatile

Blocks 16 32 144Block Size 32x4 32x4 32x4Distributed RAMTotal Size 2048 bits 4608 bits 18432 bits


ATMEL AT94K FPSLIC: array of CLCs


ATMEL AT94K FPSLIC: 16x16 array of CLCs

Hierarchical routingscheme

CLC are connected tothe eight (!)neighbours


ATMEL AT94K

One of five identicalbus planesconnectingneighbouring CLBs


ATMEL AT94K FPSLIC: bus plane


ATMEL AT94K FPSLIC: LUT based CLC


ATMEL AT94K FPSLIC: design flow


Actel Varicore: embedded FPGA

Business model:

embedded FPGA forvarious circuits andapplications

eFPGA array can beadapted inperformance and size!

Varicore Architecture V18L2x1 V18L2x2 V18L4x1 V18L4x2

CLCs 512 1024 1024 2048CLC Type LUT LUT LUT LUT

Registers / CLC 1 1 1 1


(CLCs) LUTs / CLC Size 2 8x1 2 8x1 2 8x1 2 8x1

Matrix Structure Sea ofCells

Sea ofCells

Sea ofCells

Sea ofCells

Equivalent ASIC Gate Count 5000 10000 10000 20000

Max. I/O Lines Available to User 224 320 352 448

Process Parameter (2�) 0.18� 0.18� 0.18� 0.18�

Metallisation Layers 5 5 5 5

Supply Voltage 1.8 V 1.8 V 1.8 V 1.8 V

Max. Clock Frequency 250 MHz 250 MHz 250 MHz 250 MHz

Typ. Core Power Consumption 2.4 mW /

MHz

2.4 mW/

MHz

2.4 mW/

MHz

2.4 mW/

MHz

Method of Configuration Storage SRAM SRAM SRAM SRAM

Re-configurability Volatile Volatile Volatile Volatile

System SRAM Block Size NA NA NA NA

Blocks NA NA NA NABlock Size NA NA NA NADistributed RAM

Max. Amount NA NA NA NA


Actel Varicore: embedded FPGAFPGA Macro Characteristics V18L4x4 V18L2x2R V18L4x2R V18L4x4R

CLCs 4096 1024 2048 4096CLC Type LUT LUT LUT LUT

Registers / CLC 1 1 1 1


(CLCs) LUTs / CLC Size 2 8x1 2 8x1 2 8x1 2 8x1

Matrix Structure Sea of Cells Sea of Cells Sea of Cells Sea of Cells

Equivalent ASIC Gate Count 40000 10000 20000 40000

Max. I/O Lines Available to User 6140 320 448 6140

Process Parameter (2�) 0.18� 0.18� 0.18� 0.18�

Metallisation Layers 5 5 5 5

Supply Voltage 1.8 V 1.8 V 1.8 V 1.8 V

Max. Clock Freq. 250 MHz 250 MHz 250 MHz 250 MHz

Typ. Core Power Consumption2.4 mW /

MHz

2.4 mW /

MHz

2.4 mW /

MHz

2.4 mW /

MHz

Method of Configuration Storage SRAM SRAM SRAM SRAM

Re-configurability Volatile Volatile Volatile Volatile

System SRAM Block Size NA 36864 bits 73728 bits 73728 bits

Blocks NA NA NA NABlock Size NA NA NA NADistributed RAM

Max. Amount NA NA NA NA



Hierarchy of PEG (processorelement groups, processor groupsand functional groups)



Top level view on the 4x4PEG array

local RAMs for user needs

• configuration RAM• BIST interface (build in self-test)• JTAG interface for test access and programming



Array of functional groupsinside PEG

Functional group consists forfour LUT including registers



Basic configuration ofCLB for DSP-likeapplications

split LUT

selectable register


Actel Varicore: design flow


Actel Varicore: embedded FPGA conclusion

Embedded FPGA will bring• higher flexibility to ASIC systems• better cost efficiency to processor systems

The size of the embedded FPGA can be adapted to the problem/application

The design flow is compatible with a standard ASIC design flow


FPGA conclusion

The market for re-programmable solutions is steadily increasing

FPGA are taking market shares from the ASIC business for low volumeproducts

Embedded FPGAs allow to build systems with the best from all worlds:• general purpose processor cores• optimised and adapted µP/µC cores for special applications• flexible hardware modules (eFPGA) for time critical tasks• area and speed optimised ASIC parts for certain time critical tasks

lecture03-fpga

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