ECE 287 – Lecture 15

Finite State Machines - II

Announcements

• Next Quiz on Wednesday• Exam II – Nov 15th

FSM Example

For the given circuit, we want to use it to store 16 bits of information and check if all the 4 bit individual numbers (4 of them) are all equal.

clk

valid

input out

Algorithm

State Diagram

State Table

State Machine Circuit

What if clock is fast?

How does the system start up?

Actual Comparison Circuit

Verilog for FSMs

BA

In = 0

In = 0

In = 1

Out = 1Out = 0

In = 1

reset

Try and build the Verilog for bit matching example at the start of class…

Problem Set

1. Build a verilog system for:

A

B

G

In = 0

In = 0

In = 0

In = 1

In = 1

In = 1

Out = 1

Out = 1

Out = 0

Problem Set

1. Build a verilog system for:• Design a state machine controller for an elevator. The elevator can be at one of two

floors: Ground or First. There is one button that controls the elevator, and it has two values: Up or Down. Also, there are two lights in the elevator that indicate the current floor: Red for Ground, and Green for First. At each time step (clock), the controller checks the current floor and current input, changes floors and lights in the obvious way.