Sam Palermo Analog & Mixed-Signal Center

Texas A&M University

ECEN620: Network Theory Broadband Circuit Design

Fall 2012

Lecture 17: Divider Circuits

Agenda

• Divider Basics • Dynamic CMOS Divider • CML Divider • Divider Circuit Style Partitioning • Asynchronous vs Syncnronous Dividers • Dual-Modulus Prescalers • Injection-Locked Dividers

2

Charge-Pump PLL Circuits

• Phase Detector

• Charge-Pump

• Loop Filter

• VCO

• Divider

3

Loop Divider

• Time-domain model

4

( ) ( )tN

t outfb ωω 1=

( ) ( ) ( )∫ == tN

tN

t outoutfb φωφ 1dt1

[Perrott]

φout(t) φfb(t)

Basic Divide-by-2

• Divide-by-2 can be realized by a flip-flip in “negative feedback”

• Divider should operate correctly up to the maximum output clock frequency of interest PLUS some margin

5

[Perrott]

[Fischette]

Divide-by-2 with TSPC FF

• Advantages • Reasonably fast, compact size, and no static power • Requires only one phase of the clock

• Disadvantages • Signal needs to propagate through three gates per input cycle • Need full swing CMOS inputs • Dynamic flip-flop may have issues at very low frequency operation (test

mode) depending on process leakage 6

True Single Phase Clock Flip-Flop

Divider Equivalent Circuit Note: output inverter not in left schematic

Divide-by-2 with CML FF

7

• Advantages • Signal only propagates through two CML gates per input cycle • Accepts CML input levels

• Disadvantages • Larger size and dissipates static power • Requires differential input • Need tail current biasing

• Additional speedup (>50%) can be achieved with shunt peaking inductors

[Razavi]

CML Latch

• When the clock is high (M5 on), the input pair (M1 & M2) tracks (linearly amplifies) the input

• When the clock is low (M6 on), the regenerative pair (M3 & M4) latches (with positive feedback) the state

• This regenerative pair continues to provide gain in the store mode, allowing for short cycle operation

• The minimum cross-coupled pair gain to hold the state is gm3,4RD>1 8

CML Latch

• When the clock is high (M5 on), the input pair (M1 & M2) tracks (linearly amplifies) the input

• When the clock is low (M6 on), the regenerative pair (M3 & M4) latches (with positive feedback) the state

• This regenerative pair continues to provide gain in the store mode, allowing for short cycle operation

• The minimum cross-coupled pair gain to hold the state is gm3,4RD>1 9

Optimized CML FF for High-Speed Dividers

• The cross-coupled pair gate and drain capacitances slow down the latch/flip-flop

• If the flip-flop is switching at high-speed, the regenerative pair gain can actually have a loop gain less than unity due to the short hold state

• One way to achieve this is by using a different current in the track state (ISS1) and the hold state (ISS2), allowing for smaller regeneration transistors when ISS2 < ISS1 10

CML Latch Swing Control

• If suitable resistors are not available in a certain process, the PMOS triode-region loads can be used

• Due to PVT variations, feedback control is generally required to maintain the desired CML logic swing level

• A replica circuit produces the required PMOS gate bias to insure the desired CML logic swing for a given ISS

• Note, triode PMOS loads will generally have more parasitic capacitance than linear resistors, resulting in a slower circuit

11

CML Latch with PMOS Diode Loads

• PMOS diode loads may allow for simpler biasing over PVT variations • One issue with this is the large headroom (|VTP|+VOD) required to

turn-on the PMOS diode • NMOS source followers can allow for similar headroom as with triode loads

• Another issue stems from the highly non-linear effective resistance which can introduce inter-symbol interference for random data • Note, this is not an issue for periodic switching divider applications

12

CML Latch with PMOS Diode Loads

• PMOS diode loads may allow for simpler biasing over PVT variations • One issue with this is the large headroom (|VTP|+VOD) required to

turn-on the PMOS diode • NMOS source followers can allow for similar headroom as with triode loads

• Another issue stems from the highly non-linear effective resistance which can introduce inter-symbol interference for random data • Note, this is not an issue for periodic switching divider applications

13

CML Divider Clock Swing vs Frequency

• Interestingly, the divider minimum required clock swing can actually decrease with frequency

• This is due to the feedback configuration of the divider yielding an effective ring oscillator topology that will naturally oscillate at certain frequency

• Near this frequency, the input clock amplitude can be very low • For frequencies above this natural oscillation frequency, the minimum

clock input amplitude increases 14

Divider Circuit Style Partitioning

• While CML dividers generally operate at the highest speed, the static power consumption reduces their efficiency at lower speeds

• For large divide ratios, a mixture of CML and static CMOS dividers are often used

• The first fastest fixed dividers (prescalers) are CML, while the following lower frequency dividers are static CMOS

15

Binary Dividers: Asynchronous vs Synchronous

16

Asynchronous Divider

Synchronous Divider

• Advantages • Each stage runs at lower frequency,

resulting in reduced power • Reduced high frequency clock

loading

• Disadvantage • Jitter accumulation

• Advantage • Reduced jitter

• Disadvantage • All flip-flops work at maximum

frequency, resulting in high power • Large loading on high frequency

clock [Perrott]

Jitter in Asynchronous vs Synchronous Dividers

17

Asynchronous

Synchronous

• Jitter accumulates with the clock-to-Q delays through the divider

• Extra divider delay can also degrade PLL phase margin

• Divider output is “sampled” with high frequency clock

• Jitter on divider clock is similar to VCO output

• Minimal divider delay [Perrott]

Dual Modulus Prescalers

18

÷2/3

MC=0 → ÷3 MC=1 → ÷2

÷15/16

Synchronous ÷3/4 Asynchronous ÷4 • For /15, first prescaler circuit divides by 3 once and 4 three times

during the 15 cycles

[Razavi]

Injection-Locked Frequency Dividers

• Superharmonic injection-locked oscillators (ILOs) can realize frequency dividers

• Faster and lower power than flip-flop based dividers • Injection locking range can be limited

19

LC-oscillator type (/2) Ring-oscillator type (/3)

[Verma JSSC 2003, Rategh JSSC 1999] [Lo CICC 2009]

Injection-locked Frequency Divider Design concept of injection-locked oscillator (ILO)

Unwanted harmonics may exist. Self-coupling may produce unwanted tones too.

Injection-locked frequency dividers (ILFD) feature lower power consumption and more excellent noise performance than digital dividers.

YCLO AMSC-TAMU 20

LPF/BPFFin FoutnFin + mFout

LC INFDs Advantage:

• Better noise performance (LC filtering)

• Low power consumption

• Very high operation frequency (~ fmax)

Disadvantage: • Smaller locking range (LC limited)

• Unwanted harmonics

• Large silicon area due to L and C

• Very difficult to provide multiple phases or large divisor number in one LC oscillator stage (area penalty)

• Difficult to find an excellent source to inject signal

YCLO AMSC-TAMU 21

Ring-Oscillator-Based ILFDs Advantage:

• Smaller area • Wide locking range

• Small power consumption

Disadvantage: • Inferior phase noise to LC ILFDs (Still decent) • Worse unwanted harmonics (No LC resonant filtering) • False locking

YCLO AMSC-TAMU 22

Complementary Injection-Locked Frequency Divider (CILFD)

Large odd-modulus(101) Only dynamic power

consumption 100% frequency locking

range Differential input/output 50% duty cycle Small area

23

Fin ( 0° )

(2n+1)×Fin ( ø + 0° ) (2n+1)×Fin ( ø + 180° )

(2n+1)-stage

Auxiliary Inverter

Fin ( 180° )

Fin ( 0° + 360°/(2n+1) )

(2n+1)-stage

Fin ( 180° + 360°/(2n+1) )

Fin ( 0° + 360°×(2n)/(2n+1) ) Fin ( 0° + 360°×(2n)/(2n+1) )

Complementary Injection Scheme Complementary injection reinforces the injection strength to widen the frequency locking range. Only when the inverter transits state the tail transistors inject current. Independent tail injection to each stage avoids the interference between each stage.

24

Injection Signal

Ring-oscillator output

Tail NMOS injection current

Tail PMOS injection current

Locking Range (Input Sensitivity) Over 100% locking range(Post-layout simulation in TSMC 0.18 µm technology)

25

Divided-by-3 operation Divided-by-15 operation

-10

-8

-6

-4

-2

0

2

4

6

8

0 1 2 3 4 5 6 7 8

Inpu

t Pow

er (

dBm

)

Incident Frequency (GHz)

-10

-8

-6

-4

-2

0

2

4

6

8

0 1 2 3 4 5 6 7 8

Inpu

t Pow

er (

dBm

)

Incident Frequency (GHz)

Power Consumption and Phase Noise Power consumption: One ring-oscillator stage: CILFD: The power consumption is independent to the division modulus (# of ring-oscillator stage).

Phase noise: The phase noise of CILFD is mainly determined by the phase noise of injection signal.

26

+≅

1212

nfCVP InjDDStage

InjDDStage fCVP 22≅

From top to bottom (1) free running CILFD, (2) incident signal, and (3) locked CILFD

( )2.log10)()( NoModulusIncidentPNCILFDPN −≅

Example PLL Design Procedure

• Design procedure for a 100-300MHz frequency synthesizer • Step 1 – Determine VCO Tuning Range

• Needs to be at least the output frequency range plus some margin (10-20%) dependent on PVT tolerance

27

*300MHz - 100 Range Tuning VCO =

• *Note if you want the frequency extremes (100 or 300MHz) you probably want to add some margin here

• Step 2 – Determine Loop Division Ratio, N • This is a function of what reference clocks you have access to,

loop bandwidth, dominant noise sources 32=N

• Step 3 – Determine Damping Factor • Damping factors between 0.5 and 2 are reasonable, with 0.7 or 1

commonly chosen 707.0

21

≈=ζ

Example PLL Design Procedure

• Step 4 – Determine natural frequency, ωn • This is a function of the desired loop bandwidth and also the

damping factor • Maximum loop bandwidth should be less than 1/10th the

input reference clock for the loop to act as a continuous-time system

28

MHz125.332

100MHz Frequency ReferenceInput Lowest ==

• Set the loop bandwidth with some margin - 75% of max value

( )( ) sMrad

dB 47.1kHz5.312275.03 == πω

• For a damping factor of 0.707

skrads

MraddB

n 71406.2

47.1

06.23 ===

ωω

Example PLL Design Procedure • Step 5 – Determine KVCO

• This is a function of the VCO and charge pump operating voltage range

• Here I use a combination of discrete tuning caps, resulting in multiple frequency bands over the total frequency range

29

Freq

uenc

y (M

Hz)

VCO Control Voltage

Channel 4 (235 - 300MHz)

Channel 2 (145 - 210MHz)

Channel 1 (100 - 165MHz)

Kvco = 40MHz/V

100

145

190

235

165

210

255

300

Channel 3 (190 - 255MHz)

Voltage Range = 1.6V

( )sV

MradKVCO 2551.6V

MHz652==

π

• Step 6 – Determine Charge Pump Current & Filter Cap

( )

( )pF

skrad

sVMradA

C

AI

2.62714322

25525

25Set

21 =

=

=

π

µ

µ

• Step 7 – Determine Filter R and Secondary Cap ( )

( )Ω=

== kpF

skradC

Rn

8.312.62714

707.022

1ωζ

pFCpFCC 622.610 2

12 =⇒=<

PLL Linear Phase Model

30

θoutθref

θout(s)θref(s)

20log10

ω3dB = 1.47Mrad/s

θout(s)θvcon(s)

20log10

PLL Linear Phase Model: Frequency Step Response

31

θoutθref

θref(s)=Frequency Step Input: ∆ωs2 = ∆510 Mrad/sec

32s2

No Cycle Slips Observedwith Linear Model

PLL Behavioral Model • From my MSc thesis:

http://www.ece.tamu.edu/~spalermo/docs/msc_thesis_sam_palermo.pdf • Written in SpectreHDL • Also look at CppSim: http://www.cppsim.com/

32

// Multi-Band Phase Locked Loop Frequency Synthesizer Macromodel // Main Spectre File // Samuel Palermo simulator lang=spectre include "/home/samuel/research/pll/macromodels/pd/dig_pfd/dig_pfd.def" include "/home/samuel/research/pll/macromodels/lpf/lpf.def" ahdl_include "/home/samuel/research/pll/macromodels/vco/vco.def" ahdl_include "/home/samuel/research/pll/macromodels/vco/switch_vco.def" ahdl_include + "/home/samuel/research/pll/macromodels/divider/divider.def" include "/home/samuel/research/pll/macromodels/vco/reference.def" // Power Supply vdd dd 0 vsource dc=1 // Reference Signal xref 0 control fref reference vcontrol control 0 vsource type=pwl wave=[0 0.64 1u 0.64] // Digital Tri-State Phase/Frequency Comparator xdig_pfd 0 dd fref fvco up upbar down downbar dig_pfd // Charge Pump iup dd 1 isource dc=25u idown 2 0 isource dc=25u gup 1 vd up 0 relay vt1=0 vt2=1 ropen=100M rclosed=1m gupbar 1 0 upbar 0 relay vt1=0 vt2=1 ropen=100M rclosed=1m gdown vd 2 down 0 relay vt1=0 vt2=1 ropen=100M rclosed=1m gdownbar dd 2 downbar 0 relay vt1=0 vt2=1 ropen=100M rclosed=1m // Loop Filter xfilter 0 vd lpf gvdgnd vd 0 vd_gnd 0 relay vt1=0 vt2=1 ropen=100M rclosed=10 // Voltage Controlled Oscillator //xvco vd out vco (gain=40e6 fc=256e6) xvco 0 vd out nv_temp vd_gnd + switch_vco (u=0.8 d=-0.8 gain=40e6 fc=256e6) // Divider xdivider 0 out fvco buffer n_temp divider (divisor=32) op dc

timedom tran stop=20u step=20p ic=all maxstep=20p skipdc=yes relref=alllocal simulator lang=spice .ic vd=0 save vd control fref fvco nv_temp vd_gnd .OPTIONS rawfmt=psfbin save=selected diagnose=yes vabstol=.01 + reltol=.99

*********************************************************************** // Digital Phase Frequency Detector Macromodel // Samuel Palermo subckt dig_pfd (gnd dd fref fvco up upbar down downbar) ahdl_include "/home/samuel/research/pll/macromodels/pd/dig_pfd/dff.def" ahdl_include + "/home/samuel/research/pll/macromodels/pd/dig_pfd/nand.def" xdffup gnd dd fref up upbar r dff xdffdown gnd dd fvco down downbar r dff xnand gnd up down r nand ends dig_pfd

*********************************************************************** // D Flip Flop Macromodel // Samuel Palermo module dff(gnd, D, CLK, Q, QBAR, R) () node [V, I] gnd, D, CLK, Q, QBAR, R ; real Q_temp; real QBAR_temp; initial Q_temp=0; QBAR_temp=1; analog if ($threshold (V(CLK, gnd)-1, 1)) if (V(D,gnd)==1) Q_temp=1; QBAR_temp=0; else Q_temp=0; QBAR_temp=1; if (V(R, gnd)==0) Q_temp=0; QBAR_temp=1;

PLL Frequency Step Response: Linear vs Behavioral Model

33

θref(s)=Frequency Step Input: ∆ωs2 = ∆510 Mrad/sec

32s2

No Cycle Slips Observedwith Linear Model

Cycle Slips