lecture2 - mosfet

8/6/2019 Lecture2 - MOSFET

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ECE Computer Aided Design (EC543L1)

MOS Field Effect Transistor Page 1

METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR

1.0Introduction In this chapter, we introduce the second major type of transistors (the first one being

the bipolar junction transistors discussed in earlier electronics courses), the field-effecttransistors (FET).

There are two general classes of FETs:o the metal oxide semiconductor FET (MOSFET)o thejunction FET(JFET)

The MOSFET has led to the second electronics revolution in the 1970s and 1980s, inwhich the microprocessor has made possible powerful desktop computers andsophisticated hand-held calculators.

The MOSFET can be made very small, so high-density VLSI circuits includingmicroprocessors and memories can be fabricated.

In the MOSFET, the current is controlled by an electric field applied perpendicular toboth the semiconductor surface and to the direction of current.

The phenomenon used to modulate the conductance of a semiconductor, or controlcurrent in a semiconductor, by applying an electric field perpendicular to the surface iscalled the field effect.

The basic transistor principle is that the voltage between two terminals controls thecurrent through the third terminal.

1.1.1 Two-Terminal MOS Structure

The heart of the MOSFET is the metal-oxide-semiconductor capacitor shown inFigure 1.1

Figure 1.1


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The metal may be aluminum or some other type of metal. In many cases, the metalis replaced by a high-conductivity polycrystalline silicon layer deposited on the oxide.

The parameter tox is the thickness of the oxide and ox is the oxide permittivity (=3.90). The physics of the MOS structure can be explained with the aid of a simple parallel-platecapacitor. Figure 1.2(a) below shows a parallel-plate capacitor with the top plate at a negative voltage

with respect to the bottom plate.

Figure 1.2(a)

An insulator material separates the two plates. With this bias, a negative chargeexists on the top plate, a positive charge exists on the bottom plate, and an electricfield is induced between the two plates as shown.

A MOS capacitor with a p-type semiconductor substrate is shown in Figure 1.2(b)

Figure 1.2(b)

The top-metal terminal, also called the gate, is at a negative voltage with respect tothe semiconductor substrate. From the example of the parallel-plate capacitor, anegative charge will exist on the top metal plate and an E-field will be induced in thedirection shown in the figure.


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If the electric field penetrates the semiconductor, the holes in the p-type materialsemiconductor will experience a force towards the oxide-semiconductor interface.At equilibrium, the distribution of charge in the MOS capacitor is shown in Figure1.2(c).

Figure 1.2(c)

An accumulation layer of positively-charged holes in the oxide-semiconductor junction corresponds to the positive charge on the bottom plate of the MOScapacitor.

Figure 1.3(a) shows the same MOS capacitor, but with the polarity of the appliedvoltage reversed. A positive charge now exists on the top metal plate and theinduced electric field is in the opposite direction, as shown.

Figure 1.2(a)

If the electric field penetrates the semiconductor, holes in the p-type material willexperience a force away from the oxide-semiconductor interface. As the holes arepushed away from the interface, a negative space-charge region is created, due tothe fixed acceptor impurity atoms. The negative charge in the induced depletionregion corresponds to the negative charge on the bottom plate of the MOS


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capacitor. Figure 1.3(b) shows the equilibrium distribution of charge in the MOScapacitor with this applied voltage.

Figure 1.3(b)

When a larger positive voltage is applied to the gate, the magnitude of the inducedelectric field increases. Minority carrier electrons are attracted to the oxide-semiconductor interface, as shown in Figure 1.3(c). This region of minority carrierelectrons is called an electron inversion layer. The magnitude of the charge in theinversion layer is a function of the applied gate voltage.

Figure 1.3(c)

The same basic charge distributions can be obtained in a MOS capacitor with an n-type semiconductor substrate. Figure 1.4(a) shows this MOS capacitor structure,with a positive voltage applied to the top gate terminal.


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Figure 1.4(a)

A positive charge is created on the top gate and an electric field is induced in thedirection shown. In this situation, an accumulation layer of electrons is induced inthe n-type semiconductor.

Figure 1.4(b) below shows the case when a negative voltage is applied to the gateterminal. A positive space-charge region is induced in the n-type substrate by theinduced electric field.

Figure 1.4(b)

When a larger negative voltage is applied, a region of positive charge is created atthe oxide-semiconductor interface, as shown in Figure 1.4(c). This region of minority

carrier holes is called a hole inversion layer. The magnitude of the positive charge inthe inversion layer is a function of the applied gate voltage.


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Figure 1.4(c)

The term enhancement mode means that the voltage must be applied to the gate tocreate an inversion layer.

For the MOS capacitor with a p-type substrate, a positive gate voltage must beapplied to create the electron inversion layer; for the MOS capacitor with an n-typesubstrate, a negative gate voltage must be applied to create the hole inversion layer.

1.1.2 n-Channel Enhancement-Mode MOSFET

Figure 1.5(a) shows a simplified cross section of a MOS field-effect transistor.

Figure 1.5(a)


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The gate, oxide, and p-type substrate regions are the same as those of a MOScapacitor. In addition, we now have two n-regions, called the source terminal anddrain terminal. The current in a MOSFET is the result of the flow of charge in theinversion layer, also called the channel region, adjacent to the oxide-semiconductorinterface.

The channel length L and channel W are defined on the figure. The channel length ofa typical integrated circuit MOSFET is less than 1 um (10-6 m), which means thatMOSFETs are small devices. The oxide thicknes tox is typically on the order of 400angstroms, or less.

Figure 1.5(b) shows a more detailed cross section of a MOSFET fabricated into anintegrated circuit configuration. A thick oxide, called the field oxide, is depositedoutside the area in which the metal interconnect lines are formed. The gate materialis usually heavily doped polysilicon.

Figure 1.5(b)

With zero bias applied to the gate, the source and drain terminals are separated bythe p-region as shown in Figure 1.6(a). This is equivalent to two back-to-back diodes,as shown in Figure 1.6(b). The current in this case is essentially zero.


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Figure 1.6(a)

Figure 1.6(b)

If a large enough positive gate voltage is applied, an electron inversion layer iscreated at the oxide-semiconductor interface and this layer connects the n-sourceto the n-drain, as shown in Figure 1.6(c). A current can then be generated betweenthe source and drain terminals.


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Figure 1.6(c)

Since a voltage must be applied to the gate to create the inversion charge, thistransistor is called an enhancement-mode MOSFET. Also, since the carriers in theinversion layer are electrons, this device is also called an n-channel MOSFET(NMOS).

The source terminal supplies carriers that flow through the channel and the drainterminal allows the carriers to drain from the channel. For the NMOS, electrons flowfrom the source to the drain with an applied drain-to-source voltage, which meansthe conventional current enters the drain and leaves the source.

The magnitude of the current is a function of the amount of charge in the inversionlayer, which in turn is a function of the applied gate voltage.

Since the gate terminal is separated from the channel by an oxide or insulator, thereis no gate current.

Similarly, since the channel and substrate are separated by a space-charge region,there is essentially no current through the substrate.

1.1.3 Ideal MOSFET Current-Voltage Characteristics

The threshold voltage, VTH, of the n-channel MOSFET is defined as the appliedvoltage needed to create an inversion charge in which the density is equal to theconcentration of majority carriers in the semiconductor substrate.

Simply put, VTH can be thought of as the gate voltage required to turn on thetransistor.


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For the n-channel enhancement-mode MOSFET, the threshold voltage is positive. If the gate voltage is less than the threshold voltage, the current in the device is

essentially zero. If the gate voltage is greater than the threshold voltage, a drain-to-source current is generated as the drain-to-source voltage is applied.

Figure 1.7(a) shows an n-channel enhancement-mode MOSFET with the source andsubstrate terminals connected to ground. The gate-to-source voltage is less than thethreshold voltage, and there is a small drain-to-source voltage. With this biasconfiguration, there is no electron inversion layer, the drain-to-substrate pn junctionis reversed biased, and the drain current is zero.

Figure 1.7(a)

Figure 1.7(b) shows the same MOSFET with an applied gate voltage greater than thethreshold voltage. In this situation, an electron inversion layer is created and, whena small drain voltage is applied, electrons in the inversion layer flow from the sourceto the positive drain terminal. The conventional current enters the drain terminaland leaves the source terminal.


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Figure 1.7(b)

The iD versus vDS characteristics for small values of vDS is shown below in Figure 1.8.

Figure 1.8

When vGS < VTH, the drain current is zero. When vGS > VTH, the channel inversion charge is formed and the drain current

increases with vDS. Then with a larger gate voltage, a larger inversion charge densityis created, and the drain current is greater for a given value of vDS.

Figure 1.9(a) shows the basic MOS structure for vGS > VTH and a small applied vDS.

Figure 1.9(b) shows the situation when vDS increases. As the drain voltage increases,the voltage drop across the oxide near the drain terminal decreases, which meansthat the induced inversion charge density near the drain also decreases. Theincremental conductance of the channel at the drain then decreases, which causesthe slope of the channel at the drain then decreases, which causes the slope of the iDversus vDS curve to decrease.


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Figure 1.9

As vDS increases to the point where the potential difference across the oxide at thedrain terminal is equal to VTH, the induced inversion charge density at the drainterminal is zero. This effect is shown schematically in Figure 1.9(c). For this


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condition, the incremental channel conductance at the drain is zero, which meansthat the slope of iD versus vDS curve is zero. At this point, we can write

vGS vDSsat = VTHor

vDSsat = vGS VTHwhere vDS(sat) is the drain-to-source voltage that produces zero inversion chargedensity at the drain terminal.

When vDS becomes larger than vDS(sat), the point in the channel at which theinversion charge is just zero moves toward the source terminal. In this case,electrons enter the channel at the source, travel through the channel toward the

drain, and then, at the point where the charge goes to zero, are injected into thespace-charge region, where they are swept by the E-field to the drain contact. In theideal MOSFET, the drain current is constant for vDS > vDS(sat). This is shown in Figure1.9(d).

Figure 1.10 shows the family of curves of iD versus vDS for a given vGS.

Figure 1.10

1.1(a)

1.1(b)


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The region for which vDS < vDS(sat) is known as the nonsaturation or triode region.The ideal current-voltage characteristics in this region are described by the equation

iD = k2vGS VTHvDS vDS In the saturation region, the ideal current-voltage characteristics for vGS > VTH are

described by the equation

iD = kvGS VTH In the saturation region, since the ideal drain current is independent of the drain-to-

source voltage, the incremental or small-signal resistance is infinite.

The parameter kn is called the conduction parameter for the n-channel device and isgiven by

k = WC2L where Cox is the oxide capacitance per unit area. The capacitance is given by

C = t where tox is the oxide thickness and ox is the oxide permittivity. The parameter n isthe mobility of the electrons in the inversion layer. The channel width W and the

channel length L were shown in Figure 1.5(a).

The conduction parameter is a function of both electrical and geometric parameters.The oxide capacitance and carrier mobility are essentially constants for a givenfabrication technology. The geometry, or width-to-length ratio W/L, is a variable inthe design of MOSFETs that is used to produce current-voltage characteristics inMOSFET circuits.

We can rewrite the conduction parameter in the form

k = k2 WL where kn = nCox. Normally, kn is considered to be a constant, so Eq. 5.3(b)emphasized that the width-to-length ratio W/L is the transistor design variable.

Example 1.1. Consider an n-channel enhancement mode MOSFET with the followingparameters: VTH = 0.75 V, W = 40 um, L = 4 um, n = 650 cm

2/V-s, tox = 450 angstroms and

1.2(a)

1.2(b)

1.3(a)

1.3(b)


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ox = (3.9)(8.85 x 10-14) F/cm. Determine the current when VGS = 2VTH, for the transistor

biased in the saturation region.

Example 1.2. An n-channel enhancement-mode MOSFET has a threshold voltage of VTH =1.2 V and an applied gate-to-source voltage of vGS = 2 V. Determine the region of operation

when: (i) vDS = 0.4 V; (ii) vDS = 5 V.

Example 1.3. The NMOS device described in the above example have parameters W = 100um, L = 7 um, tox = 450 , n = 500 cm

2/V-s, and = 0. (a) Calculate the conductionparameter kn for the device. (b) Calculate the drain current for each bias condition.

Example 1.4. An NMOS transistor with VTH = 1 V has a drain current iD = 0.8 mA when vGS = 3V and vDS = 4.5 V. Calculate the drain current when (a) vGS = 2 V, vDS = 4.5 V; and (b) vGS = 3 V,vDS = 1 V.

1.1.4Circuit Symbols and Conventions

The conventional circuit symbol for the n-channel enhancement-mode MOSFET isshown in Figure 1.11(a); the simplified circuit symbol in Figure 1.11(b). In the secondcase, the source is assumed to be connected together to the substrate terminal.

Figure 1.11


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1.1.5 Additional MOSFET Structures and Circuit Sybmols

n-Channel Depletion-Mode MOSFET

Figure 1.12

o Figure 1.12(a) shows the cross-section of an n-channel depletion-mode MOSFET.o The term depletion-mode means that a channel exists even at zero gate voltage.

A negative gate voltage must be applied to the n-channel depletion MOSFET toturn the device off.

o Figure 1.12(b) shows the n-channel depletion-mode MOSFET with a negativeapplied gate-to-source voltage. A negative gate voltage induces a space-charge


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region under the oxide, thereby reducing the thickness of the n-channel region.The reduced thickness decreases the channel conductance, which in turnreduces the drain current. When the gate voltage is equal to the thresholdvoltage, which is negative for this device, the induced space-charge regionextends completely through the n-channel region, and the current goes to zero.

A positive gate voltage creates an electron accumulation layer, as shown inFigure 1.12(c) which increases the drain current.

o The general iD versus vDS family of curves for the n-channel depletion-modeMOSFET is shown in Figure 1.13.

Figure 1.13

o The conventional and simplified schematic symbol for n-channel depletion-modeMOSFET is shown in Figure 1.14.


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Figure 1.14

p-Channel MOSFETso Figures 1.15(a) and 1.15(b) show cross sections of a p-channel enhancement-

mode and a p-channel depletion-mode MOSFET, as well as the biasingconfigurations and current directions.

Figure 1.15

o The types of impurity doping in the source, drain and substrate regions of the p-channel MOSFETs or PMOS transistors are reversed compared to the n-channeldevices.

o In the p-channel enhancement-mode device, a negative gate-to-source voltagemust be applied to create the inversion layer, or channel region of holes that


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connects the source and the drain regions. The threshold voltage for the p-channel device is negative for an enhancement-mode device; positive for a p-channel depletion-mode device.

o Because holes flow from the source to the drain, the conventional current entersthe source and leaves the drain.

o The operation of the p-channel device is the same as that of the n-channeldevice, except that the hole is the charge carrier, rather than the electron, andthe conventional current direction and voltage polarities are reversed.

o For the p-channel device biased in the nonsaturation region, the current is givenby

iD = k2vSG + VTHvSD vSD o In the saturation region, the current is

iD = kvSG + VTHo The parameter kp is the conduction parameter for the p-channel device and is

given by

k = WC2L where W, L and Cox are the channel width, length and oxide capacitance per unitarea, as previously defined. The parameter p is the mobility of holes in the holeinversion layer. In general, the hole inversion layer mobility is less than theelectron inversion layer mobility. The above equation can be rewritten as

k = k

2 WL

where kp = pCox.

o For a p-channel MOSFET biased in the saturation region, we havevSD > vSDsat = vSG + VTH

Example 1.5. Consider a depletion-mode p-channel MOSFET for which kp = 0.2 mA/V2, VTH =

0.5 V and iD = 0.5 mA. Determine the source-to-drain voltage required to bias a p-channeldepletion-mode MOSFET in the saturation region.

1.4(a)

1.4(b)

1.5(a)

1.5(b)

1.6


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Example 1.6. (a) For a PMOS device, the threshold voltage is VTH = -2 V and the appliedsource-to-gate voltage is vSG = 3 V. Determine the region of operation when (i) vSD = 0.5 V;(ii) vSD = 2 V; and (iii) vSD = 5 V. (b) Repeat part (a) for a depletion-mode PMOS device withVTH = 0.5 V.

o The conventional and simplified circuit symbol for the p-channel enhancement-mode MOSFET appears in Figure 1.16.

Figure 1.16

o The conventional and simplified schematic symbol for the p-channel depletion-mode MOSFET appears in Figure 1.17.

Figure 1.17


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Complementary MOSFET (CMOS)o Complementary MOS (CMOS) technology uses both n-channel and p-channel

devices in the same circuit. Figure 1.18 shows the cross section of n-channel andp-channel devices fabricated on the same chip.

Figure 1.18

o CMOS circuits, in general, are more complicated to fabricate than circuits usingentirely NMOS or PMOS devices. Yet, CMOS circuits have great advantages overjust NMOS or PMOS circuits.

o In order to fabricate n-channel and p-channel devices that are electricallyequivalent, the magnitude of the threshold voltages must be equal, and the n-channel and p-channel conduction parameters must be equal. Since, in general,the mobilities of the electrons and holes are not equal, the design of theequivalent transistors involves adjusting the width-to-length ratios of thetransistors.


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1.1.6 Summary of Transistor Operation

1.1.7 Nonideal Current-Voltage Characteristics

The five nonideal effects in the current-voltage characteristics of MOS transistors areo Finite output resistance in the saturation regiono The body effecto Subthreshold conductiono Breakdown effectso Temperature effects

Finite output resistanceo In the ideal case, when a MOSFET is biased in the saturation region, the drain

current iD is independent of drain-to-source voltage vDS. However, in actualMOSFET iD versus vDS characteristics, a nonzero slope does exist beyond thesaturation.

o For vDS > vDS(sat), as vDS is increased, the effective channel length decreases,producing the phenomenon called the channel length modulation.

o An exaggerated view of the current-voltage characteristics is shown in Figure1.19. The curves can be extrapolated so that they intercept the voltage axis at apoint vDS = -VA. The positive quantity VA is similar to the Early voltage of a bipolar

transistor.o At saturation, for an n-channel device, the current iD can then be expressed as

iD = kvGS VTH1 + vDSwhere the quantity is called the channel length modulation parameter.

1.7


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Note that

VA = 1

Figure 1.19

o The output resistance due to channel length modulation is defined asr = iDvDS

o From Equation 1.7, the output resistance evaluated at Q-point isr = 1kVGSQ VTH

or approximately

r = 1IDQ =VAIDQ

o The output resistance ro is also a factor in the small-signal equivalent circuit ofthe MOSFET.

Example 1.7. For an NMOS enhancement-mode device, the parameters are: VTH = 0.8 V andkn = 0.1 mA/V

2. The device is biased at vGS = 2.5 V. Calculate the drain current when vDS = 2 Vand vDS = 10 V for: (a) = 0 and (b) = 0.02 V

-1. (c) Calculate the output resistance ro forparts (a) and (b).

1.8

1.9a

1.9b


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Body Effecto Up to this point, we have assumed that the substrate, or body, is connected to

the source. For this bias condition, the threshold voltage is a constant.o In integrated circuits, however, the substrates of all n-channel MOSFETs are

usually common and are tied to the most negative potential in the circuit, as

shown in Figure 1.20.

Figure 1.20

o A change in the source-substrate junction voltage changes the threshold voltage;this is called body effect.

o Considering the n-channel device shown in Figure 1.21, to maintain a zero- orreversed-biased source-substrate pn junction, we must have vSB 0.

Figure 1.21


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o The threshold voltage for this condition is given by VTH = VTO + 2+ vSB 2

where VTO is the threshold voltage for vSB = 0; , called the bulk threshold or

body-effect parameter, is related to device properties, and is typically on theorder of 0.5 V1/2; and f is a semiconductor parameter, typically on the order of0.35 V, and is a function of the semiconductor doping.

o We see from the Equation 1.10 that the threshold voltage in n-channel devicesincreases due to this body effect.

Example 1.8. An NMOS transistor has parameters VTO = 1 V, = 0.35 V1/2, and f = 0.35 V.

Calculate the threshold voltage when: (a) vSB = 0, (b) vSB = 1 V, and (c) vSB = 4 V.

Subthreshold Conductiono If we consider the ideal current-voltage relationship for the n-channel MOSFET

biased in the saturation region, we have, from Equation 1.2(b),

iD = kvGS VTHTaking the square root of both sides of the equation, we obtain

iD = kvGS VTHFrom this, we see that iD is a linear function of vGS. Figure 1.22 shows a plot ofthis ideal relationship.

Figure 1.22

1.10

1.11


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o Also plotted are experimental results, which show that when vGS is slightly lessthan VTH, the drain current is not zero, as previously assumed. This current iscalled the subthreshold current.

Breakdown Effectso The drain-to-substrate pn junction may breakdown if the applied drain voltage is

too high and avalanche multiplication occurs.o As the size of the device becomes smaller, another breakdown mechanism,

called punch-through, may become significant. Punch-through occurs when thedrain voltage is large enough for the depletion region around the drain to extendcompletely through the channel to the source terminal. This effect also causesthe drain current to increase rapidly with only a small increase in drain voltage.

o A third breakdown mechanism is called near-avalanche or snapback breakdown.This breakdown process is due to second-order effects within the MOSFET. Thisis basically due to parasitic bipolar transistor action that increases with the drain

voltage.o If the electric field in the oxide becomes large enough, breakdown can also occurin the oxide.

Temperature Effectso Both the threshold voltage VTH and conduction parameter kn are functions of

temperature.o The magnitude of the threshold voltage decreases with temperature, which

means that the drain current increases with temperature at a given VGS.o The conduction parameter, on the other hand, is a direct function of the

inversion carrier mobility, which decreases as the temperature increases.

1.1.8 SPICE Models for MOSFET MOSFET description

M L=

+W=

.model Level=

Models for MOSFETo

Level = 1 >> Schichman-Hodges Modelo Level = 2 >> advanced Schichman-Hodges Model

o Level = 3 >> modified Schichman-Hodges model, semi-empirical short channelmodel


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Some Level 1 SPICE model parametersMathematical Symbol SPICE Symbol Description Unit

VTO VTO Threshold voltage V GAMMA Body effect coefficient V1/2

2f PHI Fermi level potential Vtox TOX Gate oxide thickness m

n or p UO Channel mobility cm2/V-s

LAMBDAChannel length modulation

coefficientV-1

kn' or kp KP Transconductance parameter A/V2

Level 1 SPICE Models for NMOS and PMOS Devices

lecture2 - mosfet

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