lecturer michael s. mccorquodale authors michael s. mccorquodale, fadi h. gebara, keith l. kraver,...
TRANSCRIPT
LecturerMichael S. McCorquodale
AuthorsMichael S. McCorquodale, Fadi H. Gebara, Keith L. Kraver, Eric D. Marsman, Robert M. Senger, and Richard B. Brown
A Top-Down Microsystems Design Methodology and Associated Challenges
Solid State Electronics LaboratoryCenter for Wireless Integrated MicrosystemsDepartment of Electrical Engineering and Computer ScienceUniversity of MichiganAnn Arbor, MI USA 48109-2122
Design Automation and Test Europe Conference, Munich, Germany, March 2003
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Outline
• Motivation
• Microsystems: Anatomy
• Bottom-Up Design Methodology
• WIMS Microcontroller
• Design Framework
• Top-Down Design Methodology
• Gaps and Solutions
• Conclusions
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Motivation• Discuss design trends and challenges in
microsystems technology• Leverage advances in mixed-signal SoC
design automation• Determine a design methodology and
framework appropriate for microsystems technology
• Implement methodology in a microsystem design
• Demonstrate increased design efficiency and verification
• Identify gaps in tool suite and promote development of required capabilities
Motivation Microsystems Bottom-Up Microcontroller Framework Top-Down Gaps & Solns. Conclusions
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The anatomy of a generalized wireless integrated microsystem (WIMS). Key technologies and associated development tools are shown
Microsystems: Anatomy
MEMS Analog Mixed-Signal Digital/VLSI
Antenna
MicroprocessorWirelessInterface
Clock
Sensor/Actuator Interface
Sensor
Actuator
BasebandModem
RFIC/RFMEMS
FE Tools
AHDLCustom IC Tools
VHDL Synthesis
Tools
AHDL Custom
RFIC Tools
DAC
ADC
MS-HDL Custom IC Tools
Motivation Microsystems Bottom-Up Microcontroller Framework Top-Down Gaps & Solns. Conclusions
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The anatomy of a generalized wireless integrated microsystem (WIMS). Key technologies and associated development tools are shown
Microsystems: Anatomy
MEMS Analog Mixed-Signal Digital/VLSI
Antenna
MicroprocessorWirelessInterface
Clock
Sensor/Actuator Interface
Sensor
Actuator
BasebandModem
RFIC/RFMEMS
FE Tools
AHDLCustom IC Tools
VHDL Synthesis
Tools
AHDL Custom
RFIC Tools
DAC
ADC
MS-HDL Custom IC Tools
Motivation Microsystems Bottom-Up Microcontroller Framework Top-Down Gaps & Solns. Conclusions
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Mic
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l S. M
cCo
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Un
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sity
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Mic
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The anatomy of a generalized wireless integrated microsystem (WIMS). Key technologies and associated development tools are shown
Microsystems: Anatomy
MEMS Analog Mixed-Signal Digital/VLSI
Antenna
MicroprocessorWirelessInterface
Clock
Sensor/Actuator Interface
Sensor
Actuator
BasebandModem
RFIC/RFMEMS
FE Tools
AHDLCustom IC Tools
VHDL Synthesis
Tools
AHDL Custom
RFIC Tools
DAC
ADC
MS-HDL Custom IC Tools
Motivation Microsystems Bottom-Up Microcontroller Framework Top-Down Gaps & Solns. Conclusions
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Mic
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l S. M
cCo
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Un
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sity
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Mic
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an
The anatomy of a generalized wireless integrated microsystem (WIMS). Key technologies and associated development tools are shown
Microsystems: Anatomy
MEMS Analog Mixed-Signal Digital/VLSI
Antenna
MicroprocessorWirelessInterface
Clock
Sensor/Actuator Interface
Sensor
Actuator
BasebandModem
RFIC/RFMEMS
FE Tools
AHDLCustom IC Tools
VHDL Synthesis
Tools
AHDL Custom
RFIC Tools
DAC
ADC
MS-HDL Custom IC Tools
Motivation Microsystems Bottom-Up Microcontroller Framework Top-Down Gaps & Solns. Conclusions
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Mic
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l S. M
cCo
rqu
od
ale
Un
iver
sity
of
Mic
hig
an
The anatomy of a generalized wireless integrated microsystem (WIMS). Key technologies and associated development tools are shown
Microsystems: Anatomy
MEMS Analog Mixed-Signal Digital/VLSI
Antenna
MicroprocessorWirelessInterface
Clock
Sensor/Actuator Interface
Sensor
Actuator
BasebandModem
RFIC/RFMEMS
FE Tools
AHDLCustom IC Tools
VHDL Synthesis
Tools
AHDL Custom
RFIC Tools
DAC
ADC
MS-HDL Custom IC Tools
Motivation Microsystems Bottom-Up Microcontroller Framework Top-Down Gaps & Solns. Conclusions
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Bottom-Up Design Methodology
Verification: DRC, LVS (Top Routing Only), Parasitic Extraction and Backannotation(IC Tool)
Digital Specification Analog Specification Mechanical Specification
Custom Analog Design(SPICE)
Custom Mechanical Design(FE)
Synthesis/APR/Timing(Synthesizer)
Analog Physical Design(IC Tool)
DigitalLibrary
Tapeout
ProcessLibrary
Digital Design(HDL)
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Analog Macro Mechanical MacroDigital Macro
System Specification and Design Partition
Macro Automatic Place and Route(APR and IC Tool)
Verification: DRC, LVS (Top Routing Only), Parasitic Extraction and Backannotation(IC Tool)
Digital Specification Analog Specification Mechanical Specification
Custom Analog Design(SPICE)
Custom Mechanical Design(FE)
Synthesis/APR/Timing(Synthesizer)
Analog Physical Design(IC Tool)
DigitalLibrary
Tapeout
ProcessLibrary
Digital Design(HDL)
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Analog Macro Mechanical MacroDigital Macro
System Specification and Design Partition
Macro Automatic Place and Route(APR and IC Tool)
Motivation Microsystems Bottom-Up Microcontroller Framework Top-Down Gaps & Solns. Conclusions
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Bottom-Up Design Methodology
Verification: DRC, LVS (Top Routing Only), Parasitic Extraction and Backannotation(IC Tool)
Digital Specification Analog Specification Mechanical Specification
Custom Analog Design(SPICE)
Custom Mechanical Design(FE)
Synthesis/APR/Timing(Synthesizer)
Analog Physical Design(IC Tool)
DigitalLibrary
Tapeout
ProcessLibrary
Digital Design(HDL)
Dig
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Analog Macro Mechanical MacroDigital Macro
System Specification and Design Partition
Macro Automatic Place and Route(APR and IC Tool)
Verification: DRC, LVS (Top Routing Only), Parasitic Extraction and Backannotation(IC Tool)
Digital Specification Analog Specification Mechanical Specification
Custom Analog Design(SPICE)
Custom Mechanical Design(FE)
Synthesis/APR/Timing(Synthesizer)
Analog Physical Design(IC Tool)
DigitalLibrary
Tapeout
ProcessLibrary
Digital Design(HDL)
Dig
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Analog Macro Mechanical MacroDigital Macro
System Specification and Design Partition
Macro Automatic Place and Route(APR and IC Tool)
Motivation Microsystems Bottom-Up Microcontroller Framework Top-Down Gaps & Solns. Conclusions
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Bottom-Up Design Methodology
Verification: DRC, LVS (Top Routing Only), Parasitic Extraction and Backannotation(IC Tool)
Digital Specification Analog Specification Mechanical Specification
Custom Analog Design(SPICE)
Custom Mechanical Design(FE)
Synthesis/APR/Timing(Synthesizer)
Analog Physical Design(IC Tool)
DigitalLibrary
Tapeout
ProcessLibrary
Digital Design(HDL)
Dig
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An
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Me
ch
an
ica
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Analog Macro Mechanical MacroDigital Macro
System Specification and Design Partition
Macro Automatic Place and Route(APR and IC Tool)
Verification: DRC, LVS (Top Routing Only), Parasitic Extraction and Backannotation(IC Tool)
Digital Specification Analog Specification Mechanical Specification
Custom Analog Design(SPICE)
Custom Mechanical Design(FE)
Synthesis/APR/Timing(Synthesizer)
Analog Physical Design(IC Tool)
DigitalLibrary
Tapeout
ProcessLibrary
Digital Design(HDL)
Dig
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Analog Macro Mechanical MacroDigital Macro
System Specification and Design Partition
Macro Automatic Place and Route(APR and IC Tool)
Motivation Microsystems Bottom-Up Microcontroller Framework Top-Down Gaps & Solns. Conclusions
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Bottom-Up Design Methodology
Verification: DRC, LVS (Top Routing Only), Parasitic Extraction and Backannotation(IC Tool)
Digital Specification Analog Specification Mechanical Specification
Custom Analog Design(SPICE)
Custom Mechanical Design(FE)
Synthesis/APR/Timing(Synthesizer)
Analog Physical Design(IC Tool)
DigitalLibrary
Tapeout
ProcessLibrary
Digital Design(HDL)
Dig
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An
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Me
ch
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ica
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Analog Macro Mechanical MacroDigital Macro
System Specification and Design Partition
Macro Automatic Place and Route(APR and IC Tool)
Verification: DRC, LVS (Top Routing Only), Parasitic Extraction and Backannotation(IC Tool)
Digital Specification Analog Specification Mechanical Specification
Custom Analog Design(SPICE)
Custom Mechanical Design(FE)
Synthesis/APR/Timing(Synthesizer)
Analog Physical Design(IC Tool)
DigitalLibrary
Tapeout
ProcessLibrary
Digital Design(HDL)
Dig
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Analog Macro Mechanical MacroDigital Macro
System Specification and Design Partition
Macro Automatic Place and Route(APR and IC Tool)
Motivation Microsystems Bottom-Up Microcontroller Framework Top-Down Gaps & Solns. Conclusions
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Bottom-Up Design Methodology
Verification: DRC, LVS (Top Routing Only), Parasitic Extraction and Backannotation(IC Tool)
Digital Specification Analog Specification Mechanical Specification
Custom Analog Design(SPICE)
Custom Mechanical Design(FE)
Synthesis/APR/Timing(Synthesizer)
Analog Physical Design(IC Tool)
DigitalLibrary
Tapeout
ProcessLibrary
Digital Design(HDL)
Dig
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An
alo
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Me
ch
an
ica
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Analog Macro Mechanical MacroDigital Macro
System Specification and Design Partition
Macro Automatic Place and Route(APR and IC Tool)
Verification: DRC, LVS (Top Routing Only), Parasitic Extraction and Backannotation(IC Tool)
Digital Specification Analog Specification Mechanical Specification
Custom Analog Design(SPICE)
Custom Mechanical Design(FE)
Synthesis/APR/Timing(Synthesizer)
Analog Physical Design(IC Tool)
DigitalLibrary
Tapeout
ProcessLibrary
Digital Design(HDL)
Dig
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Me
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Analog Macro Mechanical MacroDigital Macro
System Specification and Design Partition
Macro Automatic Place and Route(APR and IC Tool)
Motivation Microsystems Bottom-Up Microcontroller Framework Top-Down Gaps & Solns. Conclusions
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Bottom-Up Design Methodology
The Problems
• No opportunity for architectural studies
• Time-consuming design iteration
• Cross-domain verification at top level only
• Time-consuming system level simulation, if it is even possible
Motivation Microsystems Bottom-Up Microcontroller Framework Top-Down Gaps & Solns. Conclusions
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WIMS Microcontroller
• TSMC 0.18 micron mixed-mode
• 16-bit 3-stage pipeline core
• Analog front end (AFE)
• MEMS-based clock generator
• 64KB on-chip SRAM
• Timer and serial interfaces
• 1.5 million transistors
• 10.24mm2Die micrograph of the fabricated microsystem
Motivation Microsystems Bottom-Up Microcontroller Framework Top-Down Gaps & Solns. Conclusions
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Design Framework: Requirements
• System level simulation support (HDL)
• Cross-domain verification at any level for MEMS, analog, and digital electronics
• Finite element simulation
• Active device and HDL simulation
• Parasitic extraction
• Co-simulation of primitives and HDL
• Timing verification
• HDL synthesis
• Automatic place and route
Motivation Microsystems Bottom-Up Microcontroller Framework Top-Down Gaps & Solns. Conclusions
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Design Framework: Employed
• Cadence AMSSystem modeling, primitive/HDL co-simulation, and MEMS modeling
• SpectreAnalog device level simulation
• CoventorwareFinite element analysis
• SynopsysDigital synthesis
• Cadence Silicon EnsembleAutomatic place and route
• Mentor Graphics CalibreDRC, ERC, and LVS
Motivation Microsystems Bottom-Up Microcontroller Framework Top-Down Gaps & Solns. Conclusions
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Top-Down Design Methodology
Cross- Domain Verification(Verilog with updated Verilog-A from achieved performance and/or Verilog and Verilog-A with Primitives)
Analog Model(Verilog-A)
Mechanical Model(Verilog-A)
Abstract System Model(Verilog-AMS: Verilog and Verilog-A)
DigitalLibrary
ProcessLibrary
Tapeout
Dig
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Mec
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Do
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Cross - Domain Verification(Verilog with updated Verilog - A from parasitics and/or Verilog and Verilog-A with Primitives)
Cross-Domain Verification(Verilog with updated Verilog- A with interconnect parasitics )
Analog Macro
Parasitic Extraction(IC Tool)
Extraction, Timing(Timing Tool)
Digital Macro Mechanical Macro
Parasitic Extraction(IC Tool)
Custom Analog Design(SPICE)
Mechanical Design(Finite Element)
Macro Place and Route, Layout Verification: DRC, LVS(APR and IC Tool)
Layout Parasitic Extraction (LPE) and Backannotation(IC Tool)
Synthesis/APR/Timing(Synthesis Tool)
Physical Design/Verif.(IC Tool)
Physical Design/Verif.(IC Tool)
Digital Model(Verilog)
Behavioral Verification(Verilog)
Motivation Microsystems Bottom-Up Microcontroller Framework Top-Down Gaps & Solns. Conclusions
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Top-Down Design Methodology
Cross- Domain Verification(Verilog with updated Verilog-A from achieved performance and/or Verilog and Verilog-A with Primitives)
Analog Model(Verilog-A)
Mechanical Model(Verilog-A)
Abstract System Model(Verilog-AMS: Verilog and Verilog-A)
DigitalLibrary
ProcessLibrary
Tapeout
Dig
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Do
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Mec
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Do
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Cross - Domain Verification(Verilog with updated Verilog - A from parasitics and/or Verilog and Verilog-A with Primitives)
Cross-Domain Verification(Verilog with updated Verilog- A with interconnect parasitics )
Analog Macro
Parasitic Extraction(IC Tool)
Extraction, Timing(Timing Tool)
Digital Macro Mechanical Macro
Parasitic Extraction(IC Tool)
Custom Analog Design(SPICE)
Mechanical Design(Finite Element)
Macro Place and Route, Layout Verification: DRC, LVS(APR and IC Tool)
Layout Parasitic Extraction (LPE) and Backannotation(IC Tool)
Synthesis/APR/Timing(Synthesis Tool)
Physical Design/Verif.(IC Tool)
Physical Design/Verif.(IC Tool)
Digital Model(Verilog)
Behavioral Verification(Verilog)
Motivation Microsystems Bottom-Up Microcontroller Framework Top-Down Gaps & Solns. Conclusions
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Top-Down Design Methodology
Cross- Domain Verification(Verilog with updated Verilog-A from achieved performance and/or Verilog and Verilog-A with Primitives)
Analog Model(Verilog-A)
Mechanical Model(Verilog-A)
Abstract System Model(Verilog-AMS: Verilog and Verilog-A)
DigitalLibrary
ProcessLibrary
Tapeout
Dig
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Mec
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Do
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Cross - Domain Verification(Verilog with updated Verilog - A from parasitics and/or Verilog and Verilog-A with Primitives)
Cross-Domain Verification(Verilog with updated Verilog- A with interconnect parasitics )
Analog Macro
Parasitic Extraction(IC Tool)
Extraction, Timing(Timing Tool)
Digital Macro Mechanical Macro
Parasitic Extraction(IC Tool)
Custom Analog Design(SPICE)
Mechanical Design(Finite Element)
Macro Place and Route, Layout Verification: DRC, LVS(APR and IC Tool)
Layout Parasitic Extraction (LPE) and Backannotation(IC Tool)
Synthesis/APR/Timing(Synthesis Tool)
Physical Design/Verif.(IC Tool)
Physical Design/Verif.(IC Tool)
Digital Model(Verilog)
Behavioral Verification(Verilog)
Motivation Microsystems Bottom-Up Microcontroller Framework Top-Down Gaps & Solns. Conclusions
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Top-Down Design Methodology
Cross- Domain Verification(Verilog with updated Verilog-A from achieved performance and/or Verilog and Verilog-A with Primitives)
Analog Model(Verilog-A)
Mechanical Model(Verilog-A)
Abstract System Model(Verilog-AMS: Verilog and Verilog-A)
DigitalLibrary
ProcessLibrary
Tapeout
Dig
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Do
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Mec
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Do
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Cross - Domain Verification(Verilog with updated Verilog - A from parasitics and/or Verilog and Verilog-A with Primitives)
Cross-Domain Verification(Verilog with updated Verilog- A with interconnect parasitics )
Analog Macro
Parasitic Extraction(IC Tool)
Extraction, Timing(Timing Tool)
Digital Macro Mechanical Macro
Parasitic Extraction(IC Tool)
Custom Analog Design(SPICE)
Mechanical Design(Finite Element)
Macro Place and Route, Layout Verification: DRC, LVS(APR and IC Tool)
Layout Parasitic Extraction (LPE) and Backannotation(IC Tool)
Synthesis/APR/Timing(Synthesis Tool)
Physical Design/Verif.(IC Tool)
Physical Design/Verif.(IC Tool)
Digital Model(Verilog)
Behavioral Verification(Verilog)
Motivation Microsystems Bottom-Up Microcontroller Framework Top-Down Gaps & Solns. Conclusions
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Gaps and Solutions
Gaps in the Tool Suite
MEMS and analog simulation results not automatically extracted to behavioral model
Lack of physical verification for MEMS components
No synthesis capabilities for MEMS and analog subsystems from topological or behavioral models
Inability to port designs between process technologies
Solutions: Future Direction
Custom and manual extraction: Requires design automation
Custom mod. of DRC/LVS decks: Requires support
No current solution: Requires design automation
No current solution: Requires design automation
Motivation Microsystems Bottom-Up Microcontroller Framework Top-Down Gaps & Solns. Conclusions
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Conclusions
• Microsystem design methodologies are in their infancy
• Current methodologies have originated from the disparate nature of the technology
• The proposed top-down methodology leverages advances in mixed-signal design automation
• The proposed methodology is efficient and offers superior verification as compared to current methodologies
• Gaps in tool suites exist and must be addressed for future microsystems developments
• Tool suites are disparate and can be built into a single framework
Motivation Microsystems Bottom-Up Microcontroller Framework Top-Down Gaps & Solns. Conclusions