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library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use...

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  • Library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity TopLevelModule is Port ( clk : in STD_LOGIC;
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library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity TopLevelModule is Port ( clk : in STD_LOGIC; Buttons : in std_logic_vector(3 downto 0); DIP : in std_logic_vector(7 downto 0); select_display : out STD_LOGIC_VECTOR (3 downto 0); Segments : out STD_LOGIC_VECTOR (7 downto 0); divide_by_zero : out std_logic ); end TopLevelModule; architecture Behavioral of TopLevelModule is component MyDivider Port ( clk : in std_logic; rst : in std_logic; Divident : in std_logic_vector(15 downto 0); Divisor : in std_logic_vector(15 downto 0); Quotient : out std_logic_vector(15 downto 0); ResRem : out std_logic_vector(15 downto 0); divide_by_zero : out std_logic ); end component; component Encoder4_7 Port ( BCD : in STD_LOGIC_VECTOR (3 downto 0); Segments : out STD_LOGIC_VECTOR (7 downto 1)); end component; type state is (a1, a2, a3); signal FSMstate, FSMnext_state : state; signal WhichDisplay : std_logic_vector(1 downto 0); signal div : std_logic_vector(22 downto 0) := (others => '0'); signal BCD : std_logic_vector(3 downto 0); signal Q : std_logic_vector(15 downto 0); signal R : std_logic_vector(15 downto 0); Entidade - Interface NET "clk" TNM_NET = "clk"; TIMESPEC "TS_clk" = PERIOD "clk" 50 MHz HIGH 50 %; NET "clk" LOC = "B8"; NET "Segments<0>" LOC = "C17"; # SEGMENTs NET "Segments<1>" LOC = "L18"; NET "Segments<2>" LOC = "F18"; NET "Segments<3>" LOC = "D17"; NET "Segments<4>" LOC = "D16"; NET "Segments<5>" LOC = "G14"; NET "Segments<6>" LOC = "J17"; NET "Segments<7>" LOC = "H14"; NET "select_display<0>" LOC = "F17"; #DISPLAYs NET "select_display<1>" LOC = "H17"; NET "select_display<2>" LOC = "C18"; NET "select_display<3>" LOC = "F15"; NET "DIP<7>" LOC = "R17"; NET "DIP<6>" LOC = "N17"; NET "DIP<5>" LOC = "L13"; NET "DIP<4>" LOC = "L14"; NET "DIP<3>" LOC = "K17"; # DIPs NET "DIP<2>" LOC = "K18"; NET "DIP<1>" LOC = "H18"; NET "DIP<0>" LOC = "G18"; NET "Buttons<3>" LOC = "H13"; NET "Buttons<2>" LOC = "E18"; NET "Buttons<1>" LOC = "D18"; NET "Buttons<0>" LOC = "B18"; # Button 0 NET "divide_by_zero" LOC = "J14"; arquitectura – implementação componentes tipos sinais Declarações funcionalidade

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Page 1: Library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity TopLevelModule is Port ( clk : in STD_LOGIC;

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity TopLevelModule is Port ( clk : in STD_LOGIC; Buttons : in std_logic_vector(3 downto 0); DIP : in std_logic_vector(7 downto 0); select_display : out STD_LOGIC_VECTOR (3 downto 0); Segments : out STD_LOGIC_VECTOR (7 downto 0); divide_by_zero : out std_logic );end TopLevelModule;

architecture Behavioral of TopLevelModule is

component MyDividerPort ( clk : in std_logic; rst : in std_logic; Divident : in std_logic_vector(15 downto 0); Divisor : in std_logic_vector(15 downto 0); Quotient : out std_logic_vector(15 downto 0); ResRem : out std_logic_vector(15 downto 0); divide_by_zero : out std_logic );end component;

component Encoder4_7 Port ( BCD : in STD_LOGIC_VECTOR (3 downto 0); Segments : out STD_LOGIC_VECTOR (7 downto 1));end component;

type state is (a1, a2, a3);

signal FSMstate, FSMnext_state : state;

signal WhichDisplay : std_logic_vector(1 downto 0);signal div : std_logic_vector(22 downto 0) := (others => '0');

signal BCD : std_logic_vector(3 downto 0);

signal Q : std_logic_vector(15 downto 0);signal R : std_logic_vector(15 downto 0);signal convert_me : std_logic_vector(7 downto 0);

signal DIP_Divident : std_logic_vector(15 downto 0);signal DIP_Divisor : std_logic_vector(15 downto 0);

signal reset, rst : std_logic;

signal ready, converted : std_logic;signal BCD2, BCD1, BCD0 : STD_LOGIC_VECTOR (3 downto 0);

begin

Segments(0) <= '1'; rst <= Buttons(0);

Entidade - Interface

NET "clk" TNM_NET = "clk";TIMESPEC "TS_clk" = PERIOD "clk" 50 MHz HIGH 50 %;

NET "clk" LOC = "B8";

NET "Segments<0>" LOC = "C17"; # SEGMENTsNET "Segments<1>" LOC = "L18";

NET "Segments<2>" LOC = "F18";NET "Segments<3>" LOC = "D17";NET "Segments<4>" LOC = "D16";NET "Segments<5>" LOC = "G14";NET "Segments<6>" LOC = "J17";NET "Segments<7>" LOC = "H14";

NET "select_display<0>" LOC = "F17"; #DISPLAYsNET "select_display<1>" LOC = "H17";NET "select_display<2>" LOC = "C18";NET "select_display<3>" LOC = "F15";

NET "DIP<7>" LOC = "R17";NET "DIP<6>" LOC = "N17";NET "DIP<5>" LOC = "L13";NET "DIP<4>" LOC = "L14";NET "DIP<3>" LOC = "K17"; # DIPsNET "DIP<2>" LOC = "K18";NET "DIP<1>" LOC = "H18";NET "DIP<0>" LOC = "G18";

NET "Buttons<3>" LOC = "H13";NET "Buttons<2>" LOC = "E18";NET "Buttons<1>" LOC = "D18";NET "Buttons<0>" LOC = "B18"; # Button 0

NET "divide_by_zero" LOC = "J14";

arquitectura – implementação

componentes

tipos

sinais

Dec

lara

ções

funcionalidade

Page 2: Library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity TopLevelModule is Port ( clk : in STD_LOGIC;

Divider : MyDivider port map (clk, Buttons(0),DIP_Divident,DIP_Divisor,Q,R,divide_by_zero);Encoder : Encoder4_7 port map (BCD,Segments(7 downto 1));Converter : entity BinToBCD port map ( clk , reset , '1' , ready, converted, convert_me, BCD2, BCD1, BCD0 );

process(clk,rst)begin if rst = '1' then FSMstate <= a1; elsif rising_edge(clk) then FSMstate <= FSMnext_state; end if;end process;

process(clk)begin if rising_edge(clk) then case FSMstate is when a1 => reset <= '0'; case Buttons is when "0010" => DIP_Divident <= "00000000" & DIP; FSMnext_state <= a2; convert_me <= DIP; when "0100" => DIP_Divisor(15 downto 8) <= DIP; convert_me <= DIP;

DIP_Divisor(7 downto 0) <= (others => '0'); FSMnext_state <= a2; when "0000" => FSMnext_state <= a2; convert_me <= Q(7 downto 0); when "1000" => FSMnext_state <= a2; convert_me <= R(7 downto 0); when others => FSMnext_state <= a1; end case; when a2 => FSMnext_state <= a3; reset <= '1'; when a3 => reset <= '0'; if converted = '1' then FSMnext_state <= a1;

else FSMnext_state <= a3; end if; when others => null; end case; else null; end if;end process;

div<= div + 1 when rising_edge(clk); WhichDisplay <= div(16 downto 15);

process(WhichDisplay) begin if WhichDisplay ="00" then select_display <= "1110"; elsif WhichDisplay ="01" then select_display <= "1101"; elsif WhichDisplay ="10" then select_display <= "1011"; else select_display <= "0111"; end if;end process;

process(clk) begin

if rising_edge(clk) then if (WhichDisplay ="11") then BCD <= "0000"; elsif (WhichDisplay ="10") and (converted = '1') then BCD <= BCD2; elsif (WhichDisplay ="01") and (converted = '1') then BCD <= BCD1; else if converted = '1' then BCD <= BCD0; else null; end if; end if;else null; end if;

end process;

end Behavioral;

instâncias (objectos)

Bloc

os e

atr

ibui

ções

conc

orre

ntes

Page 3: Library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity TopLevelModule is Port ( clk : in STD_LOGIC;

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity TopLevelModule is Port ( clk : in STD_LOGIC; Buttons : in std_logic_vector(3 downto 0); DIP : in std_logic_vector(7 downto 0); select_display : out STD_LOGIC_VECTOR (3 downto 0); Segments : out STD_LOGIC_VECTOR (7 downto 0); divide_by_zero : out std_logic );end TopLevelModule;

architecture Behavioral of TopLevelModule is

component MyDividerPort ( clk : in std_logic; rst : in std_logic; Divident : in std_logic_vector(15 downto 0); Divisor : in std_logic_vector(15 downto 0); Quotient : out std_logic_vector(15 downto 0); ResRem : out std_logic_vector(15 downto 0); divide_by_zero : out std_logic );end component;

component Encoder4_7 Port ( BCD : in STD_LOGIC_VECTOR (3 downto 0); Segments : out STD_LOGIC_VECTOR (7 downto 1));end component;

type state is (a1, a2, a3);

signal FSMstate, FSMnext_state : state;

signal WhichDisplay : std_logic_vector(1 downto 0);signal div : std_logic_vector(22 downto 0) := (others => '0');

signal BCD : std_logic_vector(3 downto 0);

signal Q : std_logic_vector(15 downto 0);signal R : std_logic_vector(15 downto 0);signal convert_me : std_logic_vector(7 downto 0);

signal DIP_Divident : std_logic_vector(15 downto 0);signal DIP_Divisor : std_logic_vector(15 downto 0);

signal reset, rst : std_logic;

signal ready, converted : std_logic;signal BCD2, BCD1, BCD0 : STD_LOGIC_VECTOR (3 downto 0);

begin

Segments(0) <= '1'; rst <= Buttons(0);

Declaração de componentes

Page 4: Library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity TopLevelModule is Port ( clk : in STD_LOGIC;

Divider : MyDivider port map (clk, Buttons(0),DIP_Divident,DIP_Divisor,Q,R,divide_by_zero);Encoder : Encoder4_7 port map (BCD,Segments(7 downto 1));Converter : entity BinToBCD port map ( clk , reset , '1' , ready, converted, convert_me, BCD2, BCD1, BCD0 );

process(clk,rst)begin if rst = '1' then FSMstate <= a1; elsif rising_edge(clk) then FSMstate <= FSMnext_state; end if;end process;

process(clk)begin if rising_edge(clk) then case FSMstate is when a1 => reset <= '0'; case Buttons is when "0010" => DIP_Divident <= "00000000" & DIP; FSMnext_state <= a2; convert_me <= DIP; when "0100" => DIP_Divisor(15 downto 8) <= DIP; convert_me <= DIP;

DIP_Divisor(7 downto 0) <= (others => '0'); FSMnext_state <= a2; when "0000" => FSMnext_state <= a2; convert_me <= Q(7 downto 0); when "1000" => FSMnext_state <= a2; convert_me <= R(7 downto 0); when others => FSMnext_state <= a1; end case; when a2 => FSMnext_state <= a3; reset <= '1'; when a3 => reset <= '0'; if converted = '1' then FSMnext_state <= a1;

else FSMnext_state <= a3; end if; when others => null; end case; else null; end if;end process;

div<= div + 1 when rising_edge(clk); WhichDisplay <= div(16 downto 15);

process(WhichDisplay) begin if WhichDisplay ="00" then select_display <= "1110"; elsif WhichDisplay ="01" then select_display <= "1101"; elsif WhichDisplay ="10" then select_display <= "1011"; else select_display <= "0111"; end if;end process;

process(clk) begin

if rising_edge(clk) then if (WhichDisplay ="11") then BCD <= "0000"; elsif (WhichDisplay ="10") and (converted = '1') then BCD <= BCD2; elsif (WhichDisplay ="01") and (converted = '1') then BCD <= BCD1; else if converted = '1' then BCD <= BCD0; else null; end if; end if;else null; end if;

end process;

end Behavioral;

instanciação de blocos físicosem hardware

component MyDividerPort ( clk : in std_logic; rst : in std_logic; Divident : in std_logic_vector(15 downto 0); Divisor : in std_logic_vector(15 downto 0); Quotient : out std_logic_vector(15 downto 0); ResRem : out std_logic_vector(15 downto 0); divide_by_zero : out std_logic );end component;

component Encoder4_7 Port ( BCD : in STD_LOGIC_VECTOR (3 downto 0); Segments : out STD_LOGIC_VECTOR (7 downto 1));end component;

entity TopLevelModule is Port ( clk : in STD_LOGIC; Buttons : in std_logic_vector(3 downto 0); DIP : in std_logic_vector(7 downto 0); select_display : out STD_LOGIC_VECTOR (3 downto 0); Segments : out STD_LOGIC_VECTOR (7 downto 0); divide_by_zero : out std_logic );end TopLevelModule;

architecture Behavioral of TopLevelModule is

signal BCD : std_logic_vector(3 downto 0);

signal Q : std_logic_vector(15 downto 0);signal R : std_logic_vector(15 downto 0);signal convert_me : std_logic_vector(7 downto 0);

signal DIP_Divident : std_logic_vector(15 downto 0);signal DIP_Divisor : std_logic_vector(15 downto 0);

signal reset, rst : std_logic;

signal ready, converted : std_logic;signal BCD2, BCD1, BCD0 : STD_LOGIC_VECTOR (3 downto 0);

Divider

Encoder

clk

rst

Div

iden

tD

ivis

or

Quotient

ResR

em

divi

de_b

y_ze

ro

Page 5: Library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity TopLevelModule is Port ( clk : in STD_LOGIC;

Divider : MyDivider port map (clk, Buttons(0),DIP_Divident,DIP_Divisor,Q,R,divide_by_zero);Encoder : Encoder4_7 port map (BCD,Segments(7 downto 1));Converter : entity BinToBCD port map ( clk , reset , '1' , ready, converted, convert_me, BCD2, BCD1, BCD0 );

process(clk,rst)begin if rst = '1' then FSMstate <= a1; elsif rising_edge(clk) then FSMstate <= FSMnext_state; end if;end process;

process(clk)begin if rising_edge(clk) then case FSMstate is when a1 => reset <= '0'; case Buttons is when "0010" => DIP_Divident <= "00000000" & DIP; FSMnext_state <= a2; convert_me <= DIP; when "0100" => DIP_Divisor(15 downto 8) <= DIP; convert_me <= DIP;

DIP_Divisor(7 downto 0) <= (others => '0'); FSMnext_state <= a2; when "0000" => FSMnext_state <= a2; convert_me <= Q(7 downto 0); when "1000" => FSMnext_state <= a2; convert_me <= R(7 downto 0); when others => FSMnext_state <= a1; end case; when a2 => FSMnext_state <= a3; reset <= '1'; when a3 => reset <= '0'; if converted = '1' then FSMnext_state <= a1;

else FSMnext_state <= a3; end if; when others => null; end case; else null; end if;end process;

div<= div + 1 when rising_edge(clk); WhichDisplay <= div(16 downto 15);

process(WhichDisplay) begin if WhichDisplay ="00" then select_display <= "1110"; elsif WhichDisplay ="01" then select_display <= "1101"; elsif WhichDisplay ="10" then select_display <= "1011"; else select_display <= "0111"; end if;end process;

process(clk) begin

if rising_edge(clk) then if (WhichDisplay ="11") then BCD <= "0000"; elsif (WhichDisplay ="10") and (converted = '1') then BCD <= BCD2; elsif (WhichDisplay ="01") and (converted = '1') then BCD <= BCD1; else if converted = '1' then BCD <= BCD0; else null; end if; end if;else null; end if;

end process;

end Behavioral;

instanciação de blocos físicosem hardware

component MyDividerPort ( clk : in std_logic; rst : in std_logic; Divident : in std_logic_vector(15 downto 0); Divisor : in std_logic_vector(15 downto 0); Quotient : out std_logic_vector(15 downto 0); ResRem : out std_logic_vector(15 downto 0); divide_by_zero : out std_logic );end component;

component Encoder4_7 Port ( BCD : in STD_LOGIC_VECTOR (3 downto 0); Segments : out STD_LOGIC_VECTOR (7 downto 1));end component;

entity TopLevelModule is Port ( clk : in STD_LOGIC; Buttons : in std_logic_vector(3 downto 0); DIP : in std_logic_vector(7 downto 0); select_display : out STD_LOGIC_VECTOR (3 downto 0); Segments : out STD_LOGIC_VECTOR (7 downto 0); divide_by_zero : out std_logic );end TopLevelModule;

architecture Behavioral of TopLevelModule is

signal BCD : std_logic_vector(3 downto 0);

signal Q : std_logic_vector(15 downto 0);signal R : std_logic_vector(15 downto 0);signal convert_me : std_logic_vector(7 downto 0);

signal DIP_Divident : std_logic_vector(15 downto 0);signal DIP_Divisor : std_logic_vector(15 downto 0);

signal reset, rst : std_logic;

signal ready, converted : std_logic;signal BCD2, BCD1, BCD0 : STD_LOGIC_VECTOR (3 downto 0);

Divider

Encoder

BCDSegments

Page 6: Library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity TopLevelModule is Port ( clk : in STD_LOGIC;

process(clk,rst)begin if rst = '1' then FSMstate <= a1; elsif rising_edge(clk) then FSMstate <= FSMnext_state; end if;end process;

process(clk)begin if rising_edge(clk) then case FSMstate is when a1 => reset <= '0'; case Buttons is when "0010" => DIP_Divident <= "00000000" & DIP; FSMnext_state <= a2; convert_me <= DIP; when "0100" => DIP_Divisor(15 downto 8) <= DIP; convert_me <= DIP;

DIP_Divisor(7 downto 0) <= (others => '0'); FSMnext_state <= a2; when "0000" => FSMnext_state <= a2; convert_me <= Q(7 downto 0); when "1000" => FSMnext_state <= a2; convert_me <= R(7 downto 0); when others => FSMnext_state <= a1; end case; when a2 => FSMnext_state <= a3; reset <= '1'; when a3 => reset <= '0'; if converted = '1' then FSMnext_state <= a1;

else FSMnext_state <= a3; end if; when others => null; end case; else null; end if;end process;

Divider : MyDivider port map (clk, Buttons(0),DIP_Divident,DIP_Divisor,Q,R,divide_by_zero);Encoder : Encoder4_7 port map (BCD,Segments(7 downto 1));Converter : entity BinToBCD port map ( clk , reset , '1' , ready, converted, convert_me, BCD2, BCD1, BCD0 );

div<= div + 1 when rising_edge(clk); WhichDisplay <= div(16 downto 15);

process(WhichDisplay) begin if WhichDisplay ="00" then select_display <= "1110"; elsif WhichDisplay ="01" then select_display <= "1101"; elsif WhichDisplay ="10" then select_display <= "1011"; else select_display <= "0111"; end if;end process;

process(clk) begin

if rising_edge(clk) then if (WhichDisplay ="11") then BCD <= "0000"; elsif (WhichDisplay ="10") and (converted = '1') then BCD <= BCD2; elsif (WhichDisplay ="01") and (converted = '1') then BCD <= BCD1; else if converted = '1' then BCD <= BCD0; else null; end if; end if;else null; end if;

end process;

end Behavioral;

Máquina de estados finitosque partilha acesso aobloco “binary – BCD”

Page 7: Library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity TopLevelModule is Port ( clk : in STD_LOGIC;

process(clk,rst)begin if rst = '1' then FSMstate <= a1; elsif rising_edge(clk) then FSMstate <= FSMnext_state; end if;end process;

process(clk)begin if rising_edge(clk) then case FSMstate is when a1 => reset <= '0'; case Buttons is when "0010" => DIP_Divident <= "00000000" & DIP; FSMnext_state <= a2; convert_me <= DIP; when "0100" => DIP_Divisor(15 downto 8) <= DIP; convert_me <= DIP;

DIP_Divisor(7 downto 0) <= (others => '0'); FSMnext_state <= a2; when "0000" => FSMnext_state <= a2; convert_me <= Q(7 downto 0); when "1000" => FSMnext_state <= a2; convert_me <= R(7 downto 0); when others => FSMnext_state <= a1; end case; when a2 => FSMnext_state <= a3; reset <= '1'; when a3 => reset <= '0'; if converted = '1' then FSMnext_state <= a1;

else FSMnext_state <= a3; end if; when others => null; end case; else null; end if;end process;

Page 8: Library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity TopLevelModule is Port ( clk : in STD_LOGIC;

process(clk,rst)begin if rst = '1' then FSMstate <= a1; elsif rising_edge(clk) then FSMstate <= FSMnext_state; end if;end process;

process(clk)begin if rising_edge(clk) then case FSMstate is when a1 => reset <= '0'; case Buttons is when "0010" => DIP_Divident <= "00000000" & DIP; FSMnext_state <= a2; convert_me <= DIP; when "0100" => DIP_Divisor(15 downto 8) <= DIP; convert_me <= DIP;

DIP_Divisor(7 downto 0) <= (others => '0'); FSMnext_state <= a2; when "0000" => FSMnext_state <= a2; convert_me <= Q(7 downto 0); when "1000" => FSMnext_state <= a2; convert_me <= R(7 downto 0); when others => FSMnext_state <= a1; end case; when a2 => FSMnext_state <= a3; reset <= '1'; when a3 => reset <= '0'; if converted = '1' then FSMnext_state <= a1;

else FSMnext_state <= a3; end if; when others => null; end case; else null; end if;end process;

Divider : MyDivider port map (clk, Buttons(0),DIP_Divident,DIP_Divisor,Q,R,divide_by_zero);Encoder : Encoder4_7 port map (BCD,Segments(7 downto 1));Converter : entity BinToBCD port map ( clk , reset , '1' , ready, converted, convert_me, BCD2, BCD1, BCD0 );

div<= div + 1 when rising_edge(clk); WhichDisplay <= div(16 downto 15);

process(WhichDisplay) begin if WhichDisplay ="00" then select_display <= "1110"; elsif WhichDisplay ="01" then select_display <= "1101"; elsif WhichDisplay ="10" then select_display <= "1011"; else select_display <= "0111"; end if;end process;

process(clk) begin

if rising_edge(clk) then if (WhichDisplay ="11") then BCD <= "0000"; elsif (WhichDisplay ="10") and (converted = '1') then BCD <= BCD2; elsif (WhichDisplay ="01") and (converted = '1') then BCD <= BCD1; else if converted = '1' then BCD <= BCD0; else null; end if; end if;else null; end if;

end process;

end Behavioral;

Controlo dos displays

Page 9: Library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity TopLevelModule is Port ( clk : in STD_LOGIC;

div<= div + 1 when rising_edge(clk); WhichDisplay <= div(16 downto 15);

process(WhichDisplay) begin if WhichDisplay ="00" then select_display <= "1110"; elsif WhichDisplay ="01" then select_display <= "1101"; elsif WhichDisplay ="10" then select_display <= "1011"; else select_display <= "0111"; end if;end process;

process(clk) begin

if rising_edge(clk) then if (WhichDisplay ="11") then BCD <= "0000"; elsif (WhichDisplay ="10") and (converted = '1') then BCD <= BCD2; elsif (WhichDisplay ="01") and (converted = '1') then BCD <= BCD1; else if converted = '1' then BCD <= BCD0; else null; end if; end if;else null; end if;

end process;

end Behavioral;

Page 10: Library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity TopLevelModule is Port ( clk : in STD_LOGIC;

entity MyDivider isPort ( clk : in std_logic;

rst : in std_logic; Divident : in std_logic_vector(15 downto 0); Divisor : in std_logic_vector(15 downto 0); Quotient : out std_logic_vector(15 downto 0); ResRem : out std_logic_vector(15 downto 0); divide_by_zero : out std_logic );

end MyDivider;

architecture Behavioral of MyDivider istype state_type is (a0,a1,a2,a3,a4,a5); signal FSMstate, FSMnext_state : state_type;signal local_quotient : std_logic_vector(15 downto 0);signal local_divisor : std_logic_vector(15 downto 0);signal error : std_logic;

begindivide_by_zero <= error;error <= '1' when Divisor = "0000000000000000" else '0';

process(clk,rst)begin if rst = '1' then FSMstate <= a0; elsif rising_edge(clk) then FSMstate <= FSMnext_state; end if;end process;

process(clk,rst)variable remainder : std_logic_vector(15 downto 0);variable index : integer range 0 to 9;begin if rst = '1' then local_quotient <= (others => '0'); local_divisor <= Divisor;

remainder := Divident; index := 0; elsif falling_edge(clk) then case FSMstate is

when a0 => FSMnext_state <= a1; local_quotient <= (others => '0'); local_divisor <= Divisor; remainder := Divident; index := 0;when a1 => if local_divisor > remainder then FSMnext_state <= a2; else FSMnext_state <= a3; end if;when a2 => FSMnext_state <= a4; local_quotient <= local_quotient(14 downto 0) & '0';when a3 => FSMnext_state <= a4; remainder := remainder-local_divisor; local_quotient <= local_quotient(14 downto 0) & '1';when a4 => local_divisor <= '0' & local_divisor(15 downto 1); index := index+1;

if (index = 9) then FSMnext_state <= a5; else FSMnext_state <= a1;end if;

when a5 => FSMnext_state <= a0; if error = '0' then Quotient <= local_quotient; ResRem <= remainder;else Quotient <= (others => '0');

ResRem <= (others => '0');end if;

when others => null; end case; else null; end if;end process;

end Behavioral;

Page 11: Library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity TopLevelModule is Port ( clk : in STD_LOGIC;

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Encoder4_7 is Port ( BCD : in STD_LOGIC_VECTOR (3 downto 0); Segments : out STD_LOGIC_VECTOR (7 downto 1));end Encoder4_7;

architecture Behavioral of Encoder4_7 isbeginSegments <= "1000000" when BCD = "0000" else

"1111001" when BCD = "0001" else"0100100" when BCD = "0010" else"0110000" when BCD = "0011" else"0011001" when BCD = "0100" else"0010010" when BCD = "0101" else"0000010" when BCD = "0110" else"1111000" when BCD = "0111" else"0000000" when BCD = "1000" else"0010000" when BCD = "1001" else"1111111";

end Behavioral;

Pode aparecer erro seficheiro UCF não corresponder

a esta codificação

NET "Segments<0>" LOC = "C17";NET "Segments<1>" LOC = "L18";NET "Segments<2>" LOC = "F18";NET "Segments<3>" LOC = "D17";NET "Segments<4>" LOC = "D16";NET "Segments<5>" LOC = "G14";NET "Segments<6>" LOC = "J17";NET "Segments<7>" LOC = "H14";

Page 12: Library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity TopLevelModule is Port ( clk : in STD_LOGIC;

constant convert_to_segments : display_ROM :=("00000011","10011111","00100101","00001101","10011001","01001001","01000001","00011111", "00000001","00001001","00010000","00000000","01100010","00000010","01100000","01110000");

NET "segments<7>" LOC = "L18";NET "segments<6>" LOC = "F18";NET "segments<5>" LOC = "D17";NET "segments<4>" LOC = "D16";NET "segments<3>" LOC = "G14";NET "segments<2>" LOC = "J17";NET "segments<1>" LOC = "H14";NET "segments<0>" LOC = "C17";

Page 13: Library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity TopLevelModule is Port ( clk : in STD_LOGIC;

entity BinToBCD is Port ( clk : in STD_LOGIC; reset : in STD_LOGIC; start : in std_logic; ready, converted : out STD_LOGIC; binary : in STD_LOGIC_VECTOR (7 downto 0); BCD2 : out STD_LOGIC_VECTOR (3 downto 0); BCD1 : out STD_LOGIC_VECTOR (3 downto 0); BCD0 : out STD_LOGIC_VECTOR (3 downto 0));end BinToBCD;

architecture Behavioral of BinToBCD istype state is (idle, op, done);signal c_s, n_s : state;signal tempC_V, tempN_V : STD_LOGIC_VECTOR (7 downto 0);signal BCD2_c, BCD1_c, BCD0_c, BCD2_n, BCD1_n, BCD0_n : unsigned(3 downto 0);signal BCD2_tmp, BCD1_tmp, BCD0_tmp : unsigned(3 downto 0); signal int_rg_c, int_rg_n : STD_LOGIC_VECTOR (7 downto 0); signal index_c, index_n : unsigned(3 downto 0); begin

Page 14: Library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity TopLevelModule is Port ( clk : in STD_LOGIC;

process(clk,reset)begin

if reset = '1' thenc_s <= idle;BCD2_c <= (others => '0'); BCD1_c <= (others => '0');BCD0_c <= (others => '0');

elsif rising_edge(clk) thenc_s <= n_s;BCD2_c <= BCD2_n;BCD1_c <= BCD1_n;BCD0_c <= BCD0_n;index_c <= index_n;int_rg_c <= int_rg_n;

end if;end process;

Page 15: Library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity TopLevelModule is Port ( clk : in STD_LOGIC;

process (c_s, BCD2_c, BCD1_c, BCD0_c, BCD2_tmp, BCD1_tmp, BCD0_tmp, start, binary, int_rg_c, index_c)begin

n_s <= c_s; BCD2_n <= BCD2_c; BCD1_n <= BCD1_c; BCD0_n <= BCD0_c;index_n <= index_c; int_rg_n <= int_rg_c;case c_s is when idle => converted <= '0';

if start = '1' then n_s <= op; ready <= '0'; BCD2_n <= (others => '0'); BCD1_n <= (others => '0'); BCD0_n <= (others => '0'); int_rg_n <= binary; index_n <= "1000";end if;

when op =>int_rg_n <= int_rg_c(6 downto 0) & '0';BCD0_n <= BCD0_tmp(2 downto 0) & int_rg_c(7);BCD1_n <= BCD1_tmp(2 downto 0) & BCD0_tmp(3);BCD2_n <= BCD2_tmp(2 downto 0) & BCD1_tmp(3);index_n <= index_c - 1;if (index_n = 0) then n_s <= done;end if;

when done =>n_s <= done;converted <= '1';BCD0 <= std_logic_vector(BCD0_c);BCD1 <= std_logic_vector(BCD1_c);BCD2 <= std_logic_vector(BCD2_c);ready <= '1';

end case;end process;

BCD0_tmp <= BCD0_c + 3 when BCD0_c > 4 else BCD0_c;BCD1_tmp <= BCD1_c + 3 when BCD1_c > 4 else BCD1_c;BCD2_tmp <= BCD2_c + 3 when BCD2_c > 4 else BCD2_c;

end Behavioral;

Page 16: Library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity TopLevelModule is Port ( clk : in STD_LOGIC;

architecture Behavioral of BinToBCD istype state is (idle, op, done);signal c_s, n_s : state;signal BCD2_i, BCD1_i, BCD0_i : unsigned(3 downto 0);signal BCD2_tmp, BCD1_tmp, BCD0_tmp : unsigned(3 downto 0); signal int_rg_n : STD_LOGIC_VECTOR (7 downto 0); signal index_n : unsigned(2 downto 0); begin

process(clk,reset)begin

if reset = '1' thenc_s <= idle;

elsif rising_edge(clk) thenc_s <= n_s;

end if;end process;

Page 17: Library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity TopLevelModule is Port ( clk : in STD_LOGIC;

process (clk)begin if falling_edge(clk) then

case c_s is when idle => converted <= '0';

if start = '1' then n_s <= op; ready <= '0'; BCD2_i <= (others => '0'); BCD1_i <= (others => '0'); BCD0_i <= (others => '0'); int_rg_n <= binary; index_n <= "111";else n_s <= idle;end if;

when op => index_n <= index_n - 1;int_rg_n <= int_rg_n(6 downto 0) & '0';BCD0_i <= BCD0_tmp(2 downto 0) & int_rg_n(7);BCD1_i <= BCD1_tmp(2 downto 0) & BCD0_tmp(3);BCD2_i <= BCD2_tmp(2 downto 0) & BCD1_tmp(3);if (index_n = 0) then n_s <= done; end if;

when done => n_s <= done; converted <= '1'; BCD0 <= std_logic_vector(BCD0_i);BCD1 <= std_logic_vector(BCD1_i); BCD2 <= std_logic_vector(BCD2_i);ready <= '1';

end case; end if;end process;BCD0_tmp <= BCD0_i + 3 when BCD0_i > 4 else BCD0_i;BCD1_tmp <= BCD1_i + 3 when BCD1_i > 4 else BCD1_i;BCD2_tmp <= BCD2_i + 3 when BCD2_i > 4 else BCD2_i;

Page 18: Library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity TopLevelModule is Port ( clk : in STD_LOGIC;

O código seguinte permite ler 3 operandos sequencialmente, utilizando:1.Interruptores 5 downto 0 e Botão 0 para o primeiro operando – Op1;2.Interruptores 5 downto 0 e Botão 1 para o segundo operando – Op2;3.Interruptores 5 downto 0 e Botão 2 para o terceiro operando – Op3;

O resultado vai depender dos valores dos interruptores 7, 6:1.Interruptores 7,6 = 00 e Botão 3 – Op1+Op2+Op3;2.Interruptores 7,6 = 01 e Botão 3 – Op1/Op2;3.Interruptores 7,6 = 10 e Botão 3 – resto de divisão Op1/Op2;

Page 19: Library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity TopLevelModule is Port ( clk : in STD_LOGIC;

process(clk)begin if rising_edge(clk) then case FSMstate is when a1 => reset <= '0';

case Buttons is when "0001" => Op1 <= DIP(5 downto 0); DIP_Divident <= "0000000000" & DIP(5 downto 0); FSMnext_state <= a2; convert_me <= "00"&DIP(5 downto 0); when "0010" => Op2 <= DIP(5 downto 0); DIP_Divisor(15 downto 8) <= "00"&DIP(5 downto 0);

DIP_Divisor(7 downto 0) <= (others => '0'); convert_me <= "00"&DIP(5 downto 0); FSMnext_state <= a2;

when "0100" => Op3 <= DIP(5 downto 0); convert_me <= "00"&DIP(5 downto 0); FSMnext_state <= a2;

when "1000" => case DIP(7 downto 6) is

when "00" => convert_me <= ("00"&Op1)+("00"&Op2)+("00"&Op3);when "01" => convert_me <= Q(7 downto 0);when "10" => convert_me <= R(7 downto 0);when others => null;

end case;FSMnext_state <= a2;

when others => FSMnext_state <= a1;end case;

when a2 => FSMnext_state <= a3; reset <= '1'; when a3 => reset <= '0';

if converted = '1' then FSMnext_state <= a1; else FSMnext_state <= a3; end if; when others => null; end case; else null; end if;end process;


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