NextgenerationcomputingusingFPGA’s

Asmallwhat,why,how,introintoFieldProgrammableGate

Arrays

ByRolfHuismanRolf.Huisman@infosupport.com

@rlrhuisman

FPGA?A field-programmablegatearray (FPGA)isanintegratedcircuitdesignedtobeconfiguredbyacustomeroradesigneraftermanufacturing– hence"field-programmable”

Source:Wikipedia

Simplified:YoucancreateyourownprocessorWhyshouldonecare?

InnovationKeynoteIgnite2016

Title document 307-11-16

“But we not stopping there. We are now, taking those; neural nets, deep neural nets, convolution nets and asking ourselves; What if we can run them not just on cpu’s or gpu’s, what if we can run them on silicon ?”Satya Nadella

Source: Innovation Keynote Ignite 2016

InnovationKeynoteIgnite2016

Dough Burger

Source: Innovation Keynote Ignite 2016

FPGAarepowerfull24-core2.4Haswell <10Cpu cores+4FPGA’s

Source: Innovation Keynote Ignite 2016

LasttwoyearsatRolf’satticFPGAmeetsraspberrypi

PersonalPOCPensionCalculation50ktransactionspersecond

7x300Watts 1,89Watts+3,34Watts2100Watts 5,23Watts

Titledocument 707-11-16

WhatamIseeing?

RaspberryPI

MicroService

WhatamIseeing?

RaspberryPI FPGAShield

MicroService RAM

SPISerial Peripheral Interface

WhatamIseeing?

RaspberryPI FPGAShield

MicroService RAM

FPGAChip

MyProcessor

SPISerial Peripheral Interface

AndGate

A B Out0 0 01 0 00 1 01 1 1

OutANDAB

OrGate

A B Out0 0 01 0 10 1 11 1 1OutORA

B

ANDAB

(Multiplexer)MUX

Choosingbetweengates

ORAB

Out

ANDAB

S

S A B Out0 0 0 00 1 0 00 0 1 00 1 1 11 0 0 01 1 0 11 0 1 11 1 1 1

AND

OR

(Multiplexer)MUX

MuxGate

ORAB

ANDAB

S

Out

(Multiplexer)MUX

MuxGate

ORAB

ANDAB

S

Out

0

(Multiplexer)MUX

MuxGate

ORAB

ANDAB

S

Out

1

(Multiplexer)MUX

MuxGate

ORAB

ANDAB

S

OutThe selectors are part of the “Bitstream”This Bitstream is the configuration you write to you’re FPGA

That’s how you are configuring/building your own dedicated processor

RealityisabitmorecomplexInreality:GatesareLookUpTables(LUT)with5or6inputs,and2outputsFlip-Flops(Memorycells)RoutingFabric(LotofMultiplexerstoroutesignals)IOpinsconnectingtooutsideworld

AndalotI’llignorefornowSignalTimingsHeatingwithintheFPGAchipPowerconsumption…

Specifying/ProgrammingDirect– VHDL– Verilog– GateDiagrams

Indirect:– (HLS)C– Open-CL

VHDL of Blinking light (“Hello World”)

ConstraintsSpecifywhichpinsareconnected

SpecifyPackages

BGAQFP144

Synthesis,Mapping,Placing,RoutingAutomatic,Manual,orBoth

Specify

Can take weeks if very complex

GeneratingBitstream andupload

DebuggingHardwaresimulationsJTAGinterfaceOscilloscope

ConclusionFPGA’sisaveryinterestingtechnology– Powerful– EfficientFPGA’sisalsoadifficulttechnology– Steeplearningcurve– Synthesis,mapping,androutingcantakeages– Highlyparallelandphysicalinterferencemakesforfundebuggingsessions

– Physicalbehavior(Heatingofchip,chirp)Useabstractionslikeopen-clifyou'reableto

Titledocument 2407-11-16

Thanks

Spartan-6LX9~17$

715CLB’s9.152LUT6’S102IOPins*

*The XC6SLX9-2TQG144C only has 94 pins bonded

IncomparisontotheIgnitedemoStratix VD5,dependingontheversion:– Between300kand952kLUTS(Comparedto9kSpartan6-LX9)

– Between1K$and5K$(Comparedto17$Spartan6-LX9)

AndhehasfourofthemJ