limitations of digital computation william trapanese richard wong

Limitations of Digital Limitations of Digital ComputationComputation

William TrapaneseWilliam Trapanese

Richard WongRichard Wong

Fundamental LimitFundamental Limit

Irreversible Logic DeviceIrreversible Logic Device First developed by John von Neumann over 50 years First developed by John von Neumann over 50 years

ago and discussed in depth by Rolf Landauer in 1961ago and discussed in depth by Rolf Landauer in 1961Entropy caused by changing states defined by Boltzmann Entropy caused by changing states defined by Boltzmann Principle that:Principle that:

S = kS = kBB ln ln ΩΩ

Where S = entropy and Where S = entropy and ΩΩ is number of states is number of statesThe energy required to overcome this entropy is:The energy required to overcome this entropy is:

ΔΔE = T E = T ΔΔSSE = T kE = T kBB ln ln ΩΩ

Since digital logic is binary (Since digital logic is binary (ΩΩ = 2) and the energy needed to = 2) and the energy needed to change a bit is:change a bit is:

E = kE = kBBT ln 2T ln 2


From this equation known as the von From this equation known as the von Neumann – Landauer expression Neumann – Landauer expression limits of other properties ariselimits of other properties arise

EEbitbit ≥ k ≥ kBBT ln 2 = .017 eV.T ln 2 = .017 eV.

Use the uncertainity relations to Use the uncertainity relations to determine the minimum limits of the determine the minimum limits of the size, density, power and speed of a size, density, power and speed of a

digital switching device?digital switching device?


ΔΔx x ΔΔp ≥ ħp ≥ ħΔΔE E ΔΔt ≥ ħt ≥ ħ

xxminmin = ħ / = ħ / ΔΔp = ħ / (2 mp = ħ / (2 mee E Ebitbit)).5.5 = = 1.5nm1.5nmWhere xWhere xminmin is the minimum size of a switch is the minimum size of a switch

nnmaxmax = 1 / x = 1 / x 2 2 = = 4.7 x 104.7 x 1013 13 devices / cmdevices / cm22

Where nWhere nmaxmax is the maximum density of switches is the maximum density of switches

ttminmin = ħ / = ħ / ΔΔE = E = .04 ps.04 ps Where tWhere tminmin is the minimum switching time is the minimum switching time

SpeedSpeed = 1 / t = 1 / tminmin = 1/.04 = = 1/.04 = 2.5 x 102.5 x 101313 hz hz

PP = ( = (nnmaxmax E Ebitbit) / t) / tminmin = = 3.7 x 103.7 x 1066 W / cm W / cm22


The Fundamental Limit Depends on using The Fundamental Limit Depends on using mobile electron carriers to change states and mobile electron carriers to change states and irreversible logic.irreversible logic. Possible FixesPossible Fixes

Using Reversible Computing LogicUsing Reversible Computing Logic Only represents minor gains of about 1-2 orders of magnitudeOnly represents minor gains of about 1-2 orders of magnitude

Using New Logic Alternatives Using New Logic Alternatives SpintronicsSpintronics Phase Chase Logic DevicesPhase Chase Logic Devices Interference devicesInterference devices Optical SwitchesOptical Switches

Silicon TransistorsSilicon TransistorsThe last 40 years of silicon transistor technology has been achieved The last 40 years of silicon transistor technology has been achieved with more or less the same techniqueswith more or less the same techniques

Metal-Oxide Semiconductor (MOS) TransistorsMetal-Oxide Semiconductor (MOS) Transistors

Complimentary MOS (CMOS) circuits to design logic gatesComplimentary MOS (CMOS) circuits to design logic gates

Materials: Si, SiO2, Al, Si3N4, TiSi2, Tin, WMaterials: Si, SiO2, Al, Si3N4, TiSi2, Tin, W

Moore’s LawMoore’s Law

A new generation of technology is produced A new generation of technology is produced every 2-3 yearsevery 2-3 years

Each new generation has:Each new generation has: Twice the number of transistorsTwice the number of transistors Increased performance by 40%Increased performance by 40% Four times the memory capacityFour times the memory capacity

Hi. Hi.

Moore’s LawMoore’s LawIncreased number of transistors: where does it come from?Increased number of transistors: where does it come from?

Shrinking lithography dimensions (scaling)Shrinking lithography dimensions (scaling) Increase in chip area (cheating!)Increase in chip area (cheating!) ““Cleverness” in designCleverness” in design

With practical limits on chip area and the general unpredictability of With practical limits on chip area and the general unpredictability of “cleverness,” scaling is the most important aspect of Moore’s Law“cleverness,” scaling is the most important aspect of Moore’s Law

It is estimated that current technology will progress for another 10-It is estimated that current technology will progress for another 10-15 years before a new “breakthrough” is required15 years before a new “breakthrough” is required

Limits of ScalingLimits of ScalingPhysical Gate Oxide Physical Gate Oxide ThicknessThickness

Max Silicide/Si Contact Max Silicide/Si Contact ResistivityResistivity

Source/Drain Extension Source/Drain Extension Sheet ResistanceSheet Resistance

S/D Extension Junction S/D Extension Junction DepthDepth

Oxide Gate ThicknessOxide Gate Thickness

Present DayPresent Day SiOSiO22 gate oxide gate oxide Has a low kHas a low k Makes near perfect Makes near perfect

electrical interface with electrical interface with SiSi

Effectively used up to Effectively used up to 1.2nm thickness1.2nm thickness


ProblemsProblems Although most properties of Although most properties of

the device have been the device have been scaled at similar rates the scaled at similar rates the gate voltage has not. To gate voltage has not. To compensate for this, the compensate for this, the electric field across the electric field across the capacitor increases. capacitor increases.

At about 1nm, the At about 1nm, the thickness and large electric thickness and large electric field causes a large field causes a large leakage current do to leakage current do to electron tunnelingelectron tunneling


Possible SolutionsPossible Solutions Strained SiliconStrained Silicon

Used today in 90nm Used today in 90nm technologytechnology

Allows greater mobility in Allows greater mobility in channel thus lowering the channel thus lowering the leakage currentleakage current

High k dielectricHigh k dielectricHigh k allows for larger High k allows for larger thickness while keeping thickness while keeping the same capacitancethe same capacitance

Difficult to apply to silicon Difficult to apply to silicon base without increasing base without increasing scattering in channelscattering in channel

Shallow JunctionsShallow Junctions

In MOSFET technology, In MOSFET technology, the current drive limited the current drive limited by the channel resistanceby the channel resistanceAs MOSFETS get smaller As MOSFETS get smaller parasitic resistances are parasitic resistances are no longer comparatively no longer comparatively smallsmallTo reduce these To reduce these resistances doping is resistances doping is increasedincreasedDoping is only feasible till Doping is only feasible till electrical solubility limits electrical solubility limits are reachedare reached

Minimum Feature Size (nm)

0

50

100

150

200

250

300

1997 1999 2002 2005 2008 2011 2014

Year

Isolated Gate Length (nm)

0

20

40

60

80

100

120

1997 1999 2002 2005 2008 2011 2014

Year

Equivalent Physical Gate

0

1

2

3

4

5

6

1997 1999 2002 2005 2008 2011 2014

Year

Dielectric Constant of DRAM Capacitor

0

200

400

600

800

1000

1200

1400

1600

1997 1999 2002 2005 2008 2011 2014

Year

Wire RestrictionsWire RestrictionsWhile not directly related to silicon technology, wires represent a While not directly related to silicon technology, wires represent a fundamental problem in miniaturization of circuitsfundamental problem in miniaturization of circuits

As transistors continue to shrink, wires and interconnect do not shrink at As transistors continue to shrink, wires and interconnect do not shrink at a similar pacea similar pace

However, more and more wiring is needed to connect the increased However, more and more wiring is needed to connect the increased number of transistorsnumber of transistors

Getting around Wire LimitsGetting around Wire Limits

Use fewer wires!Use fewer wires! Integrated circuits reduces the need for wiringIntegrated circuits reduces the need for wiring

Decreasing width of wiringDecreasing width of wiring

Layering wires on top of each otherLayering wires on top of each other

Problems with Decreasing WidthProblems with Decreasing Width

Increases resistance per unit lengthIncreases resistance per unit length Smaller cross-sectional area means increased resistance per unit lengthSmaller cross-sectional area means increased resistance per unit length Capacitance inversely increased, leading to constant RC timesCapacitance inversely increased, leading to constant RC times As circuit speed increases, this leads to transmission delays limited by As circuit speed increases, this leads to transmission delays limited by

RC times rather than velocity of Electromagnetic wavesRC times rather than velocity of Electromagnetic waves

Problem with Longer WiringProblem with Longer Wiring

Requires layering to separate each traceRequires layering to separate each trace

Leads to higher production costsLeads to higher production costs

Result: Production limits are sometimes restricted by monetary Result: Production limits are sometimes restricted by monetary barriers, not technological limitationsbarriers, not technological limitations

Problems with Current DensityProblems with Current DensityCurrent density increase as cross-sectional area of the wire Current density increase as cross-sectional area of the wire decreasesdecreases

Current density is limited by electromigration, the movement of Current density is limited by electromigration, the movement of atoms by electric currentsatoms by electric currents

Corrected, in part, by copper wiringCorrected, in part, by copper wiring

Open Circuit Failure Short Circuit Failure

Current DensityCurrent DensityA numerical analysis:A numerical analysis:

Electron density of copper

Fermi speed, Ef = 7 eV

Conductivity of copper at 20°C

Mean free path of an electron

Resistance, given diameter 1mm and length 1m

Current density, given 1 volt

Drift velocity

More reasonable: 3A current yields 382 A/m^2 and a drift velocity of 0.00028 m/s

““Wire-Limited Chip” ConceptWire-Limited Chip” ConceptAssumptions: the area needed for wiring dominates the area of the Assumptions: the area needed for wiring dominates the area of the chipchip

Each component has area Each component has area aa

The component separation is The component separation is a^0.5a^0.5

Average length of the wire channels that must provided per Average length of the wire channels that must provided per component is ma^0.5, where m is the length in component pitches component is ma^0.5, where m is the length in component pitches needed to run the wireneeded to run the wire

Minimum distance between wires is WMinimum distance between wires is W

K is the number of layersK is the number of layers

Ka = m (a)^0.5 WKa = m (a)^0.5 W

A = (mW/K)^2A = (mW/K)^2

limitations of digital computation william trapanese richard wong

Documents