Logic Gate Circuity

ELCTEC-131Lecture 2

Noise

Unwanted electrical signals.

Induced by electromagnetic fields by such sources as motors, fluorescent lights, high-frequency circuits, and cosmic rays.

Can cause erroneous operation of a digital circuit.

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Noise Margin

A certain amount of tolerance is built into digital devices to tolerate noise.

Noise margin is required for both LOW and HIGH inputs (See Figure 11.15 in the textbook).

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Noise Margin for 74LS04

HIGH state:

VNH = VOH – VIH = 3.0 V – 2.0 VVNH = 1.0 V.

LOW state:

VNL = VIL – VOL = 0.8 V – 0.5 VVNL = 0.3 V.

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Noise Margin for 74HC00A

HIGH state:

VNH = VOH – VIH = 3.98 V – 3.15 VVNH = 0.63 V.

LOW state:

VNL = VIL – VOL = 1.35 V – 0.26 VVNL = 1.09 V.

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TTL Gates Internal Circuitry Uses the bipolar junction transistor.

The transistors used are in one of two modes: cutoff or saturation.

In cutoff mode, the transistor acts as an open switch.

In saturation, the transistor acts as a closed switch.

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TTL Gates Internal Circuitry

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Bipolar Transistor Characteristics

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Cutoff Active SaturationI C 0

V CE Open cct. >0.8 V 0.2 V - 0.7 VV BE <0.6 V 0.6 V - 0.7 V

BβI= BβI<

v7.0≈

Open-Collector Outputs

A circuit that has LOW-state output circuitry, but no HIGH-state output circuitry.

Requires an external pull-up resistor to enable the output to produce a HIGH-state.

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Advantages of Open-Collector Outputs Allows the outputs of multiple gates to be

directly connected.

◦ – Called wired-AND.

Can produce voltage levels in excess of 5 Volts.

Can drive high-input current devices.

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Open-Collector Outputs

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Open-Collector Applications

Wired-AND – the outputs of logic gates are wired together.

The wired-AND logical equivalent of combining the outputs in an AND function.

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Open-Collector Applications

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Open-Collector Applications

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TTL Inputs

LOW inputs allow current to flow from the gate VCC to the input.

HIGH inputs cause current to flow to the phase splitter transistor.

Open (floating) inputs act as a logic HIGH, but are unstable and vulnerable to noise.

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Totem Pole Outputs

The standard TTL output configuration with a HIGH output and a LOW output transistor, only one of which is active at any time.

A phase splitter transistor controls which transistor is active.

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Totem Pole Outputs

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Advantages of Totem Pole Configuration Changes state faster than open-collector

outputs.

No external components are required.

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Totem Pole Switching Noise

Caused by one output transistor turning off slower than the other turns on.

Briefly shorts VCC to ground.

Prevented with use of decoupling capacitors.

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Decoupling Capacitors

Usually about 0.1 µF placed between VCCand ground on the chips to be decoupled.

Acts as a low-impedance path to ground for high frequency noise.

Usually require one per chip.

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Decoupling Capacitors

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Decoupling Capacitors

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Decoupling Capacitors

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Connecting Totem Pole Outputs

Outputs must never be connected together.

Connecting outputs causes excessively high currents to flow.

Outputs will eventually be damaged.

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Connecting Totem Pole Outputs

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Tristate Outputs

A configuration where there are three possible output states: logic HIGH, logic LOW, and a high-impedance state (Z).

Created with circuitry to cut off both totem pole output transistors.

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Tristate Inverter Truth Table

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G A Y A Y0 0 Hi-Z 0 0 10 1 Hi-Z 0 1 01 0 1 1 0 Hi-Z1 1 0 1 1 Hi-Z

G

Other Basic TTL Gates

NOR gates require an individual transistor for each input.

AND and OR gates are based on NAND and NOR gates and require an extra inverter stage.

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MOSFET Types Depletion-mode.

Enhancement-mode:

◦ n-channel

◦ p-channel

CMOS (complementary) constructed from both n- and p-channel transistors.

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MOSFET Types

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MOSFET BIAS Requirements

Operates in two modes:

Cutoff – acts as a very high impedance between the drain and the source.

Ohmic – equivalent of saturation. Acts like a relatively low resistance between the drain and the source.

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MOSFET BIAS Requirements

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MOSFET BIAS Requirements

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CMOS Inverter

Depends on the biasing of the complementary transistors Q1 and Q2.

Q1 and Q2 are always in opposite states.

When Q1 is ON, Q2 is OFF.

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CMOS Inverter

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CMOS Transmission Gate Behaves like an analog switch.

Conducts in both directions.

Used to enable or inhibit time-varying analog signals.

◦ When CONTROL = 1, conduction occurs

◦ When CONTROL = 0, conduction is inhibited

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CMOS Transmission Gate

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Schottky Family TTL

Uses a Schottky barrier diode to create a Schottky transistor.

Allows transistors to avoid deep saturation and to switch faster.

Uses less power than standard TTL.

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Speed-Power Product

One measure of logic circuit efficiency.

Uses worst-case values of propagation delay and power dissipation per gate.

Expressed in picojoules (pJ).

See Table 11.15 in the textbook.

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CMOS Logic Families Metal-Gate CMOS (rarely used).

High-Speed CMOS.

Advanced High-Speed CMOS.

Low-Voltage CMOS.

See Table 11.16 in the textbook.

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