logic synthesis of concurrent controller specificationspmat/research/phd.pdf · logic synthesis of...

LOGIC SYNTHESIS OF

CONCURRENT CONTROLLER

SPECIFICATIONS

PAVLOS M. MATTHEAKIS

SUPERVISOR: CHRISTOS P. SOTIRIOU

1

OVERVIEW

• Motivation

• Background

• MSFSMs

• Synthesis

• Verification

• Optimization

• Results

• Conclusions and Future Work

2

STATE EXPLOSION

Concurrent

Specification

State Space

• Logic Synthesis requires specification’s complete state space

• State space’s size is exponential compared to the specification

Implementation

3

SPECIFICATION AND

STATE CONFLUENCE

T1

T2 T3

T2

T2

T3

T3

T1

T1

T2 T3

T2

T2

T3

T3

T1

T2 T3

…

Concurrent

Specification

Concurrent

Specification

+ (T2,P4)

State Space = 4 states

Infinite State Space

• Changes at the Concurrent Specification

Level Have Unpredictable Results at the State

Space

P1 P2 P1 P2

4

DECOMPOSABILITY

Component #2

P=6

State Space=6

Component #1

P=9

State Space=27

• Concurrent Specification Decomposition is Unpredictable as it is

Evaluated with Specification Level Metrics, e.g. number of places.

Complete Specification

P=15

State Space=33

5

IMPORTANCE

• Logic Synthesis

• HLS – VLSI Programming

• Formal Verification State Explosion

• Complex Synthesis Flows

• Digital Design

Specification and State Space Confluence

• Logic Synthesis

• HLS – VLSI Programming Decomposability

6

OVERVIEW

• Motivation

• Background

• MSFSMs

• Synthesis

• Verification

• Optimization

• Results


7

PTNET OPERATION

8

FSM

PTNet

PTNET OPERATION

9

FSM

PTNet

PTNET OPERATION

10

FSM

PTNet

PTNet Algebra

CONTROL MODELS

EXPRESSABILITY

S0 = S1.b + S2.a

+ S0.(a+b)’

S1 = S0.a + S1.b’

S2 = S0.b + S2.a’

x = S0.a + S1

+ S2.a

Control Model State Space Choice Concurrency Synchronization

Algebra Implicit Implicit Implicit Implicit

FSM Explicit Explicit Implicit Implicit

Inter. FSMs Implicit Explicit Explicit Implicit

PTNet Implicit Explicit Explicit Explicit

FSM Inter. FSMs

11

CONTROL MODELS

IMPLEMENTABILITY TO

CLOCKED LOGIC

PTNets

•This Work

Interacting FSMs

•FSM Composition and Decomposition (VIS)

• Input Don’t Cares and Permissible Behaviors(S1S)

FSMs

•State Minimization (SIS)

•Encoding (NOVA, MUSTANG)

Boolean Logic

•2-Level Exact (Q. McCluskey Method) and Heuristic (Espresso)

•Multilevel Factoring, Extraction, etc. (SIS)

Imp

lem

en

tab

ilit

y

Ab

str

acti

on

12

CONTROL MODELS

IMPLEMENTABILITY TO

SELF-TIMED LOGIC

13

(A,BM)FSM Synthesis1

• Conventional FSM Heuristics

• Exponential Concurrent Specifications

PTNet Synthesis2

• Compact Concurrent Specifications

• Exponential Synthesis Time

Decomposition4

• Lower Synthesis Time

• Infeasible Implementation

• Worst Case Exponential

Structural Synthesis5

• Lower Synthesis Time

• Worst Case Exponential

Direct Mapping3

• Linear Synthesis Time

• Suboptimal Results

1K. Y. Yun and D. L. Dill, ”Automatic synthesis of extended burst-mode circuits”, IEEE TCAD, 1999

2J. Cortadella et al., “Logic Synthesis of Asynchronous Controllers and Interfaces”, Springer-Verlag, 2002.

3D. Sokolov et al., “Direct Mapping of Low-Latency Asynchronous Controllers from STGs”, IEEE TCAD, 2007

4D. Wist et al., “Signal transition graph decomposition: internal communication for speed independent circuit

implementation“, IET Computers & Digital Techniques, 2011

5E. Pastor et al. “Structural Methods for the Synthesis of Speed-Independent Circuits“, IEEE TCAD, 1998

OVERVIEW

• Motivation

• Background

• MSFSMs

• Synthesis

• Verification

• Optimization

• Results


14

MULTIPLE

SYNCHRONIZED FSMS

Novel Model for Concurrent Control Specifications

• Parallel Tasks Described with FSMs

• Synchronization explicitly described

• Transition Barriers, Wait States

• Polynomial Synthesis and Verification Paths

PTNet FSMs MSFSMs

Synthesis

Verification

Polynomial Polynomial

Polynomial Polynomial

15

MSFSMS

SYNCHRONIZATION

PRIMITIVES

Sd/

FSM2

FSM1

Sd

• FSM1 moves from Sw to Swn

if FSM2 is at Sd

Wait State

t1

FSM2 FSM1

• FSM1 and FSM2 move to

their next states when both

t1 and t2 are activated

Transition Barrier

t2

16

MSFSMS EXAMPLE:

4-PHASE LATCH CTRL

E

Ri

Ai

Ro

Ao

I O

L

MSFSMS EXAMPLE:

4-PHASE LATCH CTRL

E

Ri

Ai

Ro

Ao

I O

L

Ri+

L+

Ai+

Ri-

Ai-

Ro+

Ao+

Ro-

Ao- L-

PTNet

18

MSFSMS EXAMPLE:

4-PHASE LATCH CTRL

E

Ri

Ai

Ro

Ao

I O

L

Ri+

L+

Ai+

Ri-

Ai-

Ro+

Ao+

Ro-

Ao- L-

PTNet State Graph (FSM)

19

MSFSMS EXAMPLE:

4-PHASE LATCH CTRL

E

Ri

Ai

Ro

Ao

I O

L

FSMLHS

Ri/

ε/Ai

Ri’/

ε/Ai’

ε/Ro

Ao/

ε/Ro’

Ao’/

ε/L

ε/L’

FSMRHS

FSMLTH

20

MSFSMS EXAMPLE:

4-PHASE LATCH CTRL

E

Ri

Ai

Ro

Ao

I O

L

FSMLHS

Ri/

ε/Ai

Ri’/

ε/Ai’

ε/Ro

Ao/

ε/Ro’

Ao’/

ε/L

ε/L’

FSMRHS

FSMLTH

21

OVERVIEW

• Motivation

• Background

• MSFSMs

• Synthesis

• Verification

• Optimization

• Results


22

OVERVIEW

PTNet Synthesis Flow to Synchronous Circuit

PTNet Decomposition to FSMs

PTNet Decomposition to S-Components

S-Components Transformation to FSMs

FSMs Synchronization

Synchronization Primitives Extraction

Synchronization Integration

23

STEPS (1/4)

a

b c d

x y z

a

b c

x

PTNet SC1

PTNet to S-

Component

Decomposition

S-Component to

FSM Mapping

Synchronization

Primitive

Extraction

Synchronization

Integration

24

STEPS (1/4)

a

b c d

x y z

a

b c

x

SC1 PTNet

a

d

y

SC2

PTNet to S-

Component

Decomposition

S-Component to

FSM Mapping

Synchronization

Primitive

Extraction

Synchronization

Integration

25

STEPS (1/4)

a

b c d

x y z

a

b c

x

SC1 PTNet

a

d

y

SC2

a

d

z

SC3

PTNet to S-

Component

Decomposition

S-Component to

FSM Mapping

Synchronization

Primitive

Extraction

Synchronization

Integration

26

STEPS (1/4)

a

b c d

x y z

a

b c

x

SC1 PTNet

PTNet to S-

Component

Decomposition

S-Component to

FSM Mapping

Synchronization

Primitive

Extraction

Synchronization

Integration

a

d

y

SC2

a

d

z

SC3

SCover

27

STEPS (2/4)

PTNet to S-

Component

Decomposition

S-Component to

FSM Mapping

Synchronization

Primitive

Extraction

Synchronization

Integration

b c

x

SC1

a

FSM1

a/

b/

c/

ε/x

28

STEPS (3/4)

PTNet to S-

Component

Decomposition

S-Component to

FSM Mapping

Synchronization

Primitive

Extraction

Synchronization

Integration

FSM1

a/ b/

c/

ε/x

FSM2

ε/y

a/

d/

a

29

STEPS (4/4)

PTNet to S-

Component

Decomposition

S-Component to

FSM Mapping

Synchronization

Primitive

Extraction

Synchronization

Integration FSM1

a.S47/

b/

c/

ε/x

FSM23

ε/y∙z

a.S3/

d/

30

FINAL RESULT

a

b c d

x y z

PTNet

FSM1

a.S47/

b/

c/

ε/x

FSM23

ε/y∙z

a.S3/

d/

MSFSM

FSMs Synchronization

31

COMPLEXITY

O(PT+P2) • PTNet to S-Component

Decomposition

O(P2T2) • S-Component to FSM Mapping

O(P3T2) • Synchronization Primitive

Extraction

O(P2T) • Synchronization Integration

O(P3T2)

32

OVERVIEW

PTNet Synthesis Flow to Asynchronous Circuit

PTNet Decomposition to BMFSMs

PTNet Decomposition to S-Components

S-Components Transformation to

BMFSMs

BMFSMs Synchronization

Synchronization Primitives Extraction

Synchronization Integration

33

STEPS 1/3

Ri+

Ro+

Ai+ Ao+

Ro- Ri-

Ai- Ao-

PTNet

PTNet to S-

Component

Decomposition S-Component to

BM-FSM

Mapping

Synchronization

Primitive

Extraction

Synchronization

Integration

1. Choose a signal (Ri) and form

all the consecutive transition

pairs (Ri+,Ri-) (Ri-,Ri+)

34

STEPS 1/3

Ri+

Ro+

Ai+ Ao+

Ro- Ri-

Ai- Ao-

PTNet




2. For each pair (Ri+,Ri-)

(i)remove all concurrent PTNet

components

(ii)DFS to connect pair’s

transitions

PTNet to S-

Component


BM-FSM

Mapping

Synchronization

Primitive

Extraction

Synchronization

Integration

35

STEPS 1/3

Ri+

Ro+

Ao+

Ri-

Ao-

SComponent

PTNet to S-

Component


BM-FSM

Mapping

Synchronization

Primitive

Extraction

Synchronization

Integration




2. For each pair (Ri+,Ri-)

(i)remove all concurrent PTNet

components

(ii)DFS to connect pair’s

transitions

3. Remove all unmarked PTNet

components and their

corresponding arcs

36

STEPS 1/3

PTNet to S-

Component


BM-FSM

Mapping

Synchronization

Primitive

Extraction

Synchronization

Integration

Ai+

Ro-

Ai-

Ro+

Ro-

Ro+

Ao+

Ao-

SC1

SC2

Ri+

Ri-

Ro+

Ao+

Ao-

SC3

Ri+

SCover

Ri+

Ro+

Ai+ Ao+

Ro- Ri-

Ai- Ao-

PTNet

Ro,Ai

Ro,Ao Ri,Ao

37

STEPS 2/3

PTNet to S-

Component


BM-FSM

Mapping

Synchronization

Primitive

Extraction

Synchronization

Integration

SC1

FSM1

ε/Ro+

Ai+

Ro-

Ai-

Ro+

Ai+/ ε/Ro-

Ai-/

38

STEPS 3/3

PTNet to S-

Component


BM-FSM

Mapping

Synchronization

Primitive

Extraction

Synchronization

Integration FSM1

Ai+/

Ai-/

FSM2

ε/Ro-

ε/Ao-

Ri+/

ε/Ro+

ε/Ro-

ε/Ro+

ε/Ao+

Ai Ro

S1 0 0

S2 0 1

S3 1 1

S4 1 0

Ao

S5 0

S6 0

S7 1

S8 1

S9 0

1. Form the Signal Support

for each BMFSM

FSM2 FSM1

39

STEPS 3/3


for each BMFSM

2. Insert Synchronizing

BMFSMs

S1+,S5+

/sync1+

S1-,S5-

/sync1-

S3+,S7+

/sync2+

S3-,S7-

/sync2-

FSM1

FSM2

Ai Ro

S1 0 0

S2 0 1

S3 1 1

S4 1 0

Ao

S5 0

S6 0

S7 1

S8 1

S9 0

Ai+/

Ai-/

ε/Ro-

ε/Ao-

Ri+/

ε/Ro+

ε/Ro-

ε/Ro+

ε/Ao+

FSM2 FSM1

PTNet to S-

Component


BM-FSM

Mapping

Synchronization

Primitive

Extraction

Synchronization

Integration

40

STEPS 3/3

FSM1

sync1-,Ai+/

sync2-/Ai-/

sync2+

/Ro-

sync2-/Ao-

Ri+/

sync1+

/Ro+

sync2+

/Ro-

sync1+

/Ro+

sync1-/Ao+

Ai Ro S1 S3 sync1 sync2

S1 0 0 1 0 0 0

S2 0 1 0 0 1 0

S3 1 1 0 1 0 0

S4 1 0 0 0 0 1


for each BMFSM

FSM2 FSM1

2. Insert Synchronizing

BMFSMs

S1+,S5+

/sync1+

S1-,S5-

/sync1-

S3+,S7+

/sync2+

S3-,S7-

/sync2-

3. Insert Synchronization

Logic

PTNet to S-

Component


BM-FSM

Mapping

Synchronization

Primitive

Extraction

Synchronization

Integration

41

COMPLEXITY

O(PT3+ P2T2)

• PTNet to S-Component Decomposition

O(P2T2) • S-Component to BM-FSM Mapping

O(P3T2) • Synchronization Primitive Extraction

O(P2T) • Synchronization Integration

O(P3T2+PT3)

42

OVERVIEW

• Motivation

• Background

• MSFSMs

• Synthesis

• Verification

• Optimization

• Results


43

INTERACTING FSMS

TO PTNETS

a.S3/o

a’.S4/o’

FSMa

b.S1/

b’.S2/

FSMb SCa

o

a-

o-

a

SCb

b-

b

Interacting FSMs SCover

o

a-

o-

a b

b-

PTNet

C a

b

o

44

MSFSM VERIFICATION

PU1

PU2

PU3

CTRL

Ri2

Ri1 Ro

Ao1

Ao2 Ai

Ri1/

ε/Ao1

Ri1’/

ε/Ai1’

Ri2/

ε/Ao2

Ri2’/

ε/Ai2’

ε/Ro

Ai/

ε/Ro’

Ai’/

Synchronization Points

W Dependent States

S8 S1, S5

S1 S10

S5 S10

Is the Concurrent System Deadlock-Free?

45

MSFSM VERIFICATION

PU1

PU2

PU3

CTRL

Ri2

Ri1 Ro

Ao1

Ao2 Ai

Ri1/

ε/Ao1

Ri1’/

ε/Ai1’

Ri2/

ε/Ao2

Ri2’/

ε/Ai2’

ε/Ro

Ai/

ε/Ro’

Ai’/

Synchronization Points

W Dependent States

S8 S1, S5

S1 S10

S5 S10

Ri1/

ε/Ao1

Ri1’/

ε/Ai1’

ε/Ro

Ai/

ε/Ro’

Ai’/

Ri2/

ε/Ao2

Ri2’/

ε/Ai2’

46

MSFSM VERIFICATION

ε/Ro

Ai/

Ri2/

ε/Ao2

Ri2’/

ε/Ai2’

Ri1/

Ri1’/

ε/Ai1’

ε/Ro

Ai/

Ri1/

ε/Ao1

Ri1’/

ε/Ai1’

ε/Ro

Ai/

ε/Ro’

Ai’/

Ri2/

ε/Ao2

Ri2’/

ε/Ai2’

The system is covered by 5 initially marked

minimal siphons.

Deadlock-Free

47

OVERVIEW

• Motivation

• Background

• MSFSMs

• Synthesis

• Verification

• Optimization

• Results


48

HORIZONTAL AND

VERTICAL COLLAPSING

f1/g1

FSM

Vertical Horizontal

FSM min

f2/g2

f1 ∙ f2

/g1 ∙ g2

(t1)

(t2)

(t12)

• t1 and t2 are not synced and g1=ε | f2=ε

• t1 is synced and f2=ε

• t2 is synced and g1=ε

f/g

FSM

(t1)

f’/g’

FSM’

(t’1)

+ = f ∙ f’ /g ∙ g’

FSM min

• FSM and FSM’ exhibit concurrency between

transitions t and t’

• f(t)=ε & f’(t)=ε

• g(t)=ε & g’(t)=ε

49

HORIZONTAL AND

VERTICAL COLLAPSING

E

Ri

Ai

Ro

Ao

I O

L

FSMLHS

Ri/

ε/Ai

Ri’/

ε/Ai’

ε/Ro

Ao/

ε/Ro’

Ao’/

ε/L

ε/L’

FSMRHS

FSMLTH

50

HORIZONTAL AND

VERTICAL COLLAPSING

E

Ri

Ai

Ro

Ao

I O

L

FSMLHS

Ri/Ai

Ri’/Ai’

Ao’/Ro

Ao/Ro’

ε/L

ε/L’

FSMRHS FSMLTH

51

HORIZONTAL AND

VERTICAL COLLAPSING

E

Ri

Ai

Ro

Ao

I O

L

FSMmin

Ri∙Ao’/Ai∙Ro∙L

Ri’∙Ao/Ai’∙Ro’∙L’

52

FSM

X-COMPATIBLES

f1/g1

(t1)

f’1/g’1

(t’1)

tb1

tb2

FSM’ FSM

f1 ∙ f’1

/g1 ∙ g’1

tb1

tb2

FSM’

• Two transitions are X-Compatible if they are concurrent and

mutually inclusive.

• t1 and t1’ are X-Compatible

53

X-COMPATIBLES

EXTRACTION

tb1

tb2

(t1) (t7)

(t8) (t6) (t5) (t4)

(t3) (t2)

entry entry

exit exit FSM1 FSM2

CFG1 CFG2

54

X-COMPATIBLES

MINIMIZATION

entry entry

exit exit

CFG1 CFG2

entry

exit

entry

exit

Dominator Tree1

Dominator

Tree2

55

X-COMPATIBLES

MINIMIZATION

entry

exit

entry

exit

DFS From entry

to exit

56

X-COMPATIBLES

MINIMIZATION

entry

exit

entry

exit

DFS From entry

to exit

Form X-

Compatibles

57

X-COMPATIBLES

MINIMIZATION

DFS From entry

to exit

Form X-

Compatibles

Synchronize

tb1

tb2

(t1) (t7)

(t8) (t6) (t5) (t4)

(t3) (t2)

FSM1 FSM2

tbcc1

tbcc2

58

X-COMPATIBLES

MINIMIZATION

DFS From entry

to exit

Form X-

Compatibles

Synchronize

tb1

tb2

(t1∙t7)

(t6∙t8) (t5) (t4)

(t3) (t2)

FSM1 FSM2

Minimize

59

OVERVIEW

• Motivation

• Background

• MSFSMs

• Synthesis

• Verification

• Optimization

• Results


60

RESULTS

110

1001000

10000100000

100000010000000

1000000001E+091E+101E+111E+121E+131E+141E+151E+161E+171E+181E+19

Global State Space vs. MSFSM State Space

GLOBAL STATE SPACE MSFSM STATE SPACE

61

• Transforming a PTNet to MSFSMs and then to a synthesizable equivalent does

not suffer from the state explosion issue.

ASYNCHRONOUS

SYNTHESIS SYNTHETIC

BENCHMARK

62

N Parallel Handshake Controllers

M Sequential Controllers Per Pipeline

Synchronized at the M stage

63

AREA

• Expose unveils the solution space between the direct mapping approaches

and the ones which require the complete state space

64

EXECUTION TIME

• Expose execution time scales with the size of the initial specification

CONTROL CIRCUITS

AREA

Benchmark Petrify Optimist Expose

alloc-outbound 66 258 30

c3 12 198 13

count2 Irresolvable CSC 302 178

dff 44 304 20

duplicator 93 228 111

full 44 264 102

half 43 198 148

monkey N/A 1148 181

rpdft 34 214 25

semi-decoupled 86 242 208

vbe6a 132 732 237

65

OPTIMIZATION AREA

66

• Applying the introduced transformations at the MSFSM level predictably reduces area.

67

OPTIMIZATION

PERFORMANCE

• Applying the introduced transformations at the MSFSM level typically increases

performance.

OVERVIEW

• Motivation

• Background

• MSFSMs

• Synthesis

• Verification

• Optimization

• Results


68

CONCLUSIONS

Novel Control Specification Model, MSFSMs

• Key for Concurrent Specifications Synthesis and Verification

Logic Synthesis Tool, Expose, Targeting Synchronous and

Asynchronous Logic

Optimization Operations with Predictable QoR

69

FUTURE WORK

Logic Synthesis of Mixed Synchronous and Asynchronous

Circuits

Examination of the Concurrency / Area Trade-Off Unveiled by

the X-Compatibles Optimization

Expansion of the supported Asynchronous Timing Models

• Speed Independent

70

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