Long Shaping-time Silicon Readout

Bruce SchummUniversity of California, Santa

CruzAmsterdam ECFA-DESY Workshop

April 1-4 2003

Participants

Dave Dorfan, Christian Flacco, Alex Grillo, HartmutSadrozinski, Bruce Schumm, Abe Seiden, Ned Spencer,Lan Zhang

Also, a new post-doc (Gavin Nesom) will join the effort in April

Potential external associates: SLAC, LPNHE Paris,CERN RD50

North American SD Tracker

Motivation - I

Min-i for 300m Si is about 24,000 electrons

Shaping (s) Length (cm) Noise (e-)

1 100 2200

1 200 3950

3 100 1250

3 200 2200

10 100 1000

10 200 1850

Agilent 0.5 m CMOS process (qualified by GLAST)

Motivation - II

Use of long shaping-time read-out (low noise) plus exploitationof duty cycle permits developmentof very long, thin ladders

Additionally, limited readout and servicing may lead tovery limited material budget in forward region (down to100 mrad)

Scope and Funding

Work funded via a two-year, $90,000 grant fromthe DOE Advanced Detector R&D Program

(Will need to enter regular LC funding game afterwards)

• 9 months graduate student support• Chip fabrication• Long-ladder development (existing sensors)• Electronics servicing to ladder

Detailed ScopeGiven the duration and magnitude of the support, our`deliverables’ will be

• Characterization of long shaping-time analog characteristics of CMOS process• Development of pulse development and electronic simulation for shaping-time and readout- scheme optimization• Demonstration of noise level commensurate with readout of 1-2m ladder• Demonstration of x100 suppression of IR heating loss• Min-i readout of long ladder

Pulse Dev SimulationEffects incorporated:

• Landau fluctuations (SS_SimSIdE, Jerry Lynch, LBNL)• Carrier (hole) diffusion / space-charge repulsion• Lorentz angle• Electronic noise• Pulse digitization / reconstruction

Uncorrelated Sampling Check

Long Shaping-time Bail-out

Much of pulse simulation effort goes into `weighting-field’ calculation (pulse-development Green’s Fnc)

However, integral of total charge is• e if electron hits strip• 0 if electron misses strip

In --> infinity limit, this is all you need to worry about!

Carrier Diffusion

)(21

exp),(0

2

ttDr

trPq

Hole diffusion distribution given by

Offest t0 reflects instantaneous expansion of hole clouddue to space-charge repulsion. Diffusion constant given by

hq qkT

D

Reference: E. Belau et al., NIM 214, p253 (1983)

sec65.00 nt

h = hole mobility

Space-charge Effects

Model deposition as uniform line of charge of radius and linear charge density .

After separation of electrons, holes, distribution expandsconformally:

1)(2

0

0 tsts

Time-Over-Threshold (TOT)

i-min

thresh

e

e

nn

i-min

pulse

e

e

nn

r

TO

T/

/r

/te

etr

TOT given by differencebetween two solutions to

(RC-CR shaper)

Digitize with granularity /ndig

Other Simulation Aspects

For now, assume mobilizing field that of plane-biaseddiode (obscures details of field near strips)

Variable inputs:• Detector geometry (pitch, thickness)• Magnetic field• Track parameters• Detector bias

Lorentz Angle (holes): 36 mrad/T

Result: S/N for 167cm Ladder

At shaping time of 3s; 0.5 m process qualified by GLAST

Pulse Simulation Goals

Questions to be answered:

• Signal-to-noise for long ladders• Optimal sensor geometry • Evaluation of analog readout scheme (time-over threshold; 2xTOT, direct analog, least-bit, etc.; goal of <7 m resolution)• Effect of large magnetic fields• Effects of oblique angles of incidence• Optimal detector bias

Hardware QualificationLe

aka

ge C

urr

ent

(A)

Potential Associations

Aurore Savoy-Navarro (LPNHE Paris)

Have discussed development of full-scale ladder,readout for testbeam run

RD-50 (CERN, Mara Bruzzi)

Standing request for expert consultation (Lorentzangle, diffusion and mobility vs. B, etc.)

Possible exploration of `Czochralski’ sensors (largearea, but leakage current needs work for now)

Next Six Months

Immediately: begin SPICE-level optimization of shapingtime (assuming 1-2 meter ladder)

Have already begun qualifying GLAST 8-channel `cutoff’structures for use in 2m ladder

April: begin mechanical design and construction oftwo-meter ladder

Submission of prototype ASIC in June-July

Longer Term

NOTE: Project funded from DOE ADR program through 2003; afterwards, will need to switch to nominal sources!

• Fall 2003: measure noise and power consumption characteristics• Winter 2003 (likely): begin design of 2nd prototype chip based on accumulated experience• Winter 2004: begin development of realistic prototype ladder, prepare for testbeam run• Summer 2004: testbeam studies; begin to develop scheme for back-end architecture