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CIRF Circuit Intégré Radio Fréquence
Low Noise Amplifier
Delaram Haghighitalab Hassan Aboushady Université Paris VI
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Multidisciplinarity of radio design
H. Aboushady University of Paris VI
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• M. Perrott, “High Speed Communication Circuits and Systems”, M.I.T.OpenCourseWare, http://ocw.mit.edu/,
Massachusetts Institute of Technology, 2005. • D. Leenaerts, J. van der Tang, and C. Vaucher, “Circuit
design for RF transceivers”, Kluwer academic publishers, 2001.
References
H. Aboushady University of Paris VI
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Heterodyne
Homodyne (Direct conversion)
Low-IF
4
LNA : 1st block of an RF Receiver
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Noise Factor : SNRin
SNRout F =
NF = 10 log10(F)
F1 G1
F2 G2
F3 G3
Si So
5 University of Paris VI
LNA Requirements: Noise
Noise Figure :
( ) ( ) ( )12121
3
1
21 ...
1...11)1(1−
−++
−+
−+−+=
n
nGGG
FGG
FGFFF
Friis Equation :
LNA Requirements to reduce the RF receiver overall Noise Factor:
• Low Noise Factor, F1 • High Gain, G1
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x(t) y(t)
Vi Vo
α1,3IPA
...11 23,3
21
21
22,3
21
21,3
23
+++≈IPIPIPIP AAAAβαα
ω ω1 ω2 ω ω1 ω2 2ω1-ω2 2 ω2 -ω1
ΔP
dBmindB
dBm PP
IIP +Δ
=2
3
6
β2,3IPA
γ3,3IPA
University of Paris VI
LNA Requirements: Linearity
LNA Requirements to improve the RF receiver overall linearity: • High AIP3,1 • Low α1
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• Impedance Matching
• Noise Calculations
• LNA Design • Systematic LNA Design Procedure
Outline
H. Aboushady University of Paris VI
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• Impedance Matching
• Noise Calculations
• LNA Design • Systematic LNA Design Procedure
Outline
H. Aboushady University of Paris VI
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• Impedance Matching
• Noise Calculations
• LNA Design • Systematic LNA Design Procedure
Outline
H. Aboushady University of Paris VI
-
• Impedance Matching
• Noise Calculations
• LNA Design • Systematic LNA Design Procedure
Outline
H. Aboushady University of Paris VI
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Vin
Rout
Vout
M1
Cgd
- Parasitic capacitance Cgd between input and output nodes. - Low Gain - Complex Load Impedance
outmv ZgA .=
)1( 0par
outout CjrRZ
ω=
38
Common Source Amplifier
D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI
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Vin
Vout
M1
M2
Lout - Isolation between input and output nodes - Higher Gain
)1( 00
0 outpar
cascodeout LjCjrZ ω
ω=
39 D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI
Common Source Cascode with Inductive Load
Benefits of Cascode
- Real Load Impedance can be obtained
Purpose of Inductive Load
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Vin
Vout
M1
M2
Lout
M3
R
Rref
Current Mirror
- The current in M1 is fixed by Rref and the ratio (W1/L1)/(W3/L3). - R is to increase the impedance seen by the input signal.
40 D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI
Biasing
Current Mirror
-
Vin
Vout
M1
M2
Lout
M3
R
Rref
Ldeg
Lg
- Lg compensates the complex impedance due to Cgs1 . - Ldeg adjusts the real part of the input impedance to 50 Ω .
41 D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI
Matching Input Impedance
Inductive Degeneration
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42
Input Impedance
Matching Zin to 50Ω
For a Real Impedance @ ω0
degdeg )(1)( L
CgLLs
sCsZ
gs
mg
gsin +++=
degLCgRgs
ms =
gsg CLL )(1
deg0
+=ω
D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI
Ldeg and Lg (1)
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43
For different Ldeg values
Re{
Zin}
Lg
⇒ Re{Zin} independent of Lg
D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI
Ldeg and Lg (2)
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44
Re{
Zin}
Im
{Zin
}
Lg
Lg
⇒ Ldeg for: Re{Zin}=50 Lg for: Im{Zin}=0
D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI
For different Ldeg values
⇒ Re{Zin} independent of Lg
Ldeg and Lg (2)
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45
Techno. 0.35µm c= -‐0.4j γ = 2/3
D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI
NF of a MOS Transistor
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)()()(
)(
)(
)(
)(
)(
)(
.).(
addedosourceototalo
sourcei
totalo
totaloi
sourceii
totaloo
sourceii
o
i
NNNNGN
NGSNS
NSNS
SNRSNRF
+=
====
)(
)(
)(
)()(
)(
)( 1sourceo
addedo
sourceo
addedosourceo
sourceo
totalo
NN
NNN
NN
F +=+
==⇒
1) No(added) : Output Reffered Noise due to the LNA. 2) No(source): Output Reffered Noise due to the source.
46 D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI
NF Characterization
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R
RkTiR 42 =
R
Résistance
D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI
Noise Sources
-
48
R
RkTiR 42 =
R
fgkTi
fgkTi
gsg
dd
Δ=
Δ=
δ
γ
4
42
02
Résistance Transistor
D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI
Noise Sources
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49
R
RkTiR 42 =
R Ls
Rs
Csub
Rsub Rsub Rs
fgkTi
fgkTi
gsg
dd
Δ=
Δ=
δ
γ
4
42
02
Résistance Transistor Inductance
D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI
Noise Sources
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R
RkTiR 42 =
R Ls
Rs
Csub
Rsub Rsub Rs
50
fgkTi
fgkTi
gsg
dd
Δ=
Δ=
δ
γ
4
42
02
),,,,,.( 22222 RsubRsubRsRsRRggddi HiHiHiHiHiNGfNF =
)(
)(1sourceo
addedo
NN
F +=)(addedoN
Resistance Transistor Inductance
)(sourceoND. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI
Noise Sources
-
I
inI
)()()(sIsIsH
in
outd =
51 D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI
Noise Sources
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out
out
out
Vin
Vin
Circuit
Circuit
Circuit
Iin
in
Gain : Input Impedance: Noise Factor:
)()()(sVinsVoutsGain =
)()()(sIinsVinsZin =
52
)(
)(1sourceo
addedo
NN
F +=
D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI
Characterization
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53
Length: Minimum L to reduce parasitic capacitances. Width: Ids calculated for NFmin.
Layout: Maximum number of fingers to reduce Gate resistance.
Ldeg : Adjusted for Re {Zin} = 50 Ω .
Lg : Adjusted for Im {Zin} = 0 Ω .
Lout : Adjusted for the desired Zout and Gain.
D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI
Design Procedure
Transistors
Inductors
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Techno
Transistors Sizing
NF min?
Rs f0 Vdd
Ids-‐min (Wmin,Lmin)
Caracteriza+on of NF , Gain, Zin
No
Yes
Gain Topology
Choose Inductances
Calculate NF
Impedance Matching
Gain OK?
Yes
No Gain Adjustment
Ids++
54 University of Paris VI
Automatic Sizing Procedure
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Techno
Transistors Sizing
NF min?
Rs f0 Vdd
Ids-‐min (Wmin,Lmin)
Caractérisa+on de NF , Gain, Zin
No
Yes
Gain Topology
Choose Inductances
Calculate NF
Impedance Matching
Gain OK?
Yes
No Gain Adjustment
Ids++
55 University of Paris VI
Automatic Sizing Procedure
-
Techno
Transistors Sizing
NF min?
Rs f0 Vdd
Ids-‐min (Wmin,Lmin)
Caracteriza+on of NF , Gain, Zin
No
Yes
Gain Topology
Choose Inductances
Calculate NF
Impedance Matching
Gain OK?
Yes
No Gain Adjustment
Ids++
{ } 50Re:
deg ≈in
gout
ZpourL
initialesvaleursLetL
56 University of Paris VI
Automatic Sizing Procedure
-
Techno
Transistors Sizing
NF min?
Rs f0 Vdd
Ids-‐min (Wmin,Lmin)
Caracteriza+on of NF , Gain, Zin
No
Yes
Gain Topology
Choose Inductances
Calculate NF
Impedance Matching
Gain OK?
Yes
No Gain Adjustment
Ids++
57 University of Paris VI
Automatic Sizing Procedure
-
Techno
Transistors Sizing
NF min?
Rs f0 Vdd
Ids-‐min (Wmin,Lmin)
Caracteriza+on of NF , Gain, Zin
Non
Yes
Gain Topology
Choose Inductances
Calculate NF
Impedance Matching
Gain OK?
Yes
No Gain Adjustment
I++
58 University of Paris VI
Automatic Sizing Procedure
-
Techno
Transistors Sizing
NF min?
Rs f0 Vdd
Ids-‐min (Wmin,Lmin)
Caracteriza+on of NF , Gain, Zin
No
Yes
Gain Topology
Choose Inductances
Calculate NF
Impedance Matching
Gain OK?
Yes
No Gain Adjustment
Ids++
59 University of Paris VI
Automatic Sizing Procedure
-
Techno
Transistors Sizing
NF min?
Rs f0 Vdd
Ids-‐min (Wmin,Lmin)
Caracteriza+on of NF , Gain, Zin
No
Yes
Gain Topology
Choose Inductances
Calculate NF
Impedance Matching
Gain OK?
Yes
No Gain Adjustment
Ids++
60 University of Paris VI
Automatic Sizing Procedure
-
61 University of Paris VI
Automatic Sizing Procedure
Techno
Transistors Sizing
NF min?
Rs f0 Vdd
Ids-‐min (Wmin,Lmin)
Caracteriza+on of NF , Gain, Zin
No
Yes
Gain Topology
Choose Inductances
Calculate NF
Impedance Matching
Gain OK?
Yes
No Gain Adjustment
Ids++
Ldeg for Re{Zin}=50 Lg for Im{Zin}=0
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Gain Adjustment
62 University of Paris VI
Automatic Sizing Procedure
Techno
Transistors Sizing
NF min?
Rs f0 Vdd
Ids-‐min (Wmin,Lmin)
Caracteriza+on of NF , Gain, Zin
No
Yes
Gain Topology
Choose Inductances
Calculate NF
Impedance Matching
Gain OK?
Yes
No
Ids++
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Gain Adjustment
63 University of Paris VI
Automatic Sizing Procedure
Techno
Transistors Sizing
NF min?
Rs f0 Vdd
Ids-‐min (Wmin,Lmin)
Caracteriza+on of NF , Gain, Zin
No
Yes
Gain Topology
Choose Inductances
Calculate NF
Impedance Matching
Gain OK?
Yes
No
Ids++
Choice of Lout :
)(.
outout
outmv
LfZZGA
=
−=
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Gain Adjustment
64 University of Paris VI
Automatic Sizing Procedure
Techno
Transistors Sizing
NF min?
Rs f0 Vdd
Ids-‐min (Wmin,Lmin)
Caracteriza+on of NF , Gain, Zin
No
Yes
Gain Topology
Choose Inductances
Calculate NF
Impedance Matching
Gain OK?
Yes
No
Ids++
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Technologie 0.13 um Vdd 1.2 V
Résistance de source (Rs)
50 Ω
Fréquence centrale (f0)
2.4 GHz
Gain ≥ 15 dB
W (um)
L (um) Vgs (V)
Vds (V)
Ids(mA)
M1 48.96 0.13 0.6 0.6 3.3122
M2 48.96 0.13 0.6 0.6 3.3122
M3 5.08 0.13 0.6 0.6 0.33122
R= 100 KΩ , Rref = 1.811 KΩ , Ldeg = 0.3709 nH , Lg = 48.65 nH , Lout = 3 nH 65
Spécifications
Résultats de la procédure proposée
D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI
Design Example I: A 2.4GHz LNA in 130 nm CMOS
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Gain (dB) NF (dB) ELDO 19.04 0.727277
66 D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI
Estimated and Simulated Gain and NF
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S11
(dB
) S
21 (d
B)
F (Hz)
67
S11 @ 2.4 GHz =-24.24 dB S21 @ 2.4 GHz = 17.028 dB
D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI
Simulated S Parameters
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IIP3= - 0.44 dBm
68
Fondamentale
IM3
D. Haghighitalab, M. Vasilevski & H. Aboushady University of Paris VI
Simulated IIP3