Low-Power and High-Speed Interconnect Using Serial Passive Compensation

Chun-Chen Liu and Chung-Kuan Cheng

Computer Science and Engineering Dept.

University of California, San Diego http://www.cse.ucsd.edu/~kuan/

Outline

Motivation Previous Works and Our Contributions Proposed Passive Compensation Technique

Theory Experiments: An MCM stripline Case

Analytical Performance Prediction Experimental Results and Future Work

Motivation

Technology Advancement: Interconnect is one bottleneck of system performance.

Bandwidth Increase: Interchip communication is expected to exceed 15GHz in 2010.

Low Power Requirement: IO consumes one major portion of chip power budget.

Previous Works Overview

On-chip serial link signaling schemes Pre-emphasis and equalization (W. Dally, ’98) Clocked discharging (Horowitz, ISVLSI’03) Frequency modulation (Wong, JSSC’03, Jose, ISVLSI‘05) Non-linear transmission line (Hajimiri, JSSC’05, E. C.

Kan, CICC’05)

Passive compensation Resistive termination (Hashimoto, EPEP’04, Tsuchiya,

CICC’04, Flynn, ICCAD’05, CICC’05) Surfliner (C.K Cheng, ASPDAC’07)

Published on-chip serial link signaling schemes- Resistive Termination

Use resistive termination to cut the slow RC top

Michael Flynn, ICCAD ‘05

Tsuchiya et al. developed an analytical model of eye opening with resistive termination for on-chip transmission line (CICC ’05)

Published on-chip serial link signaling schemes- Surfliner

Use shunt resistors to reduce loss tangent and maximize eye-opening and minimize jitters.

Haikun Zhu et al. developed an analytical model for eye opening with shunt resistors.

Haikun Zhu et al. Aspdac’07

Our Contributions The main advantages of this work

Adopt a novel serial passive impedance scheme to reduce the power consumption and improve the bandwidth.

Derive eye prediction methods using bitonic assumption. Propose a new interconnect scheme with wide band working

frequency.

Our proposed scheme MCM interconnect using parallel resistor and capacitor as

equalizer.

Problem Formulation and Design Flow Problem Formulation

Input: T line with R(f), L(f), G(f), C(f) (IBM EIP). Output: Best Zd to maximize the eye diagram.

Design Flow1. Set Rd = Rskin- Rdc, 2. Repeat steps 3, 4 with tuned Cd to maximize eye-opening 3. Generate step response using HPSICE.4. Predict eye diagram using step response.

Theory Analytical -Bitonic Step Response Assumption

Bitonic step response assumption A step response that monotonically increases to its

peak and then monotonically decreases to saturation voltage.

We use three parameters V1, Vmax and Vsat to predict the eye diagram.

Theoretical Analysis Telegrapher’s equations

Propagation Constant

Wave Propagation

and correspond to attenuation and phase velocity. Both are frequency dependent in general.

Characteristic Impedance

Implementation

Interconnect Scale

On-chip MCM Board

Length 10mm 10cm 25cmSeries Resistance at DC

10Ω/mm 1Ω/mm 0.01Ω/mm

Cross Section Dimension

1μmx1μm 8μmx4.5μm 4milx1.2mil

Dielectric Material SiO2 Ceramic FR4

Dielectric Constant 3.9 3.4 3.4Loss Tangent 0.00068 0.0018 0.016Frequency dependency

Small Large Significant

Operation Region RC RLC RLCSkin depth of pure copper

0.66 μm @ 10GHz

Experiment Setting:• Geometry is based on IBM high-end

AS/400 system.

• Line length = 10 cm.

Step Response with Rd and Rt (10 segments)

Step Response with Rt (10 segments)

Step Response with Zd and Rt (10 segments)

Eye-height/jitter vs Rd and Cd (10Gbps)

Eye Diagram – Zd, Rt30Gbps with Cd=0.41e-12, Rd=141, Rt=74

Vheight= 0.303V, Jitter; 2.41ps

Eye Diagram- Zd , Rt40 Gbps with Cd=0.31e-12, Rd=168, Rt=74

Vheight= 0.23V, Jitter= 2.1ps

Eye Diagram- Zd, Rt50 Gbps, with Cd=3e-13, Rd=193, Rt=74

Vheight= 0.21V, Jitter= 4.21ps

Eye Diagrams- Zd, Rt100 Gbps with Cd=1e-13, Rd=247, Rt=74

Non-Distinguishable

Eye Diagrams - Rt

30Gbps with Rd= 0, Rt=70

Vheight= 0.188V, Jitter= 13.78ps

Eye Diagrams - Rt

40Gbps with Rd= 0, Rt=70

Vheight= 0.07V, Jitter= 15.59ps

Eye Diagrams – Rd, Rt10Gbps, Rd=74,

Vheight= 0.269V, jitter=7.03ps

Eye Diagrams – Rd, Rt20Gbps, Rd=74

Vheight= 0.163V, jitter=10.04ps

Eye Diagrams – Rd, Rt30Gbps, Rd=74

Vheight= 0.103V, jitter=15.01ps

Eye Diagrams – Rd, Rt40Gbps, Rd=74

Vheight= 0.043V, jitter=16.2ps

Experimental Results

Rd= Rskin-Rdc, Rdc=50ohm

Optimal solution, and power consumption comparisonAchieve lowest power consumption.Reach up to 50Gbps with open eyes.

Compared predicted Eye-high with HSPICE

Future Work

Automate the synthesis.Prototype & measurement.Incorporate transmitter/receiver.Applications: clock trees, buses.

Q/A

Thank You