low power and low spur frequency synthesizer circuit ... · • manikandan.r.r, bharadwaj amrutur,...

Low Power and Low Spur FrequencySynthesizer Circuit Techniques for Energy

Efficient Wireless Transmitters

by

Manikandan.R.R

Submitted to the Department of Electrical Communication

Engineering

in partial fulfillment of the requirements for the degree of

Doctor of Philosophy

at the

INDIAN INSTITUTE OF SCIENCE

September 2015

I certify that I have read this thesis and that, in my opinion, it is fully

adequate in scope and quality as a thesis for the degree of Doctor of

Philosophy.

(Dr. Bharadwaj Amrutur) Principal Advisor

Approved for the University Committee on Graduate Studies.

ii

© Copyright by Manikandan.R.R 2016

All Rights Reserved

iii

Abstract

There has been a huge rise in interest in the design of energy efficient wireless

sensor networks (WSN) and body area networks (BAN) with the advent of many

new applications over the last few decades. The number of sensor nodes in these

applications has also increased tremendously in the order of few hundreds in recent

years.

A typical sensor node in a WSN consists of circuits like RF transceivers, micro-

controllers or DSP, ADCs, sensors, and power supply circuits. The RF transmitter

and receiver circuits mainly the frequency synthesizers (synthesis of RF carrier and

local oscillator signals in transceivers) consume a significant percentage of its total

power due to its high frequency of operation. A charge-pump phase locked loop

(CP-PLL) is the most commonly used frequency synthesizer architecture in these

applications.

The growing demands of WSN applications, such as low power consumption, larger

number of sensor nodes, single chip solution, and longer duration operation presents

several design challenges for these transmitter and frequency synthesizer circuits in

these applications and a few are listed below,

• Low power frequency synthesizer and transmitter designs with better spectral

performance is essential for an energy efficient operation of these applications.

• The spurious tones in the frequency synthesizer output will mix the interference

signals from nearby sensor nodes and from other interference sources present

nearby, to degrade the wireless transmitter and receiver performance [1]. With

the increased density of sensor nodes (more number of in-band interference

sources) and degraded performance of analog circuits in the nano-meter CMOS

process technologies, the spur reduction techniques are essential to improve the

performance of frequency synthesizers in these applications.

• A single chip solution of sensor nodes with its analog and digital circuits in-

tegrated on the same die is preferred for its low power, low cost, and reduced

size implementation. However, the parasitic interactions between these analog

and digital sub-systems integrated on a common substrate, degrade the spectral

performance of frequency synthesizers in these implementations [2]. Therefore,

techniques to improve the mixed signal integration performance of these circuits

are in great demand.

In this thesis, we present a custom designed energy efficient 2.4 GHz BFSK/ASK

transmitter architecture using a low power frequency synthesizer design technique tak-

ing advantage of the CMOS technology scaling benefits. Furthermore, a few design

guidelines and solutions to improve the spectral performance of frequency synthesizer

circuits and in-turn the performance of transmitters are also presented. The target

application being short distance, low power, and battery operated wireless communi-

cation applications.

The contributions in this thesis are,

Spectral performance improvement techniques

• The CP mismatch current is a dominant source of reference spurs in the nano-

meter CMOS PLL implementations due to its worsened channel length modu-

lation effect [3]. In this work, we present a CP mismatch current calibration

technique using an adaptive body bias tuning of its PMOS transistors.

Chip prototype of 2.4 GHz CP-PLL with the proposed CP calibration technique

was fabricated in UMC 0.13 µm CMOS process. Measurements show a CP

mismatch current of less than 0.3 µA (0.55 %) using the proposed calibration

technique over the VCO control voltage range 0.3 to 1 V. The closed loop PLL

measurements using the proposed technique exhibited a ≃9 dB reduction in the

reference spur levels across the PLL output frequency range 2.4 - 2.5 GHz.

• The parasitic interactions between analog and digital circuits through the com-

mon substrate severely affects the performance of CP-PLLs. In this work, we

experimentally demonstrate the effect of periodic switching noise generated from

the digital buffers on the performance of charge-pump PLLs. The sensitivity

of PLL performance metrics such as output spur level, phase noise, and output

jitter are monitored against the variations in the properties of a noise injector

digital signal.

Measurements from a 500 MHz CP-PLL shows that the pulsed noise injection

with the duty cycle of noise injector signal reduced from 50% to 20%, resulted

in a 12.53 dB reduction in its output spur level and a 107 ps reduction in its

Pk-Pk deterministic period jitter performance.

Low power circuit techniques

• A low power frequency synthesizer design using a digital frequency multipli-

cation technique is presented. The proposed frequency multiply by 3 digital

ii

edge combiner design having a very few logic gates, demonstrated a significant

reduction in the power consumption of frequency synthesizer circuits, with an

acceptable spectral performance suitable for these relaxed performance appli-

cations. A few design guidelines and techniques to further improve its spectral

performance are also discussed and validated through simulations.

Chip prototypes of 2.4 GHz CP-PLLs with and without digital frequency mul-

tiplier circuits are fabricated in UMC 0.13 µm CMOS process. The 2.4 GHz

CP-PLL using the proposed digital frequency multiplication technique (10.7

mW) consumed a much reduced power compared to a conventional implemen-

tation (20.3 mW).

• A custom designed, energy efficient 2.4 GHz BFSK/ASK transmitter architec-

ture using the proposed low power frequency synthesizer design technique is

presented. The transmitter uses a class-D power amplifier to drive the 50Ω

antenna load. Spur reduction techniques in frequency synthesizers are also used

to improve the spectral performance of the transmitter.

A chip prototype of the proposed transmitter architecture was implemented in

UMC 0.13 µm CMOS process. The transmitter consume 14 mA current from a

1.3 V supply voltage and achieve improved energy efficiencies of 0.91 nJ/bit and

6.1 nJ/bit for ASK and BFSK modulations with data rates 20Mb/s & 3Mb/s

respectively.

iii

Acknowledgements

I would like to thank my advisor Dr. Bharadwaj Amrutur for the continuous support

throughout my Ph.D study, for his patience, motivation, enthusiasm, and immense

knowledge. He inculcated the skills required for research in me by giving the freedom

to explore on my own, and at the same time the guidance to recover when my steps

faltered. I am sure that this dissertation would not have been possible without his

support and encouragement.

I take this opportunity to thank all teachers who have made me learn in my life

till now. I am especially grateful to Rajamani miss (my school teacher), Prof. P.V.

Ramakrishna (my under grad teacher), and Prof. Bharadwaj Amrutur (my Ph.D

advisor) with whom i had spent a significant portion of the learning phase of my

life so far. I would like to thank Prof. Navakanta Bhat, Prof. Gaurab Banerjee,

Prof. K.N Bhat, Prof. Vittal Rao and others for the knowledge they imparted to me

through their courses.

I owe my gratitude to Prof. Shanthi Pavan, Prof. Nagendra Krishnapura, Prof.

Jacob Baker, Prof. Elad Alon and others for generously sharing the video lectures of

courses taught by them at their universities. It has greatly helped me in my research

and I will always be indebted to them for this.

I have been fortunate to work with many wonderful colleagues. Over the years,

BT, Vikram, Tejasvi, Nandish, Pratap, Rajath, Viveka, Kaushik, Mohan, Janaki,

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Raghu, Karthik, Syam, Siva, Pushkar, Vishal, Immanuel, Zaira, Manas, Javed, and

many others have kept surroundings enjoyable and informative. I also thank my

friends in IISc Abhishek, Laxmi, Trupti, Siva, Hari, Nirmal, Baban, Bhushan, Neeraj,

and many others who had made my stay here a memorable and enjoyable one.

I thank the support staff of ECE department especially Srinivas Murthy, Sub-

hashini, and Radhika who had helped me in multiple ways with the administration

work. I would also like to acknowledge Ministry of Human Resource Development,

Govt. of India for providing the scholarship.

Finally, I wish to thank my parents for their unconditional love, support, patience

and understanding during these years.

This work was supported by Department of Electronics and Information Technol-

ogy, Govt. of India.

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Publications based on this thesis

Peer-Reviewed Journal Articles

• Manikandan.R.R, Bharadwaj Amrutur, Experimental Study on Substrate Noise

Effects of a Pulsed Clocking Scheme on PLL Performance, Circuits and Systems

II: Express Briefs, IEEE Transactions on, volume 60, Issue 12, pp. 852-856,

2013.

• Manikandan.R.R, Abhishek kumar, and Bharadwaj Amrutur, A Digital Fre-

quency Multiplication Technique for Energy Efficient Transmitters, Very Large

Scale Integration (VLSI) Systems, IEEE Transactions on, volume 23, pp. 781-

785, 2015.

• Manikandan.R.R, Bharadwaj Amrutur, A Zero Charge-Pump Mismatch Cur-

rent Tracking Loop for Reference Spur Reduction in CP-PLLs, Microelectronics

Journal, Elsevier, volume 46, pp. 422-430, 2015.

vi

Contents

Acknowledgements iv

Publications based on this thesis vi

1 Introduction 1

1.1 Thesis Contribution and Organization . . . . . . . . . . . . . . . . . 5

1.1.1 Contributions in this thesis . . . . . . . . . . . . . . . . . . . 6

1.1.2 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . 8

2 Background 10

2.1 Sensor node architecture . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1.1 Transmitter - Basic operation . . . . . . . . . . . . . . . . . . 11

2.1.2 Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1.3 Transmitter performance metrics . . . . . . . . . . . . . . . . 13

2.2 Transmitter architectures . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.2.1 Direct conversion mixer based transmitter architecture . . . . 16

2.2.2 PLL based transmitter architecture . . . . . . . . . . . . . . . 17

2.3 Low power PLL based transmitter architecture . . . . . . . . . . . . . 21

2.4 Effects of non-ideal spectral performance . . . . . . . . . . . . . . . . 24

2.4.1 Spurious tones . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

vii

2.4.2 Reference spurs . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.4.3 Mixed signal integration effects . . . . . . . . . . . . . . . . . 33

3 Reference Spur Suppression Technique 37

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.2 Prior work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.3 Current steering charge-pump circuit . . . . . . . . . . . . . . . . . . 41

3.3.1 Proposed CP mismatch current calibration technique . . . . . 42

3.4 Zero CP Mismatch Current Tracking PLL Architecture . . 45

3.5 Experimental Setup and Measurements . . . . . . . . . . . . . . . . . 51

3.5.1 Frequency synthesizer . . . . . . . . . . . . . . . . . . . . . . 51

3.5.2 Zero charge-pump mismatch current tracking loop . . . . . . . 54

3.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4 Substrate noise effects 59

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4.1.1 Noise injection . . . . . . . . . . . . . . . . . . . . . . . . . . 60

4.1.2 Noise propagation . . . . . . . . . . . . . . . . . . . . . . . . . 61

4.1.3 Noise reception . . . . . . . . . . . . . . . . . . . . . . . . . . 62

4.2 Techniques to reduce substrate noise effects . . . . . . . . . . . . . . 63

4.3 PLL design details . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

4.4 Experimental setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

4.5 Periodic switching noise effects on PLL performance . . . . . . . . . . 68

4.6 Noise coupling mechanisms . . . . . . . . . . . . . . . . . . . . . . . . 70

4.7 Substrate noise effects of pulsed clocking scheme . . . . . . . . . . . . 74

4.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

5 Low Power Frequency Synthesis 78

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

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5.2 Frequency Multiplication by Edge Combining . . . . . . . . . . . . . 80

5.3 Frequency Multiplication Circuit Techniques . . . . . . . . . . . . . . 84

5.4 Digital Frequency Multiplier Implementation . . . . . . . . . . . . . . 87

5.4.1 Logic Gate Topology Induced Mismatch . . . . . . . . . . . . 88

5.4.2 Layout Induced Mismatch Effects . . . . . . . . . . . . . . . . 91

5.4.3 Process Induced Device Mismatch . . . . . . . . . . . . . . . . 92

5.5 Impact of Technology Scaling . . . . . . . . . . . . . . . . . . . . . . 96

5.6 Frequency multiplication factor - M . . . . . . . . . . . . . . . . . . . 99

5.7 Frequency Synthesizer - Simulation Results . . . . . . . . . . . . . . . 100

5.8 Chip Implementation and Measured Results . . . . . . . . . . . . . . 104

5.9 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

6 2.4 GHz BFSK/ASK Transmitter 114

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

6.2 Energy Efficient Transmitter Architecture . . . . . . . . . . . . . . . 115

6.3 Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . 116

6.3.1 Phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . 117

6.3.2 Digital edge combiner . . . . . . . . . . . . . . . . . . . . . . 118

6.3.3 Reference spur suppression circuits . . . . . . . . . . . . . . . 121

6.4 Class-D power amplifier . . . . . . . . . . . . . . . . . . . . . . . . . 122

6.5 Transmitter Modulation and Transmission Performance . . 123

6.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

7 Conclusion and Future Works 129

7.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

7.2 Future Directions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

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Contents

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List of Tables

2.1 Transmitter power spectral density (PSD) mask specifications. . . . . 15

2.2 PLL based transmitters - performance summary. . . . . . . . . . . . . 20

3.1 Charge-pump performance summary and comparison. . . . . . . . . . 44

3.2 Performance summary and Comparison. . . . . . . . . . . . . . . . . 56

5.1 Transistor threshold voltage. . . . . . . . . . . . . . . . . . . . . . . . 98

5.2 VCO performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

5.3 Summary of PLL performance (simulation) . . . . . . . . . . . . . . . 104

5.4 Frequency Multiplication Performance Comparison . . . . . . . . . . 111

6.1 Frequency synthesizer performance summary. . . . . . . . . . . . . . 120

6.2 Reference spur suppression performance summary. . . . . . . . . . . . 121

6.3 Transmitter Performance Comparison - BFSK. . . . . . . . . . . . . . 127

6.4 Transmitter Performance Comparison - ASK. . . . . . . . . . . . . . 128

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List of Figures

1.1 Typical data-rates and coverage range for various short distance wire-

less standards [4]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Typical multi-hop wireless sensor network architecture (Image refer-

ence : Wikipedia). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.3 Spurious tones in the PLL output signal frequency spectrum. . . . . . 4

1.4 Single chip solution of a sensor node with its digital and analog circuits

integrated on the same die. . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Sensor node architecture. . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2 Simplified block diagram of transmitter. . . . . . . . . . . . . . . . . 11

2.3 Digital modulation schemes. . . . . . . . . . . . . . . . . . . . . . . . 13

2.4 Constellation diagram for EVM and FSK error calculations. . . . . . 14

2.5 Direct conversion mixer based transmitter architecture - Block diagram. 16

2.6 Phase locked loop based transmitter architecture - Block diagram. . . 17

2.7 PLL based transmitter architecture - open loop configuration. . . . . 18

2.8 Effect of closed loop PLL operation on the BFSK modulation perfor-

mance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.9 PLL based two point ∆ − Σ modulation transmitter. . . . . . . . . . 19

2.10 Low power PLL based TX using frequency multiplication technique. . 21

2.11 Local oscillator pulling in direct conversion transmitter architecture. . 23

xii

2.12 Effect of non-ideal frequency multiplication - broadband spurs. . . . . 23

2.13 Effects of frequency synthesizer spurious tones on the transmitter and

receiver performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.14 Conventional Type II, 3rd order Integer-N charge-pump PLL used for

LO generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.15 PLL transient waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 27

2.16 Effect of UP signal switching delay (Tinv) on the VCO control voltage. 28

2.17 Effect of loop filter leakage current (Ileak) on the VCO control voltage. 29

2.18 Charge-pump mismatch current (∆I) due to channel length modula-

tion effect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.19 Charge-pump mismatch current effect - Transient waveforms. . . . . . 31

2.20 Mixed signal integration effects on the charge-PLL performance. . . . 35

3.1 Conventional Type II, 3rd order Integer-N charge-pump PLL. . . . . . 38

3.2 Simulation conditions : Icp = 100 µA, Kvco = 500 MHz/V, Rz = 28.18

KΩ, Cz = 84.58 pF, Cp = 6.51 pF, and fref = 5 MHz. . . . . . . . . 39

3.3 Charge-pump mismatch current calibration techniques. . . . . . . . . 40

3.4 Current steering charge-pump circuit and its transient wave-forms (Iup <

Idn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.5 Measured charge-pump output current characteristics (L = 3 µm). . . 42

3.6 Simulated ID, VT dependence on body voltage (V b) of PMOS transistor

(W = 30 µm, L = 3 µm). . . . . . . . . . . . . . . . . . . . . . . . . 43

3.7 Measured CP output current characteristics, (L = 3 µm) with the

PMOS transistor body voltage varied between 1.3 V and 1.2 V (4 bit

control, Iup < Idn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.8 Measured CP mismatch current characteristics, with the PMOS tran-

sistor body voltage varied between 1.3 V and 1.2 V (4 bit control,

(Idn − Iup). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.9 Zero charge-pump mismatch current tracking PLL architecture. . . . 45

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3.10 Simulated step response of VCO control voltage (2.4 to 2.5 GHz). . . 46

3.11 Charge-pump output current characteristics : SAR algorithm. . . . . 47

3.12 VCO control voltage in the zero CP mismatch current tracking mode. 48

3.13 SAR controller working : PMOS bulk voltage and CP mismatch current. 48

3.14 Simulation conditions : Icp = 100 µA, Kvco = 300 MHz/V, Rz = 28.18

KΩ, Cz = 84.58 pF, Cp = 6.51 pF, fref = 5 MHz, and Tpfd = 5 ns. . 50

3.15 DAC architectures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.16 Die photograph of the fabricated test chip in 0.13 µm CMOS process

and the experimental setup used to demonstrate the proposed concept. 52

3.17 Measured VCO transfer characteristics (VCO + EC output, PVT cal-

ibration bits, B5 to B0). . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.18 Measured phase noise characteristics of 2.4 GHz signal. . . . . . . . . 53

3.19 Measured reference and feedback signals with the PLL operating in its

steady state mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.20 Measured static phase error and reference spur with the CP mismatch

current reduction loop disabled and enabled (Fout = 2.4 GHz, Fref =

1.667 MHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.21 Measurements across PLL operating frequency range 2.4 - 2.5 GHz. . 57

4.1 Substrate noise - injection, propagation and reception mechanisms. . 60

4.2 Clock distribution network using a multilevel tree architecture used in

synchronous digital systems. . . . . . . . . . . . . . . . . . . . . . . . 61

4.3 Types of substrate used in CMOS IC’s. . . . . . . . . . . . . . . . . . 62

4.4 Type II, 3rd order integer-N charge-pump PLL. . . . . . . . . . . . . 65

4.5 Measured VCO transfer characteristics for different bias-current tran-

sistor widths Wp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

4.6 Chip layout and die photograph showing the noise injector buffers (1,2,3). 67

4.7 Measured result : Impact of 5 MHz periodic substrate noise generated

from digital buffers on the PLL performance. . . . . . . . . . . . . . . 68

xiv

4.8 Type II, 3rd order integer-N charge-pump PLL and noise injector buffers

- Test bench. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

4.9 VCO output spectrum (open loop) with spurs at 2 MHz offset in re-

sponse to 2 MHz noise injected in the substrate. . . . . . . . . . . . . 71

4.10 Open loop VCO characterization (fnoise = 10 MHz). . . . . . . . . . . 72

4.11 Sensitivity of VCO (open loop) output spur level to the periodic noise

frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

4.12 Measured sensitivity of PLL output spur levels to the frequency and

duty cycle of a noise injector signal. . . . . . . . . . . . . . . . . . . . 75

4.13 Effect of a pulsed clock noise injector signal (fclock = 2.5 MHz) on the

PLL output spur levels. . . . . . . . . . . . . . . . . . . . . . . . . . . 75

4.14 Measured duty cycle effects of a 5 MHz noise injected in substrate on

Pk-Pk deterministic period jitter performance of 500 MHz PLL output

signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

5.1 Low power frequency synthesizer design using frequency multiplication

technique. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

5.2 Frequency multiplication by edge combining principle (fout = 3 ∗ fRO). 81

5.3 Effects of non-ideal frequency multiplication (fout = 3 ∗ fRO). . . . . . 82

5.4 Effect of timing mismatch (0.904 ≤ p1 ≤ 1.096) on CSR performance. 83

5.5 Frequency multiplication circuit implementation - Conceptual diagram. 84

5.6 Frequency multiplication circuit techniques. . . . . . . . . . . . . . . 85

5.7 Digital edge combiner (or frequency multiplier) implementation. . . . 87

5.8 Digital logic gates used in the edge combiner implementation. . . . . 89

5.9 Digital edge combiner waveforms - standard implementation for logic

gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

5.10 Digital edge combiner waveforms - symmetric implementation for logic

gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

5.11 Digital edge combiner (fout = 3 ∗ fRO). . . . . . . . . . . . . . . . . . 92

xv

5.12 Effect of layout parasitics on the frequency multiplied output signal. 92

5.13 Monte Carlo simulation results of carrier to spur ratio (CSR) for the

edge combiner circuit shown in Fig. 5.11a, W = 3µm, R = 1, M = 3,

fout = 2.4 GHz, and fin = 800 MHz. . . . . . . . . . . . . . . . . . . 93

5.14 Monte Carlo simulation results - Effect of transistor widths on the

carrier to spur ratio (CSR) performance of the edge combiner. . . . . 94

5.15 Process corners and temperature effects on the carrier to spur ratio

performance of the edge combiner. . . . . . . . . . . . . . . . . . . . . 96

5.16 Effect of relative strength of PMOS and NMOS transistors (R) on the

2nd harmonic power and the duty cycle of edge combiner output signal. 96

5.17 Standard deviation of difference in transistor threshold voltages versus

the inverse square root of the transistor area (W ∗ L), for 130 nm and

65 nm process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

5.18 Impact of process technology on the edge combiner CSR performance.

Transistor length chosen as 200 nm for all devices. . . . . . . . . . . . 98

5.19 Edge combiner implementation, divider power consumption and CSR

performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

5.20 Frequency synthesizer - block level description. . . . . . . . . . . . . . 101

5.21 VCO phase noise performance. . . . . . . . . . . . . . . . . . . . . . . 103

5.22 Chip micrograph in 0.13 µm CMOS process and test setup used in

measurements. Chip 1 contains frequency multiplication based trans-

mitter circuits and chip 2 contains a conventional 2.4 GHz PLL for

receiver LO generation. . . . . . . . . . . . . . . . . . . . . . . . . . . 105

5.23 Current steering charge-pump circuit used in the PLL and its measured

output current characteristics. . . . . . . . . . . . . . . . . . . . . . . 106

5.24 Pseudo-differential voltage controlled ring oscillator circuit. . . . . . . 107

5.25 Measured VCO transfer characteristics (B5 to B0) in the up-converted

2.4 GHz frequency band. . . . . . . . . . . . . . . . . . . . . . . . . . 107

xvi

5.26 PLL closed loop measurement results (fout = 2.4 GHz). . . . . . . . . 108

5.27 Digital edge combiner - measurement results. . . . . . . . . . . . . . . 109

6.1 Low power 2.4 GHz BFSK/ASK PLL-based transmitter architecture. 115

6.2 Chip micro-graph in 0.13 µm CMOS process and the test setup used

in measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

6.3 Charge-pump and VCO measurements. . . . . . . . . . . . . . . . . . 119

6.4 PLL closed loop - measured results (fout = 2.4 GHz). . . . . . . . . . 119

6.5 Digital edge combiner - measured results (fout = 2.4 GHz). . . . . . . 119

6.6 Class-D power amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . 122

6.7 Measured PA output power (50Ω load) Vs PWM control voltage. . . . 122

6.8 Measured S22 at the output of PA. . . . . . . . . . . . . . . . . . . . 123

6.9 BFSK modulation performance for "1010" data pattern measured using

vector signal analyzer (VSA). . . . . . . . . . . . . . . . . . . . . . . 124

6.10 Measured ASK transient waveform from TX using "1010" data pattern. 125

xvii

Chapter 1

Introduction

In recent years, there has been a huge rise in interest in the short distance wireless

communication applications such as Internet of Things (IoT), health monitoring with

wearable technology, air pollution and water quality monitoring, and traffic monitor-

ing. Various types of wireless communication systems and wireless standards have

been developed for these applications, including wireless local area network (WLAN),

wireless personal area network (WPAN), wireless body area network (WBAN), im-

plantable devices, and wireless sensor network (WSN). Fig. 1.1 shows the typical

data rates and coverage distances for these wireless standards.

1 10 100 1000

100k

1M

10M

100M

Implant

WBAN WPAN

WLAN

WSN

Dat

a ra

te (

b/s)

Distance (m)

Figure 1.1: Typical data-rates and coverage range for various short distance wirelessstandards [4].

The wireless communication circuits in these applications differ greatly in terms

of data rate, power level, and complexity due to its different system requirements.

Therefore, different architectures and circuit techniques have been developed to satisfy

1

2

the specific application needs and to optimize the performance.

Fig. 1.2a shows the description of a typical wireless sensor network architecture. It

consists of spatially distributed sensor nodes (few hundreds) to monitor physical and

environmental conditions such as temperature and pollution, and a gateway sensor

node to pass the recorded data from all sensor nodes to a main location. Fig. 1.2b

shows the block level description of a sensor node and it consists of circuits like RF

transmitter and receiver, micro-controller, ADCs, sensors, and a power source.

Computer

Gatewaysensor node

Sensor node

(a) Wireless sensor network.

Micro-controller

Sensor 1

Sensor 2

ADCPow

er source

External memory

Transmitter Receiver

(b) Sensor node.

Figure 1.2: Typical multi-hop wireless sensor network architecture (Image reference: Wikipedia).

The RF transmitter circuits in a typical sensor node must operate at low to

moderate data-rates [5] [6] [7] and its low power implementation with a good spectral

performance is necessary. The transmitter circuits are typically realized using PLL

based architectures in these sensor network applications due to its simpler design, fully

integrated solution, low power and low area implementation advantages [8] [9] [10] [11].

The receiver circuits are used for passing signals from one sensor node to other and to

the main controller location, to receive control signals and for occasional handshaking

purposes.

Synthesis of RF carrier and local oscillator signals in these transmitter and re-

ceiver circuits consume a large percentage (20-30%) of the total power [11] [12] [13].

3

Furthermore, the spectral performance of the frequency synthesizer circuits (magni-

tude of unwanted spurious tones) determines the performance of the communication

system as well. A charge-pump phase locked loop (CP-PLL) is the most commonly

used frequency synthesizer architecture in these applications [14].

The recent advent of many new sensor network applications and the requirement

for large number of sensor nodes (≃20 per cubic meter) in these applications, presents

several design challenges for these frequency synthesizer and transmitter circuits, such

as low power implementation, high data-rates, improved spectral performance, and

single chip solution, a few are discussed below.

Low power implementation - The sensor nodes in these networks are normally

powered using a battery or an energy harvested power source. The larger number of

sensor nodes and the nature of environment in which the WSN’s operate makes the

battery replacement in these sensor nodes impractical and the total energy harvested

from the common surroundings are also limited [15] [16].

The RF transmitter and receiver circuits, mainly the frequency synthesizers due

to its high frequency of operation dominate the total power consumption of a sensor

node compared to its other low frequency operating digital circuits such as Micro-

controllers, ADC’s and digital I/O buffers. Therefore, an energy efficient sensor node

design with low power transmitter and frequency synthesizer circuits are essential for

long duration operation of these wireless sensor networks [17] [18].

Reference spur related issues - The unwanted spurious tones generated at refer-

ence frequency (fref) offsets from the target frequency (fout) in the frequency spectrum

of PLL output signal are called reference spurs [19] - [23] (Fig. 1.3a). The reference

spurs are generated due to the non-idealities of the phase frequency detector, charge-

pump and the loop filter blocks in a CP-PLL. Large reference spurs will mix the

signals from adjacent channels to degrade both transmitter and receiver performance

in a wireless transceiver [1].

4

fout fout + freffout - fref

Referencespur (dBc)

(a) Reference spur.

fout fout + fnoisefout - fnoise

Spur level(dBc)

(b) Periodic disturbance (fnoise) effects.

Figure 1.3: Spurious tones in the PLL output signal frequency spectrum.

Larger the number of sensor nodes in a WSN, more the number of in-band inter-

ference sources present in a network. Therefore, with the growing number of sensor

nodes (more than 20 nodes per cubic meter) and the severe channel length modula-

tion effect of nano-meter CMOS process technologies, the reference spur effects are

becoming a critical issue in these sensor network applications. Therefore, reference

spur reduction techniques are required to improve the performance of transceiver

operation in these applications.

Mixed signal integration issues - A single chip solution of sensor node with its

analog and digital circuits integrated on the same die is preferred for its low power,

low cost, and reduced size implementation (Fig. 1.4). However, the design of a

mixed-signal systems-on-a-chip faces great number of challenges. One of them is the

performance degradation of analog circuits due to the parasitic interactions between

the digital and analog sub-systems integrated on the same chip [24] [25].

The digital circuits inject noise currents into the substrate during their signal

transitions. The digital buffers in a clock distribution network having very large

drive strengths inject significant amount of noise currents in the substrate [26]. The

substrate is a conductive medium and hence allows these noise currents to propagate

from the digital circuits to the analog circuits integrated on the same substrate.

The analog/RF circuits are sensitive to the voltage fluctuations in the substrate and

1.1. Thesis Contribution and Organization 5

Rx

PLL + PA

Micro -controller

ADCs Sensorinterface

Sens

or a

rray

Pow

er s

uppl

y ci

rcui

ts

External memory

Figure 1.4: Single chip solution of a sensor node with its digital and analog circuitsintegrated on the same die.

therefore, the coupled noise degrades its performance [27].

In a charge-pump PLL, the periodic voltage fluctuations in the common substrate

generated due to a periodic digital activity, couple to its sensitive nodes and then

frequency modulates the VCO [2] [28]. This generates spurious tones in its output

signal spectrum as shown in Fig. 1.3b.

The digital systems in a typical sensor node operate using low frequency clock

signals in the frequency range of few MHz. With more and more digital functionality

added to a sensor node, and the noise injector frequencies placed around the reference

frequency [2], the increased substrate noise effects in these implementations result in

a degraded spectral performance of the transmitter and receiver circuits.

1.1 Thesis Contribution and Organization

This thesis presents a custom designed energy efficient 2.4 GHz BFSK/ASK trans-

mitter architecture using a low power frequency synthesizer design technique taking

advantage of the CMOS technology scaling benefits. Furthermore, a few design guide-

lines and solutions to improve the spectral performance of these frequency synthesizer


circuits and in-turn the performance of transmitters are also presented. The target

application being short distance (≃ 10m), low power, and battery operated wireless

communication applications.

1.1.1 Contributions in this thesis

Reference spur suppression technique - The charge-pump (CP) mismatch current is

the dominant source of static phase error and reference spurs in the nano-meter CMOS

PLL implementations, due to its worsened channel length modulation effect [3]. In

this work, we present a charge-pump mismatch current calibration technique using

an adaptive body bias tuning of its PMOS transistors. The proposed technique

compensates for the DC current mismatch and the mismatch due to channel length

modulation effect, and hence improves the performance of CP-PLLs in its nano-meter

CMOS implementations.

Chip prototype of a 2.4 GHz, integer-N CP-PLL with the proposed charge-pump

mismatch current calibration technique was fabricated in a UMC 0.13 µm CMOS

process. Measurements show a CP mismatch current of less than 0.3 µA (0.55 %)

using the proposed calibration technique, over the VCO control voltage range of 0.3

to 1 V.

A zero CP mismatch current tracking loop was implemented off-chip for an au-

tomatic mismatch current calibration with respect to the VCO control voltage. The

closed loop PLL measurements using the proposed technique show a ≃9 dB improve-

ment in the reference spur performance and a reduced static phase error of within

±70 ps across the output frequency range 2.4 - 2.5 GHz.

Substrate noise effects - The need for more functionality in systems-on-a-chip

drives the integration of noise-sensitive analog/RF circuits and the noisy digital cir-

cuits on the same chip. In this case, the parasitic interactions between analog and

digital circuits through the common substrate severely affects the performance of

analog circuits [28] [27] [2]. The digital buffers in a clock distribution network usually


have very large drive strengths and hence inject significant amount of noise currents

in the substrate [26] [29] [30].

In this work, we experimentally demonstrate the effects of periodic switching

noise generated from the digital buffers on the performance of charge-pump PLLs.

The sensitivity of PLL performance metrics such as output spur level, phase noise,

and output jitter are monitored against the variations in the properties of a noise

injector digital signal.

Measurements from a 500 MHz CP-PLL chip shows that the pulsed noise injection

with the duty cycle of noise injector signal reduced from 50% to 20% keeping the

amplitude constant, resulted in a 12.53 dB reduction in its output spur level and a

107 ps reduction in its Pk-Pk deterministic period jitter performance.

Analyses results suggest that operation of digital systems with a pulsed clocking

scheme along with the conventional substrate noise isolation techniques, helps in

an efficient integration of sensitive analog/RF circuits with noisy digital systems,

achieving an enhanced functionality on a single chip.

Digital frequency multiplication technique - Frequency multiplication based PLL

architectures [31] [32] [33] [34] [35] reduce the frequency of operation of VCO and

divider circuits and hence result in a huge power savings in its design.

In this work, we have presented a digital frequency multiplier implementation for

low power frequency synthesis in the relaxed performance, short distance wireless com-

munication applications. The digital implementation of frequency multiplier circuits

offer a broadband operation with low power and low area implementation advantages

compared to the reported analog techniques. Moreover, the digital implementation

benefits from the improved performance of digital circuits in the nano-meter CMOS

process technologies.

Chip prototypes of 2.4 GHz CP-PLLs with and without digital frequency multi-

plier circuits are fabricated in UMC 0.13 µm CMOS technology. The 2.4 GHz PLL

using the proposed digital frequency multiplication technique (10.7 mW) consumed


a much reduced power compared to a conventional implementation (20.3 mW). How-

ever, the implemented low power PLL design suffers due to broadband spurs generated

from non-ideal implementation of the digital edge combiner.

Techniques to improve the spectral performance of the proposed frequency multi-

plier design with a carrier to spur ratio (CSR) of above 30 dB for Personal commu-

nication services (PCS) and above 45 dB for Zig-Bee and MICS applications are also

demonstrated. The presented multiply by 3 digital frequency multiplier design with a

very few logic gates having circuits with symmetric implementation can easily achieve

a CSR of greater than 40 dB as demonstrated through various simulations. Careful

layout practices, larger transistor dimensions, lower threshold voltage devices (VT )

and implementation using advanced CMOS process devices (65nm or less) further

improves its CSR performance to the order of 50 dB.

Energy efficient transmitter design - PLL based transmitters are typically used

for these sensor network applications due to its simpler design, fully integrated solu-

tion, low power and low area implementation advantages [8] [9] [10] [11].

In this work, we present a custom designed energy efficient 2.4 GHz BFSK/ASK

transmitter architecture using the proposed low power frequency synthesizer design

and a class-D power amplifier. Chip prototype of the proposed frequency multiplica-

tion based transmitter design is implemented in UMC 0.13 µm CMOS process. The

TX achieves maximum data rates of 3 Mb/s and 20 Mb/s for BFSK and ASK mod-

ulations, respectively, consuming a 14 mA current from 1.3 V supply voltage. The

corresponding energy efficiencies of the transmitter are 6.1 nJ/bit for BFSK and 0.91

nJ/bit for ASK modulations.

1.1.2 Thesis Organization

Chapter 2 discuss the basics of transmitter operation and its performance metrics.

In addition, the non-idealities in the frequency synthesizer design and its effects on

the transmitter performance will be discussed. Chapter 3 presents the reference spur


suppression technique in charge-pump PLLs and its measurement results. Chapter

4 presents the periodic switching noise effects generated from digital buffers on the

performance of charge-pump PLLs, measured from a test chip and its analysis results.

Chapter 5 presents a low power frequency synthesizer design using a digital frequency

multiplier and its measurement results. Techniques to improve the performance of

proposed digital frequency multiplier are also discussed in Chapter 5. Chapter 6

presents an energy efficient 2.4 GHz BFSK/ASK transmitter design and its measured

results. Chapter 7 concludes the thesis and presents some of the open problems for

future work.

Chapter 2

Background

This chapter briefly presents the background information required to better un-

derstand the technical challenges that accompany the goal of a single chip, low power,

improved spectral performance transmitter and frequency synthesizer circuits targeting

the relaxed performance communication applications.

2.1 Sensor node architecture

The block level description of a sensor node used in the wireless sensor network

applications is shown in Fig. 2.1. The sensor array could consist of temperature,

pressure, mechanical or acoustic vibration and other sensors depending upon the

target application. The ADC converts low frequency (a few KHz) analog data from

the sensors into a corresponding digital bit stream. The DSP unit processes the

digitized bits into necessary information and also manages the operation of each

component in a sensor node. The DSP unit typically operates using low frequency

clock signals in the range of a few MHz [36].

PA

Modulator

LO

LNA

Demodulator

Bas

eban

d / D

SP

Mixer

Mixer

MemoryADC

Sensor 1

Sensor 2

Sensor n

Sens

or a

rray

VGA Filter

Power

supply

circuits

Power

supply

circuits

Transmitter

Receiver

Figure 2.1: Sensor node architecture.

10

2.1. Sensor node architecture 11

The processed digital base-band data from DSP is then converted to a modulated,

high-power, RF signal by the transmitter circuits for wireless transmission. The

receiver circuits are used for passing signals from one sensor node to other and to the

main controller location, to receive control signals and for occasional handshaking

purposes.

The RF transmitter and receiver circuits form the key components of a sensor

node and often consume a significant percentage of its total power consumption due

to its high frequency of operation, high data rate, and low noise performance require-

ments. This work focuses on the low power and improved spectral performance design

techniques for transmitter and frequency synthesizer circuits targeting these sensor

network applications.

To better understand the technical challenges that accompany the goal of a single-

chip, low power, improved spectral performance CMOS transmitter design, some

background information regarding transmitters is helpful. In this section, we discuss

the basic operation of the transmitter and its performance metrics.

2.1.1 Transmitter - Basic operation

PA

ModulatorDSP

Memory

ADCSensor

front-end

Analog section of the transmitter

Mixer

LO

Figure 2.2: Simplified block diagram of transmitter.

Fig. 2.2 shows a simplified block diagram of transmitters used in the sensor

network applications. The DSP generates post processed base-band data from the

sensor nodes and pass it on to the analog section of the transmitter shown in Fig. 2.2.

This base-band signal is then attached to a high frequency signal and this process


is termed as modulation. The modulated signal is then up-converted to the RF

spectrum. Modulation and up-conversion often occur in the same circuit but for the

purposes of clarity the functions are divided in this example. Finally, the signal is

amplified and driven onto the antenna.

In summary, the analog and RF section of a transmitter converts a digital base-

band signal to a modulated, high-power, RF signal.

2.1.2 Modulation

The process of varying one or more properties of a high frequency periodic waveform

with respect to an analog or digital base-band data is called modulation. A modulated

signal may be represented as,

x(t) = a(t) · cos[2πfct + φ(t)] (2.1)

The modulated signal x(t) is essentially a sinusoid centered at fc in which both

the amplitude and phase may contain the desired information. If a(t) is fixed and

φ(t) is time varying, the signal is said to be angle modulated and if the reverse is

true, the signal is amplitude modulated.

The modulating signal may be either digital or analog, however, digital modu-

lation is predominantly used due to its better noise immunity, greater resistance to

channel variations, and higher spectral efficiency in a multi-user environment. Fur-

thermore, the advancements in CMOS process technologies favoring the digital circuit

implementations made digital modulation schemes superior for many communications

systems.

In this case, a digital bit stream is used to vary the phase, frequency and ampli-

tude of a high frequency continuous signal. The short distance, relaxed performance

wireless communication applications typically use simple digital modulation schemes

such as BFSK, BPSK, OQPSK, ASK, and OOK shown in Fig. 2.3.


time

time

time

Basebanddata

BFSK

BPSK

0 1 0 1 0+V

-V

(a) Constant envelope modulation.

time

time

time

Basebanddata

ASK

OOK

0 1 0 1 0+V

-V

(b) Non-constant envelope modulation.

Figure 2.3: Digital modulation schemes.

2.1.3 Transmitter performance metrics

A typical wireless communication system imposes certain limits on the performance

of transmitter and receiver circuits to accommodate multiple users in the system,

with a constant data connectivity. The limits set for transmitter circuits fall under

the following two categories,

Modulation accuracy - An ideal RF transmitter would transmit the desired signal

without any deviation from the ideal signal. In reality, the transmitted signal is not

an exact replica of the ideal signal and the difference between them is quantified

as modulation accuracy. High modulation accuracy is required for high data-rate

wireless communication operation. For digital modulation schemes, the difference

between the ideal signal and the actual signal can be shown more clearly using a

constellation diagram.

Fig. 2.4 a&b shows the constellation diagram for the QPSK and BFSK modula-

tions, respectively. An average estimate (over N samples) of difference between the

ideal signal and the actual signal is used to quantify the modulation performance of

a transmitter. For QPSK and BFSK modulation schemes, the modulation accuracy

is defined by error vector magnitude (EVM) and FSK error estimates, respectively.

EVM measures the average deviation of N received complex chip values (Ij1, Qj1)

from the ideal values (Ij, Qj) as shown in Fig. 2.4a. This can be done by averaging


I

Q

00

01

10

11

s (Ij1,Qj1)

(Ij,Qj) (δIj,δQj)

+f-f fideal

fi

(a) QPSK (b) BFSK

Figure 2.4: Constellation diagram for EVM and FSK error calculations.

the error vector (δIj , δQj) through these N values as shown in Eqn. 2.2, where, S is

the magnitude of vector of the ideal constellation point.

EV M =

√

√

√

√

√

√

1

N

N∑

j=1

(δI2j + δQ2

j)

S2× 100%, where S2 = I2

j + Q2j (2.2)

FSK error =

√

1

N

N∑

i=1

(fi − fideal)2

fideal

× 100% (2.3)

FSK error in Eqn. 2.3 measures the average root mean squared spread of the FSK

demodulated symbol spaced waveform around the ideal symbol (frequency) locations

shown in Fig. 2.4b.

For a target bit-error-rate (BER) performance of 10−3 in the wireless communica-

tion system, the EVM (QPSK) and FSK error (BFSK) estimates must be less than

30% and 10% respectively. Similarly, ASK error estimates and constellation diagram

are also defined for ASK and OOK modulations.

Spectral emissions - In addition to modulation accuracy, it is critical that a trans-

mitter only emit a specified amount of radiation so as not to interfere with other

devices both in the same system and in other systems. Ideally, the transmitter would

2.2. Transmitter architectures 15

Table 2.1: Transmitter power spectral density (PSD) mask specifications.

MICS IEEE 802.15.4(Medical devices) (Zig-bee)

Frequency range 402 - 405 MHz 2400 - 2483.5 MHzTransmit power (max) -16 dBm -3 to +10 dBm

-20 dBc, -20 dBc,In-band |f − fc| ≥ 150 KHz, |f − fc| ≥ 3.5 MHz,

spurious emissions 405 MHz > f > 402 MHz, 2.4835 GHz > f > 2.4 GHz,fc - carrier frequency fc - carrier frequency

Out of band-45 dBc -45 dBc

spurious emissions

only transmit a perfectly modulated signal with no other undesired spectral emis-

sions. However, this is rarely the case and thus limits must be set for the levels of

unwanted spectral emissions. The limit of the spectral emission is set by each radio

standard as a spectral mask requirement. While transmitting a signal, the emission

levels must fall below the limits set by spectral mask.

The spectral mask requirements include both in-band and out-of-band emissions.

Unwanted emissions are caused by a number of factors including non-linearity in the

system, noise resulting from interference with other circuits or spurious tones created

by clocks or frequency synthesizers. Because these non-idealities affect the in-band

signal they can also have an effect on the modulation accuracy. Table 2.1 presents

the power spectral density (PSD) mask specifications of Zig-bee and MICS wireless

standards.

2.2 Transmitter architectures

The fundamental role of a transmitter is to convert a base-band signal to a high power

RF signal. Fig. 2.2 shows a simplified block diagram of the transmitter. The choice

of a transmitter architecture is based on the performance requirements of the target

application.


The transmitter design for short distance, battery operated sensor network appli-

cations should meet the following requirements: fully integrated single chip solution,

low power consumption with better spectral performance, relatively simple modula-

tion schemes with low to moderate data-rates. In this section, transmitter architec-

tures will be discussed with respect to the above mentioned target requirements.

2.2.1 Direct conversion mixer based transmitter architecture

090

I

Q

LO

+

- RF filter(optional)

fRF

PA RF filter

Figure 2.5: Direct conversion mixer based transmitter architecture - Block diagram.

The direct conversion transmitter architectures are attractive for its simplicity of

the signal path and fully integrated solution. Fig. 2.5 shows the block diagram of a

direct conversion mixer based transmitter architecture. The digital base-band I and

Q signals are modulated and up-converted to RF frequency in a single step by the

quadrature modulator. The RF signal then passes through a discrete band-pass filter

before amplification by the PA. This pre-PA filter is not always necessary and is used

to reduce inter-modulation in the PA and to attenuate wide-band noise. Finally, after

the PA, another discrete band-pass filter is typically needed to meet the spectral mask

requirements. A single RF frequency synthesizer performs channel selection (LO).

Although the direct conversion topology is well understood and straight forward

to implement, it is not area and power efficient (150 mW in [37]), since many circuits

are required for quadrature signal processing and frequency up-conversion. Therefore,

a mixer less transmitter architecture may be an appropriate choice for sensor network

applications.


2.2.2 PLL based transmitter architecture

Vdd

VCO

PA

Rz

Cz

Cp

Iup

Idn

UP

DN

PFDVctrlFref

Divider, N

ωp

|HLP|

ωp

|HHP|

ωω

Figure 2.6: Phase locked loop based transmitter architecture - Block diagram.

Although mixer based transmitters employ PLLs to generate LO signals, they do

not directly modulate a PLL. Fig. 2.6 shows the block level description of a PLL

based transmitter architecture. Here, the base-band data is applied to control the

loop components VCO, divider or reference frequency and produce the modulated

signal at the PLL output. The PLL based architectures are compatible with constant

envelope modulation schemes such as FSK, PSK, and MSK.

Compared to mixer based architecture, several circuits, such as mixers, DAC,

filters are eliminated and hence PLL based transmitters are power efficient and well

suited for sensor network applications. The PLL based transmitters can operate in

open loop [38] and closed loop configurations [17].

Open loop approach

Fig. 2.7 shows the PLL based transmitter operating in its open loop configuration.

Here the modulation data is injected to control the VCO directly. The closed loop

PLL operation (S1 - ON, S2 - OFF) is basically used to set the desired channel

frequency and during modulation the loop is broken (S1 - OFF, S2 - ON) to prevent

the PLL from tracking out the modulation data.


Vdd

VCO

PA

Rz

Cz

Cp

Iup

Idn

UP

DN

PFDVctrlFref

Divider, N

Transmitencoder

TX data

S1

S2

DAC

Figure 2.7: PLL based transmitter architecture - open loop configuration.

The advantage of this topology is that the data bandwidth is not limited by the

PLL, and therefore high data-rates can be achieved. However, its transmission quality

is affected by the increased close-in phase noise of open loop VCO, frequency drift

due to PVT variations and disturbances in VCO control line during modulation, and

other non-ideal effects.

Closed loop approach

The closed-loop PLL-based transmitters provide a stable RF carrier. Fig. 2.9 shows

the PLL based transmitter operating in its closed loop configuration. The base-band

data can be applied to adjust the divider value or the reference signal frequency.

In this case, the data bandwidth is constrained by the PLL loop bandwidth, hence

limited to low data-rates.

Modulation can also be performed by injecting the base-band data directly in

the VCO. The direct VCO modulation supports high data-rates, however, the dis-

advantage of this approach is that the modulated waveform will be distorted from

the negative feedback loop of the PLL. Since the PLL acts as a high pass filter when

viewed from the VCO, low frequency components of the modulated data will be cor-

rupted by the PLL. In other words, long strings of zeros or ones will not be modulated


0 01 1 1 1 1 1

time

freq

uenc

y de

viat

ion

from

car

rier

-∆f

+∆f

Ideal

Closed loop modulated

Figure 2.8: Effect of closed loop PLL operation on the BFSK modulation performance.

Vdd

VCO

PA

Rz

Cz

Cp

Iup

Idn

UP

DN

PFDVctrlFref

N/N+1

∆Σ ModulatorChannel select

DACTransmitencoderTX data

Figure 2.9: PLL based two point ∆ − Σ modulation transmitter.

correctly and hence affects the modulation accuracy of the transmitters.

Fig. 2.8 shows the degradation in BFSK modulation performance due to the PLL

closed loop operation, for long strings of zeros or ones present in the base-band data.

A few techniques are reported in the literature to improve the modulation accuracy

of this closed loop PLL based transmitter architecture.

• Two point delta-sigma modulation method - The baseband data is applied to

both the VCO and the divider as shown in Fig. 2.9. In this case, the signal

injected to directly modulate the VCO is subject to the high-pass shaping,

while the signal applied to the divider is low-pass filtered. These two signal


paths are effectively combined to produce an output which is free from the loop

bandwidth limitation [9] [10] [17]. However, the mismatch in modulation gain

between these two paths affects the modulation accuracy performance of the

transmitter.

• Closed loop modulation is more effective if the DC component of the data is

removed. This can be done through Manchester encoding, which replaces 0’s

and 1’s with signal transitions [39]. Even though, the effective data rate is

halved in this case, this solution is preferred for its simpler design.

In summary, the closed loop PLL based transmitters using direct VCO modula-

tion with Manchester encoded data, provide a stable RF carrier, supports constant

envelope modulation schemes with reasonable data-rates and consume lower power

due to its reduced number of components and therefore are highly suitable for sensor

network applications.

Table 2.2: PLL based transmitters - performance summary.

[38] [17] [10] [9] [8] [40]Frequency, (GHz) 2.4 2.4 2.4 2.4 2.4 2.4

Architecture open closed closed closed closed closedModulation BFSK MSK MSK BFSK MSK BFSK

Datarate, (Mb/s) 10 4 4 2 2 1.5Power consumption, (mW)

VCO-

2.52 2.48 4.146.84a 7

Divider 3.24 3.1 2.34PLL (total) 8.25 9.36 5.89 6.84 12.5 14.7

Transmitter (total, mW) 9.2 22.86 8.525 12.42 17 19.5aVCO + Divider

Table 2.2 summarizes the modulation performance and power consumption of a

few of the PLL based transmitters reported in the literature. Frequency synthesizer

circuits consume a significant percentage (> 50%) of the total transmitter power.

Moreover, the VCO and divider circuits in frequency synthesizers due to its high

frequency (fRF ) of operation dominate the total power consumption. Therefore,

2.3. Low power PLL based transmitter architecture 21

low power frequency synthesizer designs with reasonable spectral performance are

essential for an energy efficient transmitter implementation.

VCO circuit designs using micro-machined resonators [41], subthreshold circuit

techniques [42], and current reused architecture [43] and the frequency divider circuit

techniques using injection locking phenomenon [44] [45] are presented in the literature

to reduce the power consumption of these circuits.

2.3 Low power PLL based transmitter architecture

The relaxed frequency accuracy and spectral performance specifications of short dis-

tance wireless communication applications [46] [47] can be used as an extra degree of

freedom in the transmitter architecture design to reduce its power consumption.

In these applications, ring oscillator based VCOs are preferred than LC-VCOs due

to their low power and low area implementation advantages. Also most frequency

synthesizers use flip-flop based digital prescalers to generate the feedback signal for

comparison with a crystal reference. The power consumption of these digital circuits

scales with their operating frequency.

Vdd

VCORz

Cz

Cp

Iup

Idn

UP

DN

PFDVctrl

fref

Programmable Divider

FrequencyMultiplier

Fout = M*Fin

CP

ffb

LPFLow frequency

PLL

fRF/M

fRF

PA

Figure 2.10: Low power PLL based TX using frequency multiplication technique.


Therefore, the power consumption of frequency synthesizer circuits in these appli-

cations can be minimized by operating the PLL at a divided down lower frequency of

fRF

Mand the RF carrier signal can be generated by emploing frequency multiplier cir-

cuits (fout = M ∗ fin) outside the loop [31] - [35]. Here, the VCO and divider circuits

in PLL operate at a lower frequency and hence result in significant power reduction

in this architecture. However, the frequency multiplier circuits used outside the loop

must be designed in a power and performance efficient way to take advantage of the

power savings obtained.

Fig. 2.10 shows the low power PLL based transmitter architecture using frequency

multiplication technique. A low frequency PLL and frequency multiplier circuits

together generate the modulated RF carrier, and the power amplifier amplifier drives

the 50 Ω antenna load. Modulation can be performed by adjusting reference frequency

or divider (low data-rates) and by direct VCO modulation using Manchester encoded

data or two point modulation schemes (high data-rates).

Frequency multiplication based transmitters - Advantages

The frequency multiplication based transmitter architecture shown in Fig. 2.10 has

the following advantages.

• Low power consumption due to the reduced frequency of operation of VCO and

divider circuits in PLL compared to a conventiional transmitter architecture.

• The output of PA is a modulated waveform with large power centered around

the LO frequency (ωRF ). This strong signal couples to the local oscillator and

disturbs its frequency (LO pulling shown in Fig. 2.11), and thereby affecting

the transmitter performance. The frequency multiplication based transmitter

architecture having the LO operating at a reduced frequency of ωRF /M , exhibits

zero LO pulling effect with an improved transmitter performance.


PAMixer

LO

Modulateddata

LOpulling

ωRF

ωLO = ωRF

ωRF

(a) Conventional TX.

PAMixer

LO

Modulateddata ωRF

ωLO = (ωRF/M)

Frequencymultiplier

ωRF/M

ωRFfout = M*fin

(b) Frequency multiplication based TX.

Figure 2.11: Local oscillator pulling in direct conversion transmitter architecture.

Frequency multiplication based transmitters - Limitations

The frequency multiplier circuits in these implementations works on the principle

of edge combining (discussed in detail in Chapter 5). Here, the rising and falling

transitions of a set of equally spaced, M number of phases of a low frequency signal

(fin) are combined to generate a high frequency signal (fout = M ∗ fin).

fin M*fin

Carrierto

spurratio(dB)

Frequency

Pow

er (

dB)

Unwanted spursgenerated due to non-ideal

frequency multiplication

(M+1)*fin(M-1)*fin (M+N)*fin

Figure 2.12: Effect of non-ideal frequency multiplication - broadband spurs.

The non-idealities in the frequency multiplier implementation affects the tran-

sition time instants in the frequency multiplied output signal, thereby introducing

broadband spurs at harmonics of fin in its output signal spectrum as shown in Fig.

2.12. The generated broadband spurs form the out of band interference sources and

hence affects the performance of communication systems present nearby. Therefore,

the broadband spurs must be kept low within the power spectral density (PSD) mask

2.4. Effects of non-ideal spectral performance 24

specifications of the transmitter.

The reported works in [32] - [35], typically use a band-pass resonator with its

resonant frequency tuned to M ∗ fin to reduce the magnitude of broadband spurs.

However, poor on-chip inductor performance [48] with lower quality factors limits the

reduction in the magnitude of broadband spurs, besides occupying a large area.

A detailed description of low power frequency synthesis using frequency multipli-

cation technique, advantages and limitations of various frequency multiplier imple-

mentations are discussed in Chapter 5. In this work, we exploit the higher transi-

tion frequencies and the improved matching performances offered by the nano-meter

CMOS devices and demonstrate a static logic gate based digital frequency multiplier

design for low power frequency synthesis targeting the relaxed performance short dis-

tance wireless communication applications. In Chapter 6, we demonstrate a custom

designed, energy efficient 2.4 GHz BFSK/ASK transmitter architecture using the

proposed low power frequency synthesizer design technique.

2.4 Effects of non-ideal spectral performance

The frequency synthesizer in a sensor node is usually shared between the transmit-

ter and receiver circuits as shown in Fig. 2.1, to minimize the overall system power

consumption. Therefore, frequency synthesizer circuits having improved spectral per-

formance with low phase noise and reduced magnitudes of spurious tones, is essential

to improve the transmission and reception quality of a sensor node.

The sensor network applications have a more relaxed phase noise requirements of

as high as -71 dBc/Hz at 3.5 MHz offset [46]. Hence, ring oscillator based VCOs are

typically used in these applications for its low power and low area implementation

advantages [33] [49]. The phase noise performance of ring oscillators can also be

improved by burning additional power in its design.


2.4.1 Spurious tones

The unwanted spurious tones in the frequency synthesizer output affect the wireless

communication performance by introducing and down-converting the unwanted in-

terference signals, in transmitter and receiver circuits, respectively. Fig. 2.13 shows

the effect of spurious tones present in the frequency synthesizer output on the per-

formance of transmitter and receiver circuits.

Let us assume that the synthesizer output consists of a carrier at ωLO and a spur

at ωS as shown in Fig. 2.13.

LO ωLO ωS

ω0 ωint

ωIF

LOωLO ωS

data

Modulatedbaseband

ωLO ωS

Transmitter Receiver

Figure 2.13: Effects of frequency synthesizer spurious tones on the transmitter andreceiver performance.

• In transmitter operation, the spurious tones in the frequency synthesizer output

introduces in-band or out-of-band undesired signal transmissions (interference

signals), depending upon the frequency location of spurious tones, and thereby

affects the performance of nearby sensor nodes.

• In receiver operation, the spurious tones down-convert the unwanted interfer-

ence signals and affects the bit-error rate (BER) performance of the receiver.

Fig. 2.13 shows the down-converted signal component (from ωLO) and the down-

converted interference component (from ωS) appear at the same IF frequency

(if ωs − ωint = ωIF ).


Typical communication systems demand the spurious tone power levels (ωS) to

be 60 to 70 dB below the carrier (ωLO) [1]. The spurious tones in the frequency

synthesizer are generated primarily due to the following reasons.

• periodic disturbances on the VCO control voltage generated due to the non-ideal

effects in PLL closed loop operation (ωs = ωref , reference spurs).

• periodic disturbances in the PLL, generated from other circuits operating nearby

integrated on the same chip (mixed-signal integration issues).

2.4.2 Reference spurs

The unwanted spurious tones generated at reference frequency (fref) offsets from

the target carrier frequency (fLO) in the frequency spectrum of PLL output signal

are called reference spurs [1]. Larger reference spurs are vulnerable, because, in the

transmitter operation these reference spurs introduce interference signals directly at

the adjacent channel frequency. And in the receiver operation, these reference spurs

down-converts the interference signals present in the neighboring adjacent channels

and affects the BER performance. To explain the origin of these spurious tones, we

discuss the basics of PLL operation in this section.

PLL operation

The PLL generates a stable RF carrier by comparing its output phase with that of

a high quality reference signal (crystal reference) through a negative feedback loop

operation. Fig. 2.14 shows the block level description of a type II, 3rd order integer-N

charge-pump PLL used for LO signal generation.

The phase frequency detector (PFD) compares the reference (crystal) and feedback

(divided down from VCO) signals and generates two output signals (UP and DN)

whose difference in pulse widths is proportional to the amount of phase difference

between its inputs (Fig. 2.15). Here, TP F D is the PFD reset delay. Ideally, TP F D can


Rz

Cz

Cp

Vdd

Iup

Idn

fout fout+freffout-fref

Referencespur (Pspur)

Res

et

Tpfd

Vdd

Vdd

UP

DN

Programmabledivider (N)

foutffb

fref

Static phaseerror (Te)

Vctrl

PFD

CP

LPF

VCO

d

d

q

q

(dBc)

Figure 2.14: Conventional Type II, 3rd order Integer-N charge-pump PLL used forLO generation.

be zero, however, to have a dead zone free operation of PFD and to maintain proper

waveform shapes for UP and DN pulses, a finite TP F D is necessary.

The charge-pump consists of two current sources (switched by UP and DN signals)

and generates a voltage proportional to the phase difference by driving a low pass

filter. The loop filter voltage controls the VCO oscillation frequency. The frequency

divider generates the low frequency feedback signal by dividing down the VCO output

signal, for comparison with a crystal reference.

Ref too early Ref too later Phase locked

Ref

Div

UP

DN

Vctrl

Tpfd Tpfd

Figure 2.15: PLL transient waveforms.

When the loop reaches its steady state operation, the reference clock and the

divider output have the same phase and the phase locked condition is achieved (Fig.

2.15). In other words, the VCO output signal frequency is equal to N times the


reference frequency and thus, frequency multiplication is achieved (fout = N ∗ fref).

Non-ideal effects

In the steady state operation of an ideal PLL, the VCO control voltage is fixed without

any ripple as shown in Fig. 2.15. But in reality due to the circuit non-idealities like

charge-pump current mismatch, loop filter leakage, feedthrough of the charge-pump

switches, timing mismatch between the PFD output signals, a non-zero current Icp(t)

with zero average value is injected into the loop filter [50]. This non-zero current

injection create ripple on VCO control voltage at a reference frequency and then

frequency modulates the VCO, thus generating spurious tones in the PLL output as

shown in Fig. 2.14.

Timing mismatch between PFD output signals

Vdd

TPFD

TPFD

UP

DN

Tinv

Iup

Idn

Icp

Rz

Cz

Cp

Vctrl

UP

DN

TPFD

Tinv

Iup

Idn

Icp

Vctrl

UP

DN

TPFD

Icp

Vctrl

CP

LPF(Tinv = 0) (Tinv ≠ 0)

Figure 2.16: Effect of UP signal switching delay (Tinv) on the VCO control voltage.

The UP and DN signals from the phase frequency detector drive the PMOS and

NMOS current source transistors in the charge-pump respectively. The timing mis-

match between the arrival times of these PFD pulses to the charge-pump transistors

due to the added inverter delay in the UP signal path create ripple on the VCO con-

trol voltage as shown in Fig. 2.16. The timing mismatch between the PFD output

signals is typically less than a gate delay, and hence the magnitude of spurious tones


generated due to this mismatch effect (less than −70 dBc) is less significant compared

to the other mismatch effects [20].

Loop filter leakage current

Vdd

TPFD

TPFD

UPB

DN

Iup

Idn

Icp

Rz

Cz

Cp

Vctrl

UP

DN

TPFD

Icp

Vctrl

UP

DN

TPFD

Icp

Vctrl

CP

LPF(Ileak = 0)

Ileak

Iup

Tref

Ileak

(Ileak ≠ 0)

Figure 2.17: Effect of loop filter leakage current (Ileak) on the VCO control voltage.

The leakage current caused by the charge-pump transistors, VCO varactors, loop

filter capacitors disturbs the VCO control voltage. Ileak in Fig. 2.17 models the

effective leakage current due to these non-ideal effects. In sub-micrometer CMOS

process, the leakage current can be in the order of a few hundreds of pico amperes

and its effect on the magnitude of spur level is less significant [20]. However, due

to the increased gate leakage current in nano-meter CMOS process technologies, the

loop filter capacitor leakage contribute a significant amount of reference spurs in these

implementations. Leakage current recycling techniques and compensation techniques

are presented in the literature to minimize the effect of loop filter leakage current [51]

[52].

Charge-pump mismatch current

Fig. 2.18 shows the charge-pump (CP) circuit description and its output current

characteristics. The UP and DN current sources are implemented using transistors

operating in its saturation region and their currents are expressed as,


Vdd

TPFD

TPFD

UPB

DN

Iup

Idn

Icp

Rz

Cz

Cp

Vctrl

CP

LPF

∆I∆IA

B C

VCO control voltage, Vctrl

Ch

arg

e-p

um

p c

urr

ent,

Icp

IupIdn

Mp

Mn

Figure 2.18: Charge-pump mismatch current (∆I) due to channel length modulationeffect.

Iup =1

2µpCox,p

(

W

L

)

p

(Vgs,p − VT,p)2(1 + λpVds,p) (2.4)

Idn =1

2µnCox,n

(

W

L

)

n

(Vgs,n − VT,n)2(1 + λnVds,n) (2.5)

As the CP output voltage (Vctrl or VCO control voltage) increases, Vds,n increases

and Vds,p decreases, and hence Idn (NMOS current) increases and Iup (PMOS current)

decreases due to the channel length modulation effect (λp & λn). Therefore, the CP

currents Iup & Idn are matched only for a single voltage point (zero mismatch current

point, A) and the mismatch current (Iup − Idn = ∆I 6= 0) exists for all other VCO

control voltages as shown in Fig. 2.18.

Fig. 2.19 shows the transient waveforms of PFD and CP, during the steady state

mode operation of PLL. Tup and Tdn are the pulse widths of UP and DN signals from

PFD. When the PLL is in locked state, voltage on the loop filter is fixed and the net

charge provided by the charge-pump must be zero. To maintain locked condition the

following equation must be always satisfied,

Iup ∗ Tup = Idn ∗ Tdn (2.6)

• If Iup = Idn, ideal case (point A in CP current characteristics shown in Fig.


UP

DN

Vctrl(t)

TPFD TPFD

Tref

UP

DN

Icp(t)

Tref

Iup

∆I

Tdn

UP

DN

Tref

Idn

∆I

(Iup = Idn) (Iup < Idn) (Iup > Idn)

Tup

Tdn

Tup

Icp(t) Icp(t)

Vctrl(t)

Vctrl(t)

Figure 2.19: Charge-pump mismatch current effect - Transient waveforms.

2.18), then Tup = Tdn = Tpfd satisfying Eqn. 2.6 and the voltage on the loop

filter is fixed.

• If Iup < Idn (point B in CP current characteristics shown in Fig. 2.18), then

Tup 6= Tdn to satisfy the locked condition (Eqn. 2.6). Since, falling transitions

of Tup & Tdn are aligned by PFD reset signal, the rising edge of Tup leads that of

the Tdn to satisfy Eqn. 2.6, resulting in larger pulse widths for UP signal. Since

the loop operates periodically at a reference frequency, this mismatch between

CP currents create periodic ripples on the VCO control voltage at a reference

frequency as shown in Fig. 2.19.

• If Iup > Idn, then Tup < Tdn to satisfy locked condition (Eqn. 2.6) and result in

negative ripples on the VCO control voltage.

The reference spur level (Pspur in Fig. 2.14) (using narrow-band frequency mod-

ulation approximation) in the PLL output spectrum generated due to charge-pump

mismatch current can be expressed as [20] [53],

Pspur, (dBc) = 20log[

Icp · Rz · Kvco · Tpfd√2

· ∆I

Icp

]

− 20log(

fref

fpl

)

(2.7)


where Tpfd is the PFD reset delay, ∆i is the CP mismatch current, Icp is the CP

output current, Rz is the resistor value in the loop filter, Kvco is the VCO gain, and

fpl is the frequency of pole in the loop filter given by Cz+Cp

2π·Rz·Cz ·Cp.

A typical CP mismatch current of ≃10% was reported in the literature [20] [54] [55]

for the conventional charge-pump circuits implemented in sub-micrometer CMOS

technology nodes. The calculated reference spur level for a 10% CP mismatch current

using the PLL parameters Icp = 100 µA, TP F D = 5 ns, Kvco = 500 MHz/V, Rz =

28.18 KΩ, Cz = 84.58 pF, Cp = 6.51 pF, and fref = 5 MHz in Eqn. 3.1 is -47.47

dBc. These larger spurious tones form in-band interference sources and hence affect

the wireless communication performance.

The lower supply voltage operation and the severely deteriorated channel length

modulation effect of nano-scaled CMOS process, makes the charge-pump mismatch

current a dominant source of static phase error between the PFD input signals and

the reference spurs in output signal frequency spectrum [19] [56].

Reference spur reduction techniques

Several techniques and methods has been presented in the literature to minimize

the magnitude of reference spurs. These techniques can be classified under following

categories,

• Low VCO gain techniques - From Eqn. 3.1, a low VCO gain reduces the

magnitude of reference spurs in the PLL output. VCO architectures with low

gain (Kvco) and wide frequency tuning range using switched capacitor banks [57]

and dual path control schemes [58] - [60] are presented in the literature to

minimize the reference spurs.

• Randomization techniques - Techniques to randomize the charge distribution

mechanism to the loop filter are proposed in [22] [23] [61] [50] to minimize the

magnitude of reference spurs.


• CP mismatch current reduction techniques - Charge-pump mismatch current

calibration schemes are presented in the literature to minimize the mismatch

between the UP and DN currents of CP [54] [55] [3] [62] [63].

In this work, we present a charge-pump mismatch current calibration technique

utilizing an adaptive body bias tuning of its current source transistors. The proposed

CP calibration technique compensates for the DC current mismatch and the mismatch

current due to channel length modulation effect and hence improves the performance

of CP-PLLs in these nano-scaled CMOS process implementations. Chapter 3 presents

a detailed description and analysis of the proposed technique and also presents its

measured performance obtained from a test chip.

2.4.3 Mixed signal integration effects

A sensor node in the wireless sensor network applications typically consists of circuits

like ADCs, DSP or micro-controller, transmitter, receiver and power supply circuits

as shown in Fig. 2.1. A single chip solution of the sensor node with its analog and

digital circuits integrated on the same die is preferred for its low power, low cost,

and reduced size implementation advantages. However, the integration of analog and

digital sub-systems on the same chip resulted in degraded analog performance due to

the parasitic interactions between them through the common substrate [24] [25].

Parasitic coupling through substrate

The digital circuits inject noise currents into the substrate through their parasitic

capacitance during signal transitions, creating voltage fluctuations in the substrate.

These voltage fluctuations in the substrate are called substrate noise. The gener-

ated substrate noise has two components : random and periodic, generated from

random and periodic digital activity, respectively. The clock buffers in ADCs and

micro-controllers or DSP usually have very large drive strengths and hence inject a

significant amount of noise currents in the substrate [26] [29] [30].


The substrate is a conductive medium and allows the noise currents to propagate

from the digital circuits to the analog circuits integrated on the same substrate. The

analog/RF circuits are sensitive to the voltage fluctuations in the substrate and hence

the coupled noise degrades its performance.

Parasitic coupling effects on frequency synthesizers

The generated substrate voltage fluctuations couple to the sensitive nodes of a CP-

PLL integrated on the same substrate and affects its spectral performance. Fig. 2.20a

shows the potential noise coupling mechanisms in a charge-pump PLL. The voltage

fluctuations in the bulk terminals of the charge-pump, loop filter (large area) and

VCO transistors frequency modulate the VCO and affects the spectral performance

of PLL output signal.

The random noise component of the generated substrate noise increases the noise

floor in the frequency spectrum and phase noise characteristics of the PLL output

signal. While, the periodic noise component introduces spurious tones in the fre-

quency spectrum and phase noise characteristics of the PLL output signal as shown

in Fig. 2.20b. In time domain, the periodic substrate noise affects the peak-peak

deterministic jitter performance of the PLL output signal, with a summation of two

Gaussian distributions in its period measurement, reflecting a periodic disturbance

in the VCO operation.

In transmitter applications, these spurious tones form in-band or out-of-band in-

terference signals depending upon the frequency of periodic switching noise. The

digital circuits in a sensor node (ADCs and micro-controller) typically operate using

low frequency clock signals in the frequency range of a few MHz to reduce the power

consumption of the sensor nodes. Thus increasing the sources of in-band interference

signals.

The increased sensor node density and the high levels of integration on the same

chip challenges the spectral performance of the frequency synthesizer circuits and


Vdd

VCO

PA

Rz

Cz

Cp

Iup

Idn

UP

DN

PFDVctrlFref

Divider, N

Mico-controlleror DSPADC

Memory circuits

Large drivestrength

digital circuits

(a) Noise coupling mechanisms to a charge-pump PLL.

fRF

Spur level(dBc)

fRF - fnoise fRF + fnoise

Phas

e no

ise,

(dB

c/H

z)

Offset frequency, (Hz)frequency, (Hz)

Pow

er, (

dB)

loop BW fnoise 2*fnoise

Vol

tage

, (V

)

Time, (s)Pk-Pk deterministic

period jitter, (ps)

Frequency spectrum Phase noise characteristics Period jitter measurement

(b) Effects of periodic switching noise on the performance of a charge-pump PLL.

Figure 2.20: Mixed signal integration effects on the charge-PLL performance.

in-turn affects the transceiver performance in these applications.

Substrate noise mitigation techniques

Several techniques are presented in the literature to mitigate the substrate noise

coupling effects, and they can be classified under the following categories.

• Layout-based techniques - These are isolation structures fabricated in the sub-

strate itself to reduce the substrate noise effects by altering the propagation

mechanism. Some of the layout-based techniques reported are deep n-well iso-

lation [64], deep trench isolation, patterned ground shields [65], high-resistivity


substrates, triple well implementations, through-silicon-via-based physical iso-

lation [66], and guard-ring structures [27].

Circuit-based techniques - The circuit-based solutions modify the analog and

digital circuit implementations to reduce the substrate noise effects by alter-

ing the injection and reception mechanisms. The modification in analog part

includes fully differential circuit topologies with symmetrical matched layouts

to treat substrate noise as a common mode signal. Digital circuit implemen-

tations using analog-based differential current-steering techniques, such as the

folded source-coupled logic can be used to reduce the power-supply noise-current

spikes [67].

The substrate noise effects on analog circuits can be simulated by including a sub-

strate model along with the circuit net list. By analyzing the results, modifications

can be made either in circuit level or in layout level to improve the noise immunity

performance. However, the increased transistor count and very small minimum di-

mensions result in a huge substrate model, which makes it difficult to simulate within

a reasonable time.

A few works attempted to solve this problem through experimental demonstration

of substrate noise effects on sensitive analog circuits as a function of its circuit param-

eters and different isolation schemes, to provide guidelines to designers in designing

circuits with improved noise immunity [2] [28] [68] [69].

In this work, we experimentally demonstrate the effects of a periodic switching

noise generated from digital buffers (typically a clock distribution network) on the

performance of charge-pump PLL. The sensitivity of PLL performance metrics such

as output spur level, phase noise, and jitter are monitored against the variations in the

properties of a noise injector digital signal and a detailed discussion on the analysis

results are presented presented in Chapter 4.

Chapter 3

Reference Spur Suppression Technique

This chapter presents a charge-pump (CP) mismatch current calibration tech-

nique utilizing an adaptive body bias tuning of charge-pump transistors. The presented

technique compensates for the DC current mismatch and the mismatch due to channel

length modulation effect and hence improves the performance of CP-PLLs in nano-

meter CMOS implementations. For an automatic CP mismatch current calibration

with respect to the VCO control voltage, an auxiliary loop based calibration method is

used. A test chip was fabricated in UMC 0.13 µm CMOS process. The charge-pump

measurements show a minimized mismatch current of less than 0.55% over the VCO

control voltage range of 0.3 to 1 V, using the proposed technique. The closed loop

measurements show a minimized phase error of within ±70 ps and a ≃9 dB reduction

in reference spur level across the PLL output frequency range 2.4 - 2.5 GHz.

3.1 Introduction

The unwanted spurious tones generated at reference frequency (fref) offsets from the

target frequency (fout) in the frequency spectrum of PLL output signal are called

reference spurs [1]. Fig. 3.1 shows the block level desription of a charge-pump PLL

and the reference spurs in its output signal frequency spectrum. The reference spurs

are generated due to the periodic disturbances on VCO control voltage created by the

non-ideal effects in PLL implementation. The sources of reference spurs in a CP-PLL

are charge-pump mismatch current, loop filter leakage current, charge sharing from

CP switches, feed-through from PFD pulses, and the timing mismatch between PFD

output signals.

With the lower supply voltage operation and the severely deteriorated channel

37

3.1. Introduction 38

Rz

Cz

Cp

Vdd

Iup

Idn

Fout Fout+FrefFout-Fref

Referencespur (Pspur)

Res

et

Tpfd

Vdd

Vdd

UP

DN

Programmabledivider (N)

FoutFfb

Fref

Static phaseerror (Te)

Vctrl

PFD

CP

LPF

VCO

d

d

q

q

(dBc)

Figure 3.1: Conventional Type II, 3rd order Integer-N charge-pump PLL.

length modulation effect of nano-scaled CMOS process, the mismatch between charge-

pump currents (Iup & Idn) form a dominant source of static phase error between the

PFD input signals and the reference spurs in output signal frequency spectrum [19]

[56].

The static phase error (Te) and the reference spur level (Pspur) (using narrow-band

frequency modulation approximation) generated due to the charge-pump mismatch

current can be expressed as [20] [53],

Pspur, (dBc) = 20log[

Icp · Rz · Kvco · Tpfd√2

· ∆I

Icp

]

− 20log(

fref

fpl

)

(3.1)

Te = Tpfd · ∆i

Icp

(3.2)

where Tpfd is the PFD reset delay, ∆i is the CP mismatch current, Icp is the CP

output current, Rz is the resistor value in the loop filter, Kvco is the VCO gain, and

fpl is the frequency of pole in the loop filter given by Cz+Cp

2π·Rz·Cz ·Cp.

A typical CP mismatch current of ≃10% was reported in many charge-pump cir-

cuit designs [20] [54] [55] implemented in sub-micrometer CMOS process technologies.

Fig. 3.2 shows the reference spur level and static phase error dependence on the CP

3.2. Prior work 39

Figure 3.2: Simulation conditions : Icp = 100 µA, Kvco = 500 MHz/V, Rz = 28.18KΩ, Cz = 84.58 pF, Cp = 6.51 pF, and fref = 5 MHz.

mismatch current magnitudes upto 10%, calculated using Eqns. 3.1 & 3.2, respec-

tively. A zero PFD reset delay (Tpfd) will eliminate the reference spur and static

phase error issues in a charge-pump PLL as shown in Fig. 3.2. However, an appropri-

ately designed smaller Tpfd is necessary for a dead-zone free PFD operation [53] and

therefore the CP mismatch current should be minimized for an ideal PLL operation.

3.2 Prior work

Several techniques and methods has been presented in the literature to minimize the

reference spurs. These techniques can be classified under following categories,

Low VCO gain techniques - From Eqn. 3.1, a low VCO gain reduces the magni-

tude of reference spurs in the PLL output. VCO architectures with low gain (Kvco)

and wide frequency tuning range using switched capacitor banks [57] and dual path

control techniques [21] [58] [59] [60] are presented in the literature to minimize the

reference spurs. These techniques either require complex digital frequency calibra-

tion schemes [57] or suffer due to coarse-path leakage current and charge injection

issues [59].

Randomization techniques - Techniques to randomize the charge distribution

3.2. Prior work 40

mechanism to the loop filter are proposed in [22] [23] [50] [61] to minimize the mag-

nitude of reference spurs. However, the performance of these techniques are limited

due to the open loop generation of equal delays and also result in increased in-band

phase noise levels.

CP mismatch current reduction techniques - Several CP mismatch current cal-

ibration schemes are presented in the literature to reduce the pump current mis-

match [3] [54] [55] [62] [63].

A replica CP based mismatch current calibration scheme was presented in [3].

However, [3] calibrates the CPs under different control voltages and hence difficult to

compensate for the mismatch due to channel length modulation effect.

A digital mismatch current calibration (Fig. 3.3a) approach was presented in [19]

[54] [3]. However, the CP circuit implementations in these reported works consume a

larger current of 3∗Icp, which is not suitable for high output current (Icp) applications.

Charge-pump architectures with negative feedback using high gain OPAMPs (Fig.

3.3b) to minimize the mismatch current are presented in [55] [56] [62], but the non-

ideal effects of OPAMPs such as stability and offset voltage limits the performance

of charge-pump in these implementations.

Vdd

upb

down

Vdd

Vdd Vdd Vdd Vdd VddVdd

B0 B1 B2 B3

200 µA

180 µA

16 µA

8 µA

4 µA

2 µA

200 µA

Icp

CPoutput

upb

down

Vdd

(a) Digital calibration [3] [19] [54].

VddVdd

−+

Vdd

Selfbias

Vbp

Vbn

Iup

Idn

Icp

CPoutput

upb

dn

(b) Negative feedback [55].

Figure 3.3: Charge-pump mismatch current calibration techniques.

3.3. Current steering charge-pump circuit 41

Bulk-driven circuit techniques are highly useful in the design of ultra low voltage

analog circuits [70] [71] [72], to compensate for variation effects (PVT, die-to-die &

within-die), and to reduce the leakage power in digital circuits [73] [74]. In this

work, we present a charge-pump mismatch current calibration technique utilizing an

adaptive body bias tuning of its current source transistors which provide a very fine

resolution in the mismatch current calibration. An auxiliary loop based calibration

method was used for an automatic body bias tuning of charge-pump transistors with

respect to the VCO control voltage. The proposed technique compensates for the DC

current mismatch and the mismatch current due to channel length modulation effect

and hence improves the performance of CP-PLLs in the nano-scaled CMOS process

implementations.

3.3 Current steering charge-pump circuit−

+

Vdd

Iup

Icp Vctrl

Body bias(Vb)

Rz

Cz

Cp

LPF

Vdd

Vdd

Vdd

IdnM1M2 M3

M4

M5

M6M7

UPUPB

DNDNB

CP

Isource

10 uA

10 uA

1 : 1

1 : K

1 : K

IupIdn Iup

Idn

Vdd Vdd

VddUP

DN

CPCurrents

I I

Vdd

Vm

Te Tovlp

Vm

Te Tovlp

Tref

VCOcontrolvoltage(Vctrl)

(a) Charge-pump circuit (b) Transient waveforms

Figure 3.4: Current steering charge-pump circuit and its transient wave-forms (Iup <Idn).

The current steering charge-pump circuit used in the PLL is shown in Fig. 3.4a.

M7 and M3 are the up and down current source transistors in the charge-pump

respectively and their saturation currents can be expressed as,

Iup =1

2µpCox,p

(

W

L

)

p

(Vgs,p − VT,p)2(1 + λVds,p) (3.3)


Figure 3.5: Measured charge-pump output current characteristics (L = 3 µm).

Idn =1

2µnCox,n

(

W

L

)

n

(Vgs,n − VT,n)2(1 + λVds,n) (3.4)

Fig. 3.5 shows the measured output current characteristics of the CP. As the

CP output voltage (Vctrl or VCO control voltage) increases, Vds,n increases and Vds,p

decreases, and hence Idn (NMOS current) increases and Iup (PMOS current) decreases

due to the channel length modulation effect. Therefore, the CP currents Iup & Idn

are matched only for a single voltage point (zero mismatch current point) and the

mismatch current (Iup − Idn = ∆I 6= 0) exists for all other control voltages. This

mismatch between charge-pump currents Iup & Idn create ripple on VCO control

voltage at a reference frequency as shown in Fig. 3.4b.

3.3.1 Proposed CP mismatch current calibration technique

The threshold voltage of a PMOS transistor (M7 in Fig. 3.4a) is given by,

VT,p = VT 0,p + γ(√

φ + Vbs,p −√

φ) (3.5)

In a conventional CP case, the body terminal of PMOS transistor is usually con-

nected to the supply voltage (Vb = Vs = Vdd) and its threshold voltage is equal to

VT 0,p. Forward body biasing of PMOS transistor (M7) with Vb < Vdd, reduces its


threshold voltage (VT,p < VT 0,p) and hence, increases the magnitude of UP current

(Iup) as shown in Fig. 3.6.

Vdd

+

−

Vb

G

D

S

Figure 3.6: Simulated ID, VT dependence on body voltage (V b) of PMOS transistor(W = 30 µm, L = 3 µm).

Figure 3.7: Measured CP output current characteristics, (L = 3 µm) with the PMOStransistor body voltage varied between 1.3 V and 1.2 V (4 bit control, Iup < Idn).

Fig. 3.7 shows the measured output current characteristics of the charge-pump

circuit (Fig. 3.4a). In this design, the CP currents Iup & Idn are matched for a lower

VCO control voltage to emulate the Iup < Idn mismatch current scenario, when Vb =

Vs = Vdd. Forward body biasing of UP current source transistor increases the PMOS

current (Iup) and shifts the zero mismatch current point to a higher VCO control

voltage as shown in Fig. 3.7. Therefore, by adaptively adjusting the body bias voltage

of PMOS current source transistors with respect to VCO control voltage, the zero

mismatch current point can be shifted to all VCO control voltages as demonstrated in


Fig. 3.7. Thus minimizing the mismatch between CP currents Iup and Idn generated

due to the channel length modulation effect.

Figure 3.8: Measured CP mismatch current characteristics, with the PMOS transistorbody voltage varied between 1.3 V and 1.2 V (4 bit control, (Idn − Iup).

Fig. 3.8 shows the CP mismatch current characteristics (∆I = Idn−Iup) measured

across the VCO control voltage range 0.3 to 1 V. Measurements show a CP mismatch

current of less than 0.3 µA (0.55%) and 5 µA (9.1%, shown in Fig. 3.5), with the

body bias tuning enabled and disabled respectively. The body bias voltage of PMOS

transistor is varied between 1.3 to 1.2 V using LSB 4-bits of an 8-bit capacitive DAC

(output voltage range = 0 to Vdd), with the MSB 4-bits connected to supply voltage.

The mismatch current can be further reduced by having a very fine resolution DAC

in the body bias tuning at the cost of increased settling time of the PLL (discussed

in detail in Section 3.4).

Table 3.1: Charge-pump performance summary and comparison.This work [56] [55] [75]

Calibration Body bias Gain -ve -vetechnique tuning boosting feedback feedbackIcp, (µA) 55 600 100 200

∆Imax, (µA) 0.3 0.8 3.2 2Mismatch current, (%) 0.55 0.15 3.2 1

VCO control voltage, (V) 0.3 to 1 0.5 to 1.2 0.2 to 1 0.15 to 0.85

Table 3.1 summarizes the matching performance of charge-pump currents and

its comparison with other works. The obtained matching performance between the

3.4. Zero CP Mismatch Current Tracking PLL Architecture 45

−

+

VddVdd

PFDVCO


Iref

Iref

Rz

Cz

Cp

UP

UPB

DN

DNB

VCO Control Voltage

LOCKDetector

Phase ErrorMonitor

Fout

Enable

Iup

Idn

DIV_OUT

D[3:0]

(Body bias)

1/164 bit SARController

CLKDAC

Ffb

Fref

Lead/ Lag

CP LPF

Zero CP Mismatch Current Tracking Loop

Vdd Vdd Vdd

B5 B1 B0

PVT calibration controlVb

Error correction bits

A

Fref

800 MHz

2.4 GHzEC+

Figure 3.9: Zero charge-pump mismatch current tracking PLL architecture.

CP currents with a mismatch current of less than 0.55% is comparable with the

reported works in the literature and the presented calibration technique will be useful

in minimizing the channel length modulation effects on CP-PLL performance.

3.4 Zero CP Mismatch Current Tracking PLL Architecture

The PLL architecture with the charge-pump mismatch current reduction loop is

shown in Fig. 3.9. For an automatic charge-pump mismatch current calibration with

respect to the VCO control voltage, we have used an auxiliary loop based calibration

method [54] [21] [23] [3]. The mismatch current reduction loop monitors the polarity

of static phase error between the reference and feedback signals and calibrates the CP

mismatch current by adjusting the body bias voltage of UP current source transistor.

The auxiliary mismatch current reduction loop consists of a phase error monitor,

lock detector, 4-bit successive approximation register (SAR) controlled logic and a

digital to analog converter (DAC).


• The lock detector enables the mismatch current reduction loop and is imple-

mented using standard digital logic circuits [58] - [50].

• The phase error monitor outputs the lead/lag status of the reference signal over

the feedback signal and is implemented using a conventional D-type flip-flop

based symmetric bang-bang phase detector [76].

• The SAR controller is implemented using conventional digital logic circuits [77]

and the DAC uses a charge-sharing capacitive DAC architecture [78]. The SAR

controller along with the DAC performs body bias tuning based on the lead/lag

status output of the phase detector.

The PLL operates in three modes, 1. initial coarse locking mode, 2. zero CP

mismatch current tracking mode, and 3. steady state mode. The step response of

VCO control voltage explaining the different modes of operation of PLL is shown in

Fig. 3.10. In this design, the charge pump currents are matched for a lower VCO

control voltage (point C in Fig. 3.11) and for higher voltages Iup is less than Idn.

Figure 3.10: Simulated step response of VCO control voltage (2.4 to 2.5 GHz).

Coarse locking mode : In this mode, the PLL operates in its conventional closed

loop architecture and tries to acquire lock to an output frequency set by the reference

signal (Fref) and the divider value (in the case of Fig. 3.10, Fout = 2.5 GHz & Fref =

1 MHz). The lock detector output is low with the SAR controller digital bits set to


Figure 3.11: Charge-pump output current characteristics : SAR algorithm.

high ("1111") and the DAC output controlling the PMOS current source transistor’s

body voltage is held at Vdd (1.3 V).

For a VCO control voltage of 0.912 V (Fout = 2.5 GHz), the charge-pump currents

are Iup = 52.44 µA and Idn = 56.12 µA (points A & B in Fig. 3.11 respectively).

This mismatch between the CP currents create ripple on VCO control voltage and

frequency modulates the VCO output signal.

Zero CP mismatch current tracking mode : The lock detector enables the mis-

match current reduction loop on the detection of phase lock between the reference and

feedback signals. Initially, the reference signal leads the feedback signal (Iup < Idn,

Vb = 1.3 V) and the phase error is positive. A calibration clock generated by di-

viding down the reference signal is used to trigger the 4 bit-SAR controller. The

charge-pump current characteristics demonstrating the SAR controller operation in

minimizing the mismatch between Iup & Idn is shown in Fig. 3.11 and is explained

as follows,

Transition 1 : On the 1st rising edge of the calibration clock, SAR controller

calibrates its MSB ("1111" to "0111") and forward body biases the UP current source

transistor (Vb = 1.25 V in Fig. 3.13) to increase the magnitude of its output current,

shifting the zero mismatch current point to a higher VCO control voltage.

Transition 2 : On the 2nd clock rising edge, the charge-pump current Iup is less

than Idn, phase error is positive and the SAR controller adjusts its output bits from


"0111" to "0011" to further increase the magnitude of Iup (Vb = 1.225 V).

Transition 3 : On the 3rd rising transition of calibration clock, Iup > Idn with a

negative phase error and the SAR controller reduces the magnitude of forward body

biasing of PMOS transistor to reduce the magnitude of UP current ("0011" to "0101"

& Vb = 1.2375 V).

Transition 4 : On the 4th clock rising edge, Iup < Idn and the phase error is

positive. The SAR controller calibrates its LSB ("0101" to "0100" & Vb = 1.23125 V)

increasing the magnitude of UP current.

Figure 3.12: VCO control voltage in the zero CP mismatch current tracking mode.

Figure 3.13: SAR controller working : PMOS bulk voltage and CP mismatch current.

At the end of nth calibration cycle of a n-bit SAR controller, the current points

A, B & C in Fig. 3.11 almost coincide with each other, minimizing the charge-pump

mismatch current and the magnitude of ripple on the VCO control voltage. This is a

simple first order loop operation and the auxiliary loop added forms an uncondition-

ally stable system. Fig. 3.12 & 3.13 shows the effect of SAR controller operation on


the VCO control voltage and PMOS transistor body voltage (Vb), respectively, during

the zero charge-pump mismatch current tracking mode operation of PLL.

Steady state mode : After n cycles of mismatch current calibration (for a n-bit

SAR controller, in this design n = 4), PLL operates in its steady state mode with

the SAR controller and DAC holding the optimized body voltage for a minimum CP

mismatch current condition. The magnitude of CP mismatch current & pk-pk ripple

on VCO control voltage in this mode are 0.013 µA & 0.6 mV and 3.68 µA & 5.9 mV

with the mismatch current reduction loop enabled and disabled respectively as shown

in Fig. 3.12 & 3.13.

Simulation results : To demonstrate the effect of proposed CP mismatch current

calibration technique on the PLL performance, a PLL architecture shown in Fig. 3.9

is simulated using the parameter values listed in Fig. 3.14. The static phase error

and reference spur levels simulated across the PLL output frequency range 2.4 to 2.5

GHz, for a Tpfd of 5 ns is shown in Fig. 3.14. In this simulation, the PFD reset delay

is assumed larger than the optimum value to emulate the experimental conditions

used in the implementation (described in section 3.5).

The simulated static phase error and reference spur levels observed at 2.5 GHz

output frequency are 423 ps & -66.46 dBc and 9.3 ps & -86.8 dBc, with the mismatch

current reduction loop disabled and enabled respectively. Thus demonstrating the

efficiency of proposed technique in improving the reference spur and static phase

error performance of a CP-PLL. The results can be further improved by having an

optimum reset delay in the PFD design.

The overall settling time of the synthesizer is less than 120 reference clock cycles

for a 100 MHz frequency step (2.4 to 2.5 GHz shown in Fig. 3.10) and it can be

further improved by increasing the frequency at which the mismatch current reduction

loop operates or by increasing the loop bandwidth of PLL. The digital nature of the

auxiliary loop, its reduced frequency of operation (fref/16), and relaxed speed, noise,

and matching performance requirements of DAC, makes the additional noise and


(a) Static phase error.

(b) Reference spur.

Figure 3.14: Simulation conditions : Icp = 100 µA, Kvco = 300 MHz/V, Rz = 28.18KΩ, Cz = 84.58 pF, Cp = 6.51 pF, fref = 5 MHz, and Tpfd = 5 ns.

power consumption from the mismatch current reduction loop negligible.

In the steady state mode of frequency synthesizer, the capacitive DAC (Fig.3.15a)

holds the optimum body voltage for the minimum CP mismatch current condition

and therefore its output decay voltage must be kept within an LSB step. Simulations

show a worst case DAC decay voltage of 1.32 mV over a 50 ms time duration (FF,

100oC) which is much less than the unit step voltage used in this implementation.

In frequency hopping wireless applications where the frequency is reset more often,

3.5. Experimental Setup and Measurements 51

−

+

Vdd

RESET

CC21C22C2(n-1)C

B0B1B2Bn-1

VoutVoffset

(a) Capacitive DAC.

Vdd

−

+

R R R

2R 2R 2R 2R

2R

RB0B1B2Bn-1

Vout

(b) R-2R DAC

Figure 3.15: DAC architectures.

this is not an issue. However, for other applications, DAC architectures immune to

leakage such as R-2R DAC (Fig.3.15b)can used [79].

3.5 Experimental Setup and Measurements

A chip prototype containing an integer-N charge-pump PLL with the CP mismatch

current reduction loop was fabricated in a UMC 0.13 µm Mixed-Mode and RF CMOS

1.2V/3.3V 1P8M process. The buffer A in Fig. 3.9 was not integrated on-chip and

as a result, the bulk leakage current disrupted the normal operation of the capacitive

DAC present on-chip. Consequently, we have implemented the CP mismatch current

reduction loop (enclosed by dashed lines in Fig. 3.9) off-chip to demonstrate the

proposed concept. Fig. 3.16 shows the die photograph of the PLL chip and the

experimental setup used.

3.5.1 Frequency synthesizer

The type-II, 3rd order integer-N charge-pump PLL used in the experiment is shown in

Fig. 3.9. The PLL does frequency synthesis at a lower operating frequency of 800 MHz

to reduce the power consumption from its VCO & divider circuits [80] [32] [33] [34]. A

digital logic gate based edge combiner generates the 2.4 GHz RF carrier by combining

the output signals from different stages of a ring oscillator VCO used in the PLL


(a) Chip layout. (b) Die photo.

(c) Experimental setup.

Figure 3.16: Die photograph of the fabricated test chip in 0.13 µm CMOS processand the experimental setup used to demonstrate the proposed concept.

(discussed in Chapter 5). The reference signal frequency was chosen as 1.667 MHz,

so that the channel spacing in the up-converted 2.4 GHz frequency band is 5 MHz

(for Zig-bee applications).

The phase frequency detector (PFD) and divider are implemented using standard

digital logic circuits with tri-state dead zone free phase detector and down counter

architectures respectively. The current steering charge-pump circuit with adaptive

body bias tuning shown in Fig. 3.4a was designed to source or sink programmable

currents in the range of 3 µA to 100 µA from a reference current source of 10 µA.


Figure 3.17: Measured VCO transfer characteristics (VCO + EC output, PVT cali-bration bits, B5 to B0).

The loop filter parameters are Rz = 60 kΩ, Cz = 200 pF, Cp = 15.2 pF designed for

a PLL loop bandwidth of 100 KHz and phase margin 60o. The Loop filter capacitors

are implemented using the gate capacitance of NMOS transistors to reduce the area

occupied by large capacitors on-chip.

Figure 3.18: Measured phase noise characteristics of 2.4 GHz signal.

A pseudo differential voltage controlled ring oscillator (VCO) with varactor and

bias current tuning is used in the PLL. The VCO and edge combiner covers an

operating frequency range of 2.35 to 2.55 GHz and the measured VCO transfer char-

acteristics for various PVT calibration settings (B5 to B0) are shown in Fig. 3.17.

The frequency synthesizer achieves a phase noise of -96.01 dBc/Hz at 1 MHz offset

from a 2.4 GHz RF carrier consuming 8.2 mA current from a 1.3 V supply volt-

age. Fig. 3.18 shows the measured phase noise characteristics of the 2.4 GHz signal

generated from the frequency synthesizer. The measured phase noise performance is


comparable to the other ring oscillator based frequency synthesizer implementations

reported in [33] [49] and can be improved further by burning additional power in the

ring oscillator.

3.5.2 Zero charge-pump mismatch current tracking loop

The designed frequency synthesizer chip have test points that bring out the PFD

input signals (Fref & Ffb) and the CP PMOS transistor body terminal to the chip

package pins, and the zero CP mismatch current tracking loop is implemented off-

chip to demonstrate the working of the proposed concept. The digital circuits in the

mismatch current reduction loop are implemented in the FPGA using conventional

circuit techniques and the DAC is implemented from a digitally controlled variable

resistor chip AD8304. Fig. 3.16c shows the experimental setup used in the demon-

stration.

In this implementation, the non-ideal effects such as undesired coupling through

substrate, supply voltage, and other parasitic interactions also contributed to the

reference spurs [20] [54] [81]. Therefore, we have used a larger PFD reset delay in the

implementation to sense smaller CP mismatch currents through static phase error

measured off-chip and to observe the effects of CP mismatch current on the reference

spur performance of PLL over the other non-ideal effects.

The measured charge-pump output current characteristics and the effect of body

biasing in minimizing the CP mismatch current are shown in Fig. 3.7 & 3.8 re-

spectively. The corresponding measured transient response of reference and feedback

signals, with the PLL operating in its steady state mode are shown in Fig. 3.19.

• In this implementation, the CP mismatch current and the PLL output frequency

increases with the VCO control voltage (Fig. 3.8 & Fig. 3.17). Hence the static

phase error between the reference and feedback signals also increase with the

PLL output frequency as shown in Fig. 3.19a.


(a) Varying PLL output frequency.

(b) Varying PMOS UP current source transistor bodyvoltage.

Figure 3.19: Measured reference and feedback signals with the PLL operating in itssteady state mode.

• Forward body biasing of PMOS transistor reduces the CP mismatch current

and hence the static phase error also reduces as demonstrated in Fig. 3.19b.

At the zero mismatch current point where Iup = Idn, the static phase error

reaches ≃ 0 ps. Beyond this body voltage, Iup becomes greater than Idn with

the reference signal lagging behind the feedback signal as shown in Fig. 3.19b.

Fig. 3.20a shows the measured static phase error between the PFD input signals

(Fout = 2.4 GHz) with the mismatch current reduction loop disabled (2.215 ns) and

enabled (41.09 ps). The corresponding measured PLL output frequency spectrum of

2.4 GHz signal with the reference spur levels -22.42 dBc (loop disabled) and -31.47

3.5

.E

xp

erim

enta

lSet

up

and

Mea

sure

men

ts56

Table 3.2: Performance summary and Comparison.[54] [59] [63] [72] [22] This work a

Process, (µm) 0.18 0.25 0.09 0.065 0.18 0.13Supply voltage, (V ) 1.8 2.5 1 0.4 1.8 1.3

Output frequency, (GHz) 5.2 4.5 0.8 0.35 2.4 2.4Reference frequency, (MHz) 10 4 100 21.875 1 1.667

Loop Bandwidth, (KHz) 200 90 - - - 100Power consumption, (mW ) 19.8 117.5 15 0.109 18 10.7

Phase noise, -110 -87 -112 -90 -110 -96.01(dBc/Hz) @ 1 MHz @ 1 MHz @ 0.2 MHz @ 1 MHz @ 1 MHz @ 1 MHz

Reference spur, (dBc) -68.5 -45 -48 -55.3 -55 -31.47 b

Static phase error, (ps) - - < ± 40 - - < ± 70 c

Area, (mm2) 0.64 - 0.048 0.0081 0.9 0.31aMismatch current reduction loop implemented off-chipbThe reference spurs are large due to undesired parasitic coupling through substrate and supply in this implementation

A ≃9 dB reduction in spur level was demonstrated with the CP mismatch current calibration.cLimited due to the use of large PFD reset delay


Loop disabled Loop enabled

(a) Transient response - reference and feedback signals.

Loop disabled Loop enabled

(b) Frequency spectrum (2.4 GHz)

Figure 3.20: Measured static phase error and reference spur with the CP mismatchcurrent reduction loop disabled and enabled (Fout = 2.4 GHz, Fref = 1.667 MHz).

(a) Static phase error. (b) Reference spur level.

Figure 3.21: Measurements across PLL operating frequency range 2.4 - 2.5 GHz.

3.6. Summary 58

dBc (loop enabled) are shown in Fig. 3.20b. The measured spur levels are large due

to the undesired parasitic coupling from reference and feedback signal buffers to the

sensitive nodes of PLL through substrate, supply and other non-ideal effects. Similar

undesired parasitical effects resulting in large spurious tones are also been reported

in the literature [81] [82]. The static phase error and reference spur levels measured

across the synthesizer output frequency range 2.4 - 2.5 GHz are shown in Fig. 3.21a

& b respectively. Table 3.2 presents the summary of measured performance from the

frequency synthesizer and its comparison with other designs.

3.6 Summary

A charge-pump mismatch current calibration technique using an adaptive body bias

tuning of PMOS transistors in the CP was demonstrated. The proposed technique

compensates for the DC current mismatch and the mismatch due to channel length

modulation effect in the charge-pump.

Chip prototype of a 2.4 GHz, integer-N charge-pump PLL with the proposed

technique was fabricated in 0.13 µm CMOS process. Measurements show an improved

matching characteristics between charge-pump currents with a maximum mismatch

current of less than 0.3 µA (0.55 %)over the VCO control voltage range of 0.3 to 1 V.

A zero CP mismatch current tracking loop was implemented off-chip for an au-

tomatic mismatch current calibration with respect to VCO control voltage and to

improve the PLL performance. The closed loop measurements using the proposed

technique show a ≃9 dB improvement in the reference spur performance and a static

phase error of within ±70 ps across the PLL output frequency range 2.4 - 2.5 GHz.

The presented body bias based mismatch current calibration technique is useful

in improving the performance of charge-pump circuits implemented in nano-meter

CMOS process technologies and hence improves the static phase error and reference

spur performance of CP-PLLs in these implementations.

Chapter 4

Substrate noise effects

In this chapter, we experimentally demonstrate the effects of periodic switch-

ing noise generated from digital buffers (typically a clock distribution network) on

the performance of charge-pump PLLs. A chip prototype of 500 MHz CP-PLL was

designed and implemented in 0.13 µm CMOS process technology. The source and

mechanism of noise coupling are explained through various experimental techniques

performed on-chip. The sensitivity of PLL performance metrics such as output spur

level, phase noise, and jitter are monitored against the variations in the properties of

a noise injector signal and a detailed discussion on the analysis results are presented.

4.1 Introduction

The need for more functionality in systems-on-a-chip (SoC) drives the integration

of analog (PLL, LNA, and voltage reference reference circuits) and digital (Micro-

controllers, and ADC’s) circuits on the same die. The increased levels of mixed

signal integration has led to dramatic improvements in the performance of these

systems and enabled a host of new applications [25] [28]. However, the design of

mixed-signal systems-on-a-chip faces a great number of challenges. One of the most

severe challenges is from the performance degradation of analog circuits due to the

parasitic interactions between the digital and analog sub-systems integrated on the

same chip [24] [25].

The digital circuits inject noise currents into the substrate during their signal

transitions. The substrate is a conductive medium and allows the injected noise

currents to propagate from the digital circuits to the analog circuits integrated on the

same substrate. The analog/RF circuits are sensitive to the voltage fluctuations in

59


n+ p+ p+

Lb

Rb

n- well

Digital Vdd

n+n+

Lb

Rb

IN

OUT

Ivdd Ivdd

p+ n+ n+p+

Lb

Rb

Digital gnd Analog gnd

G

S D

P - substrate

h+ e+

noise propagates

Noise injection Noise reception

Inverter cross section Transistor cross section

Figure 4.1: Substrate noise - injection, propagation and reception mechanisms.

the substrate and hence the coupled noise degrades its performance.

Fig. 4.1 shows the various noise mechanisms (injection, propagation, and recep-

tion) in a mixed signal integrated circuit. The inverter cross section on the right

represents the digital circuits and the NMOS transistor cross section on the left rep-

resents the analog circuits.

4.1.1 Noise injection

The signal transitions in digital circuits inject noise currents into the substrate pri-

marily through the following three paths,

1. coupling through parasitic capacitances (bond pad to substrate capacitance

(picofarad range) [25], transistor source and drain depletion capacitances, and

interconnect to substrate capacitances),

2. through substrate contacts (voltage ringing in power supply lines couple to

substrate),

3. impact ionization currents (electron-hole pairs generated due to high electric

fields in the depleted drain end of the transistor).

In Fig. 4.1, an inverter cross section is used to emulate the digital portion of the

chip. In an actual SoC implementation, the substrate noise is generated from complex


digital logic circuits like microprocessors, and ADC’s. The generated substrate noise

from digital circuits has two components, 1. random noise component (generated

from random digital logic activity) and 2. periodic noise component (generated from

clock grid and other periodic logic activity). Digital buffers in a clock distribution

network usually have very large drive strengths and hence inject a significant amount

of noise currents into the substrate [26].

Fig. 4.2 shows a typical clock distribution network using a multi-level tree archi-

tecture [29] [30]. The fast edge rate requirement from the final stage clock buffers

such as local clock buffers and the second level clock buffers in Fig. 4.2 makes them

a dominant source of substrate noise injection.

LoadLCB

LoadLCB

LoadLCB

SLCB

SLCB

LoadLCBSLCB

LoadLCB

LoadLCBSLCB

ClockSource

MasterDriver

PrimaryDriver Repeater Second

Level ClockBuffer

LocalClockBuffer

Figure 4.2: Clock distribution network using a multilevel tree architecture used insynchronous digital systems.

4.1.2 Noise propagation

The silicon substrate is a semiconducting material and is modeled as a resistive and

capacitive mesh [27]. The model for a substrate and the propagation of noise through

it depends on the type of the substrate used. Fig. 4.3 shows the cross section view

of different types of substrates used in CMOS IC’s : epitaxial, non-epitaxial, and

silicon-on-insulator (SOI) [25] [83].


n+ p+ p+

n- well

n+ n+ p+

p- epi-layer (15 Ωcm)

p+ bulk-layer (0.05 Ωcm)

d1

d2 >> d1

(a) Epi wafer

n+ p+ p+

n- well

n+ n+ p+

p- bulk-layer (10-15 Ωcm)d

(b) Non-epi wafer

n+ p+ p+ n+ n+ p+

p- bulk-layer (10-15 Ωcm)

d1

d2 >> d1

Buried Oxide

(c) SOI wafer

Figure 4.3: Types of substrate used in CMOS IC’s.

Epitaxial wafers - Epitaxial wafers consist of a lightly doped (high resistivity) thin

layer atop a heavily-doped (low resistivity) bulk to prevent latch-up. Because of the

low resistivity bulk, most of the injected noise propagates in the low resistivity region

and the substrate can be modeled as a single node [27] (not good for mixed signal

integration).

Non-epitaxial wafers - The noise current flow is uniform through the substrate

and the isolation between analog and digital circuits improves with the distance of

separation between them.

SOI wafers - In this type of wafers, devices are built in thin silicon islands sep-

arated from the substrate by a buried oxide layer. Therefore, there is no DC path

between the silicon islands and exhibits an excellent isolation at low GHz frequen-

cies [84].

4.1.3 Noise reception

The injected noise currents in the substrate couple to sensitive nodes of analog circuits

through following paths,

• coupling through transistor parasitic capacitance,

• coupling through transistor substrate contacts,

• backgate effects - noise in the bulk terminal modulates the transistor threshold

4.2. Techniques to reduce substrate noise effects 63

voltage.

VT = VT 0 +

√2qǫsNA

Cox

(

√

|2φf | + VSB −√

|2φf |)

(4.1)

The coupled noise affects the operation of sensitive analog circuits (oscillators,

PLLs, LNA) and degrades the system performance [2] [28] [65] [85].

4.2 Techniques to reduce substrate noise effects

Several techniques are presented in the literature to understand and mitigate the sub-

strate noise coupling effects, and they can be classified under the following categories.

Layout-based techniques - These are isolation structures fabricated in the sub-

strate itself to reduce the substrate noise effects by altering the propagation mech-

anism. Some of the layout-based techniques reported are deep n-well isolation [64],

deep trench isolation, patterned ground shields [65], high-resistivity substrates, triple

well implementations, through-silicon-via-based physical isolation [66], and guard-

ring structures [27]. Many of these layout-based techniques require additional process

steps, and in some cases, they may alter the performance of the circuits enclosed.

The most common technique used by designers is the guard-ring structures (ohmic

and well type, single and double guard rings) around the sensitive blocks and noisy

circuits. However, the isolation provided by the guard-ring structures are limited

and begin to saturate when the width of the rings are increased, and also occupies

a large area [86]. Hence, with the increasing substrate noise trend [26], using wider

guard-ring structures alone is not an efficient solution as the isolation provided by

them is limited [25] [65] and begins to saturate for wider ring widths [86].

Circuit-based techniques - The circuit-based solutions does modifications to ana-

log and digital circuit implementations to reduce the substrate noise effects by altering

the injection and reception mechanisms. The modification in analog part includes

4.3. PLL design details 64

fully differential circuit topologies with symmetrical matched layouts to treat sub-

strate noise as a common mode signal. Digital circuit implementations using analog-

based differential current-steering techniques, such as the folded source-coupled logic

can be used to reduce the power-supply noise-current spikes [67]. Both techniques

require additional area and might not be practical for all applications.

Experimental demonstrations - The substrate noise effects on analog circuits can

be simulated by including a substrate model along with the circuit net list. And by

analyzing the results, modifications can be made either in circuit level or in layout

level to improve the circuit performance. However, the increased transistor count

and very small minimum dimensions result in a huge substrate model, which makes

it difficult to simulate within a reasonable time.

A few works attempted to solve this problem through experimental demonstration

of substrate noise effects on sensitive analog circuits as a function of its circuit param-

eters and different isolation schemes to provide guidelines to designers in designing

circuits with improved noise immunity [2] [28] [68] [69].

In this chapter, we experimentally demonstrate the effects of a periodic switching

noise generated from digital buffers (in the clock distribution network) on the perfor-

mance of a charge-pump PLL. A chip prototype of 500 MHz CP-PLL was designed

and implemented in 0.13 µm CMOS process technology. The source and mechanism

of noise coupling are explained through various experimental techniques performed

on-chip. The sensitivity of PLL performance metrics such as output spur level, phase

noise, and jitter are monitored against the variations in the properties of a noise

injector signal and a detailed discussion on the analysis results are presented.

4.3 PLL design details

A type II, 3rd order integer-N charge-pump (CP) PLL shown in Fig. 4.4 was im-

plemented in the United Microelectronics Corporation 0.13 µm mixed mode and the

4.3. PLL design details 65

−

+

VddVdd

PFD

VCOIref

Iref

Rz

Cz

Cp

UP

UPB

DN

DNB

VCO Control Voltage

fout

Iup

Idn

DIV_OUT

ffb

fref

+

- +

-

C1

+

- +

-

C2

+

- +

-

C3

+

- +

-

C4

+

- +

-

C5

CP

LPF

DIVIDER

+

+

-

-

VCO Control Voltage

VCO Unit Cell

Cvar

Cvar

Vdd

PBias Wp

Figure 4.4: Type II, 3rd order integer-N charge-pump PLL.

1.2/3.3-V 1P8M RF CMOS process. Fig. 4.6 a&b shows the designed chip layout

and the corresponding die photograph. The PLL generates an output frequency of

500 MHz from a 1 MHz reference signal (can be frequency multiplied by 5 to generate

a 2.5 GHz RF signal, discussed in Chapter 5). The phase frequency detector (PFD)

and divider circuits are implemented using the standard tri-state dead zone free phase

detector and down counter architectures respectively.

A current steering charge-pump circuit is used in the PLL and is designed to source

or sink programmable currents in the range 3 µA to 100 µA from a reference current

source of 10 µA. The loop filter parameters are Rz = 60 kΩ, Cz = 200 pF, and Cp =

15.2 pF and these are designed for a PLL loop bandwidth of 100 KHz and phase

margin of 60o. The loop filter capacitors are implemented using gate capacitance of

NMOS transistors to reduce the area occupied by large capacitors on-chip.

A five-stage pseudo-differential voltage-controlled ring oscillator (VCO) with var-

actor and bias-current tuning is used in the PLL, and it generates frequencies in the

range 455 to 536 MHz, achieving a gain of 72 MHz/V. Fig. 4.5 shows the measured

VCO transfer characteristics for different bias-current transistor widths.

4.4. Experimental setup 66

Figure 4.5: Measured VCO transfer characteristics for different bias-current transistorwidths Wp.

The PLL consumes a current of 4 mA (including output buffers) from a supply

voltage of 1.2 V and achieves a phase noise of -104.5 dBc/Hz at an offset of 1 MHz

from a 500 MHz carrier. Fig. 4.7b shows the measured phase noise characteristics of

a 500 MHz signal generated by the PLL.

4.4 Experimental setup

The reported works in the literature use the following techniques to inject noise

currents in the substrate to analyze its impact on circuit performance,

• n+ diffusion regions (15 µm X 15 µm) are used to inject noise in the substrate

simulating the drain of a transistor [27] [28].

• Digital buffers (inverter chains) are used to generate substrate noise with an

externally applied noise injector signal [2] [27] [68] [87].

In our implementation, the digital switching noise is generated from a chain of

large sized digital buffers (emulating clock buffers) shown in Fig. 4.6c that have

no guard rings around them. These buffers inject noise into the substrate through

their parasitic capacitances to substrate during their signal transitions. Therefore,

4.4. Experimental setup 67


unit cell

Ln = Lp = 120 nm

Wp = 2.5 µm

Wn = 1.0 µm

1x 4x 1x 4x 1x 8x

Buffer 1

Buffer 1 Buffer 1 Buffer 1

16x 64x 160x

Buffer 1 Buffer 1 Buffer 1 Buffer 1 Buffer 1

(c) Digital noise injector buffers.

Figure 4.6: Chip layout and die photograph showing the noise injector buffers (1,2,3).

a periodic signal given as input to these noise injector buffers generate a periodic

voltage fluctuation in the substrate.

To minimize the noise contribution through supply lines, separate analog and

digital power supplies with large decoupling capacitors are used and furthermore,

all PLL blocks have localized decoupling capacitors in their design. Vdd and ground

(GND) connections have five dedicated package pins each to reduce the voltage drop

over bond wire inductance (≃300 pH) [27]. External decoupling capacitors are also

used to maintain the off-chip Vdd to the GND voltage constant.

The PLL blocks (PFD, CP, VCO, divider, and LPF) and the decoupling capacitors

have p+ and n-well guard rings with the width of 20 µm around each [86]. However,

there is no dedicated bias pins used for biasing the guard rings and hence, the isolation

provided by them will be less [68].

4.5. Periodic switching noise effects on PLL performance 68

(a) Frequency spectrum (spurious tones at 5 MHz offset).

(b) Phase noise characteristics. (c) Jitter performance.

Figure 4.7: Measured result : Impact of 5 MHz periodic substrate noise generatedfrom digital buffers on the PLL performance.

4.5 Periodic switching noise effects on PLL performance

The injected periodic noise in the substrate couple to the sensitive nodes of PLL/VCO

and affects its operation with a worsened jitter and spectral performance. Fig. 4.7

shows the impact of a 5 MHz periodic substrate noise on the PLL performance.

The periodic noise near the reference frequency couple to the PLL blocks (PFD,

CP, LPF, and frequency divider) generating a beat tone which frequency modulates

the VCO [2]. The frequency modulation of VCO result in spurious tones at injected

frequency offsets from the VCO output frequency in its frequency spectrum as shown

in Fig. 4.7a. The noise injected near reference frequency has stronger effect than

4.5. Periodic switching noise effects on PLL performance 69

the noise injected near VCO frequency, because of the amplification provided by

the division ratio for noise near reference frequency [2] [88]. Therefore, we have

performed our experiments upto a periodic noise frequency of 100 MHz, targeting the

noise around reference frequency.

In noise injection experiments, the frequency of spurious tones generated (at offset

from carrier shown in Fig. 4.7a) tracks the injected noise frequency and the magnitude

of spurs in the PLL output spectrum are used to measure the sensitivity of PLL to

the periodic substrate noise. The spur level in the PLL output spectrum is defined

by,

Spur level, (dBc) = 10 · log(

Pspur

Pcarrier

)

(4.2)

where Pspur and Pcarrier are the power at spur and carrier frequencies respectively.

The measured spur level in the PLL output signal spectrum (500 MHz) with a 5 MHz

periodic noise injected into the substrate is -25 dBc (Fig. 4.7a).

Fig. 4.7b shows the measured phase noise characteristics of a 500 MHz signal

generated by the PLL, with a 5 MHz periodic noise injected into the substrate. The

spurs (C) in phase noise characteristics placed at offsets of 5 MHz and its harmonics

are generated due to the periodic noise injected into the substrate through the noise

injector buffers. The Spurs (A) and (B) are generated due to a background FPGA

activity used in the measurements.

The period jitter measurement of a 500 MHz signal generated by the PLL is

shown in Fig. 4.7c. The measured period histogram shows a summation of two

Gaussian distributions which is primarily due to the single tone modulation of VCO

by the injected periodic noise. Hence resulted in an increased peak-peak deterministic

period jitter performance of 119 ps.

The magnitude of spurious tones in the frequency spectrum and phase noise char-

acteristics of the output signal (in frequency domain), and peak-peak deterministic

period jitter performance of the output signal (in time domain) are used to quantify

4.6. Noise coupling mechanisms 70

the effects of substrate noise on PLL performance [2] [28] [68].

4.6 Noise coupling mechanisms

Fig. 4.8 shows the on-chip test setup used in the measurements. The periodic sub-

strate noise is generated from large sized digital buffers (without guard rings) shown

in Fig. 4.6c. The generated substrate noise parasitically couple to the VCO control

voltage through the loop filter, CP, and PFD circuits and also directly to the VCO

through its transistor bulk nodes, which then frequency modulates the VCO output

signal generating spurious tones in its frequency spectrum.

The loop filter capacitors (Cz = 200 pF, and Cp = 15.2 pF ) are implemented

using gate capacitance of NMOS transistors and occupy a large chip area of 250 µm

X 150 µm. Therefore, in this implementation, the loop filter transistors (due to the

large area and its NMOS transistor based implementation) and the VCO bulk nodes

are the most sensitive points to the substrate noise. And besides these noise coupling

paths, the VCO circuit is also sensitive to the noise coupled from power supplies,

bond-wires, and other noise coupling mechanisms present on-chip.

VCOPFD/CP

Rz

Cz

Cp

S1

S2 S3

S4Lb2 Lb3

Lb4 Lb5

Lb6

Lb7

Lb1

Lb8 CS11

CS1

CS2

CS3

CS4

CS5 CS6

CS8

CS7

CS9 CS10

RM1

RM2

RM3

RM4RM5

RS1 RS2

RS3

RS4

RS5

NoiseSignal

VDD CP_OUT Vctrl

VCO_VDD

LPF

Noise InjectorBuffers

VCO_OUT

Bulk Node

5 Bond WiresConnected in Parallel

Wp

Pbias

DIVIDER

Fref

Ffb VCO control voltage

Figure 4.8: Type II, 3rd order integer-N charge-pump PLL and noise injector buffers- Test bench.


The switches S1 − S4 in Fig. 4.8 can be configured to explain the different modes

of noise coupling to the VCO. A 2 MHz periodic noise is injected into the substrate

through digital buffers and the magnitude of spurs in the output spectrum are moni-

tored to characterize the sensitivity of VCO to the injected noise. The following test

cases were considered to explain the primary mode of noise coupling to the VCO,

Case 1 - S1, S2, and S3 are OFF, and S4 is ON. This enables the characterization

of noise coupling directly to the VCO through its bulk nodes, power supply, and

bond-wires. Fig. 4.9 shows the measured frequency spectrum of VCO output signal

with spur (B) in response to a 2 MHz periodic noise injected in the substrate, with

the test-bench configured under this configuration.

Figure 4.9: VCO output spectrum (open loop) with spurs at 2 MHz offset in responseto 2 MHz noise injected in the substrate.

Case 2 - S1, S2, and S4 are OFF, and S3 is ON, the loop filter transistors in PLL

are now connected to the VCO control voltage node and therefore, the substrate noise

picked up by the loop filter NMOS transistors (which occupy a large area) are now

coupled to the VCO control voltage. The large spur (A) in the VCO output spectrum

shown in Fig. 4.9 indicates that the primary mode of noise coupling to the PLL in

this implementation is through the noise picked up by the loop filter transistors.

Case 3 (VCO gain based measurements) - Fig. 4.10a shows the variations in the

VCO gain (Kvco = δfout

δVctrl, measured from loop filter voltage to the VCO output) with

respect to the VCO control voltage and the width of its current starving transistors,


(a) Sensitivity of VCO gain to the VCO control voltage.

(b) Spur level variations with respect to VCO control voltage.

Figure 4.10: Open loop VCO characterization (fnoise = 10 MHz).

Wp. With the test setup configured in Case 2 configuration, a 10 MHz periodic noise

is injected in the substrate and the sensitivity of magnitude of spurious tones are

monitored against the VCO gain variations.

Fig. 4.10b shows the measured sensitivity of spur level in the VCO output to

the VCO control voltage. The measured spur characteristics tracks the VCO gain

variations measured from loop filter node to its output.

The analysis presented in Case 1, 2 & 3 confirms that the unwanted spurs in the

VCO output spectrum are generated primarily due to the periodic substrate noise


coupled to the VCO control voltage through the loop filter NMOS transistors and

Fig. 4.10 verifies the case. Similar experiments with large spur levels in the VCO

output spectrum generated due to parasitic interaction through substrate are also

been reported in [2] [28] [68].

Simulation verification - The exact substrate model including the design on-chip,

interconnect metal layers, doping profile of the substrate is difficult to come up with.

However, for a given implementation, a simple first order model with few lumped ele-

ments attached to the transistor bulk nodes can be used to understand the substrate

noise effects [27].

The test setup shown in Fig. 4.8 is simulated to verify the noise coupling through

loop filter transistors in this implementation. The periodic noise generated from

digital buffers are injected into the bulk nodes of loop filter transistors and the be-

havior of spur levels in the VCO output are monitored. The substrate parasitics are

modeled using a few critical lumped elements connected to the bulk nodes (1st order

approximation, [27]) as shown in Fig. 4.8.

Resistors RM1 − RM5 model the series resistance of the interconnect metal layers

and RS1−RS5 model the spreading resistance through substrate. CS1−CS10 represent

the capacitance between the interconnect lines and substrate. CS11 model all the

capacitance between the bulk node and AC ground (p-n junction capacitance and ESD

capacitances). Source and drain junction capacitance are included in the transistor

model. Lb1 −Lb8 represent inductance associated with the bond wires. Five dedicated

package pins are used for the ground connection accounting a bond wire inductance

(Lb8) of ≃ 300 pH.

The component values in the assumed 1st order model can be roughly calculated

from the layout information and through empirical fitting method, to match the am-

plitude and frequency response of substrate noise effects [27]. The amplitude response

of spur levels depends on the strength of the noise injecting buffers, interconnect (≃

200 fF) and transistor capacitance to substrate, inductance of bond wires and the

4.7. Substrate noise effects of pulsed clocking scheme 74

Figure 4.11: Sensitivity of VCO (open loop) output spur level to the periodic noisefrequency.

resistance from bulk node to the ground (≃ 5Ω). The frequency response of spur

level largely depends on CS11 (includes all capacitance from bulk node to ground, ≃

95 pF) and the spreading resistance of the substrate.

Fig. 4.11 shows the measured and simulated sensitivity of output spur level to

the frequency of periodic noise injected in the substrate. A low pass characteristics of

substrate noise effects on VCO/PLL performance is observed in measurements and

is in agreement with the reported works in [2] [27].

4.7 Substrate noise effects of pulsed clocking scheme

In all the above experiments, we have used 50% duty cycled clock signals for substrate

noise injection through digital buffers (emulating the clock buffers in a mixed signal

chip). Many high-performance processors have been routinely using pulsed clocking

scheme for over a decade [89] [90] [91] as it has the following advantages of a reduced

clock load, a low sequencing overload, skew tolerance, allowed time borrowing, and

less energy consumption. Recently, it has been recognized that pulsed clocking can

be also useful for low-power digital circuits [92] [93].

PLL shown in Fig. 4.8 is configured to generate a 500 MHz output signal and

pulsed clock signals of different frequencies with duty cycle in the range 20% to 50%


Figure 4.12: Measured sensitivity of PLL output spur levels to the frequency andduty cycle of a noise injector signal.

are used for substrate noise injection. Fig. 4.12 shows the impact of frequency and

duty cycle of a pulsed clock noise injector signal on the magnitudes of spurious tones

present in frequency spectrum of PLL output signal (500 MHz).

(a) Clock harmonic content. (b) Effect on PLL output spur level.

Figure 4.13: Effect of a pulsed clock noise injector signal (fclock = 2.5 MHz) on thePLL output spur levels.

Lower duty cycle for clock signals reduces the power content of its fundamental

component (shown in Fig.4.13a) and hence result in reduced periodic noise effects

generated due to its fundamental component. Also, in this implementation, the PLL

exhibits a low pass characteristics to the substrate noise effects over the measured

frequency range as shown in Fig. 4.11 & 4.12. Therefore, the combined effect of


reduced levels of substrate noise injection and the low pass characteristics offered by

the PLL to its substrate noise effects result in reduced magnitudes of spurious tones,

on reducing the duty cycle of noise injector signal as demonstrated.

For periodic noise frequencies of 10, 20, and 40 MHz, a reduction in spur mag-

nitudes of 3.36 dB, 2.59 dB and 0.84 dB are observed, respectively, on reducing the

duty cycle of noise injector signal from 50 % to 40 %. For higher frequencies of noise

injector signal, the reduction in spur magnitudes are low, due to the low pass filtering

effect seen by the substrate noise effects.

Effect of clock harmonics - Lower duty cycle of noise injector signal reduces its

fundamental frequency power component, however, the power levels at other harmon-

ics increase as shown in Fig. 4.13a and hence their corresponding output spur levels

at higher harmonic frequency offsets also increase. However, the spurs at higher har-

monic frequency offsets are of lower amplitudes due to its lower power content and

the low pass filtering effect on the substrate noise effects.

Fig. 4.13b shows the effect of a 2.5 MHz periodic substrate noise and its harmon-

ics on the corresponding spur levels present in PLL output. The spur characteristics

at harmonic frequency offsets as a function of duty cycle follow the amplitude char-

acteristics of harmonic components of a clock signal shown in Fig. 4.13a.

Figure 4.14: Measured duty cycle effects of a 5 MHz noise injected in substrate onPk-Pk deterministic period jitter performance of 500 MHz PLL output signal.

4.8. Summary 77

Fig. 4.14 shows the duty cycle effects of a 5 MHz substrate noise on Pk-Pk

deterministic period jitter performance of a 500 MHz output signal. With the PLL

output frequency programmed to 500 MHz and for a periodic noise frequency of 5

MHz, a 12.53 dB reduction in the output spur level and a 107 ps reduction in Pk-Pk

deterministic period jitter are observed on reducing the duty cycle of a 5 MHz pulsed

clock from 50 % to 20 %.

4.8 Summary

The effect of periodic switching noise generated from pulsed clock buffers on the

performance of charge-pump PLLs are demonstrated experimentally. The sensitivity

of PLL performance metrics such as output spur level, phase noise, and jitter are

monitored against the variations in the properties of a noise injector signal. The source

and mechanism of noise coupling are also explained through various experimental

techniques performed on-chip.

A pulsed clock noise injector signal (5 MHz) with its duty cycle reduced from

50% to 20%, resulted in a 12.53 dB reduction in PLL output spur level (at 5 MHz

offset from 500 MHz output signal) and a 107 ps reduction in its Pk-Pk deterministic

period jitter performance.





Chapter 5

Low Power Frequency Synthesis

This chapter presents a digital frequency multiplier design for low power fre-

quency synthesis targeting the relaxed performance, short distance wireless communi-

cation applications. The proposed digital frequency multiplier design offers broadband

operation with low power and low area implementation advantages, and also bene-

fits from the CMOS technology scaling. The non-idealities present in the frequency

multiplier implementation, its effect on the spectral performance, and techniques to

reduce these effects are discussed in detail. Measurement and simulation results from

two PLL designs with and without digital frequency multiplier circuits implemented

in 0.13 µm CMOS process are also presented.

5.1 Introduction

A low power, fully integrated radio-on-a-chip (RoC) is essential for short range, bat-

tery operated wireless communication applications. Synthesis of RF carrier signal (in

transmitter) and local oscillator signal (in receiver) in any RoC consume a significant

percentage of its total power [44]. Therefore, low power frequency synthesizer circuits

are essential for an energy efficient wireless communication operation.

The frequency synthesizer circuits are generally implemented using charge-pump

phase locked loops (CP-PLL) [1] [14] [94]. The high frequency operating blocks,

mainly the voltage controlled oscillator (VCO) and the first few stages of a frequency

divider or prescaler, are the main power consuming blocks in a CP-PLL. VCO circuit

designs using micro-machined resonators [41], sub-threshold circuit techniques [42],

and current reused architecture [43] and the frequency divider circuit techniques using

injection locking phenomenon [44] [45] are proposed in the literature to reduce the

78


Vdd

VCORz

Cz

Cp

Iup

Idn

UP

DN

PFDVctrl

fref


FrequencyMultiplier

Fout = M*Fin

CP

ffb

LPFLow frequency

PLL

Buffer

f0

f0/M

f0

Figure 5.1: Low power frequency synthesizer design using frequency multiplicationtechnique.

power consumption of these circuits.

In the relaxed performance requirement, short distance wireless communication

applications such as IEEE 802.15.4 [46] or MICS [15] [47], ring oscillator based VCOs

are preferred than LC-VCOs due to its low power and low area implementation ad-

vantages. Also most frequency synthesizers use flip-flop based digital prescalers to

generate the feedback signal for comparison with a crystal reference. The power

consumption of these digital circuits scales with their operating frequency. There-

fore, in these implementations, the power consumption of frequency synthesizer can

be reduced by operating the PLL at a divided down lower frequency of f0

Mand the

target RF carrier signal can be generated by employing frequency multiplier circuits

(fout = M ∗ fin) outside the loop [31] [32] [33] [34] [35].

Fig. 5.1 shows the low power frequency synthesizer architecture using frequency

multiplication technique. Here, the VCO and the first few stages of frequency divider

operate at a reduced frequency of f0

M, leading to a significant power reduction in this

architecture. However, the frequency multiplier circuits in this implementation have

to be designed in a power and performance efficient way to take advantage of the

5.2. Frequency Multiplication by Edge Combining 80

power savings obtained.

In this chapter, we investigate the use of digital circuit techniques to perform a

low power and area efficient frequency multiplication operation. Moreover, the dig-

ital frequency multiplier implementation benefits from the improved performance of

digital circuits in the nano-meter CMOS process technologies. The sources of non-

ideal effects in the proposed frequency multiplier design which gives rise to broadband

spurs, solutions to minimize these mismatch effects and various wireless communi-

cation applications where such a design can be employed are discussed in detail.

Measurement and simulation results from two PLL designs with and without dig-

ital frequency multiplier circuits implemented in 0.13 µm CMOS process are also

presented for performance comparison.

5.2 Frequency Multiplication by Edge Combining

Frequency multiplication can be performed by combining the rising and falling tran-

sitions of a set of equally spaced phases of a low frequency signal as shown in Fig.

5.2. Here A, B and C are the low frequency signals generated from a ring oscillator

or delay line locked to a crystal reference and are spaced equally apart by TRO/3,

where TRO = 1

fROis the time period of oscillation of a ring oscillator or the total

delay length of a delay chain. The logical AND-OR operation of these low frequency

waveforms i.e, AB + BC + CA result in a high frequency square wave of frequency

3 ∗ fRO as shown in Fig. 5.2.

In general, edge combining using M number of phases of a low frequency signal

of frequency fRO, spaced equally apart by TRO/M , result in a high frequency output

waveform of frequency M ∗ fRO, where M is the frequency multiplication factor.

Razavi et al. in [31] used this edge combining technique to generate high frequency

signals close to the transition frequency (fT ) of a process technology and demonstrated

a 6 GHz PLL in 20 GHz BiCMOS process wherein no conventional ring oscillator


TRO

A

B

C

AB + BC + CA AB CA BC

TRO/3 TRO/3 TRO/3

Figure 5.2: Frequency multiplication by edge combining principle (fout = 3 ∗ fRO).

could achieve this frequency. Besides, synthesis of high frequency signals, the edge

combining technique is also used to minimize the power consumption of frequency

synthesizers by reducing the frequency of operation of its VCO and divider circuits [32]

- [35], as shown in Fig. 5.1.

Frequency multiplication technique limitations - The non-ideal effects in the fre-

quency multiplier (or edge combiner) implementation alters the transition time in-

stants of frequency multiplied output signal from its ideal value and hence introduces

a beat tone at a frequency of fRO in its transient waveform. This systematic error

in the edge combiner output signal causes duty cycle distortion in its transient wave-

form (deterministic period jitter) and result in an increased level of spurious tones

(broadband spurs) at harmonics of fRO in its frequency spectrum.

Fig. 5.3 shows the transient waveform of a frequency multiplied edge combiner

output signal (fout = 3 ∗ fRO) and its frequency spectrum with fRO spurs generated

due to the non-ideal effects. The constants p1 to p5 in Fig. 5.3a defines the time

instant of signal transitions in the frequency multiplied output waveform.


p1T

6

p2T

6

p3T

6

p4T

6

p5T

6

time, (t)V

olta

ge

AB BC CA

0 T

(a) Transient waveform of a frequency multiplied output signal.

fRO 2fRO 3fRO 4fRO 5fRO

Carrierto

spurratio(dB)

Frequency

Pow

er (

dB)

Unwanted spursgenerated due to non-ideal

frequency multiplication

(b) Power spectrum of a frequency multiplied output signal.

Figure 5.3: Effects of non-ideal frequency multiplication (fout = 3 ∗ fRO).

• Ideal implementation - In an ideal case, pi = i, where i = 1, 2, ...., (2M − 1),

and the broadband spurs are negligible (equal to noise floor) in the frequency

multiplied output signal spectrum.

• Non-ideal implementation - Under mismatched condition, the constants pi’s

can take values in the range, (0 < p1 < 2), (1 < p2 < 3), (2 < p3 < 4),

(3 < p4 < 5), (4 < p5 < 6) and hence result in duty cycle distortion effect in

the frequency multiplied transient waveform and generate broadband spurs in

its frequency spectrum.

The broadband spur performance of an edge combiner is quantified using its carrier

to spur ratio (CSR) metric measured in dB as shown in Fig. 5.3b. Fourier series

expansion of the frequency multiplied output signal (AB+BC+CA) can be expressed

as,


f(t) =a0

2+

∞∑

n=1

an · cos(

2nπt

T

)

+∞

∑

n=1

bn · sin(

2nπt

T

)

(5.1)

a0 =V0

3·

[

p1 + p3 + p5 − p2 − p4

]

(5.2)

an =V0

nπ·[

sin(

p1nπ

3

)

+sin(

p3nπ

3

)

+sin(

p5nπ

3

)

− sin(

p2nπ

3

)

−sin(

p4nπ

3

)]

(5.3)

bn =V0

nπ·[

1−cos(

p1nπ

3

)

−cos(

p3nπ

3

)

−cos(

p5nπ

3

)

+ cos(

p2nπ

3

)

+cos(

p4nπ

3

)]

(5.4)

where V0 is the peak-peak voltage swing. The power content of spurious tones

(fRO spurs) and at the desired output frequency (M ∗ fRO), and hence the CSR can

be computed from the Fourier series coefficients an and bn.

Figure 5.4: Effect of timing mismatch (0.904 ≤ p1 ≤ 1.096) on CSR performance.

Fig. 5.4 shows the effect of timing mismatch in p1 edge (0.904 ≤ p1 ≤ 1.096) on the

CSR performance of a frequency multiplied output signal (M=3, fRO = 800 MHz,

and fout = 2.4 GHz). A CSR of ≥ 35 dB can be achieved by limiting the timing

mismatch in transition time instants to within ± 10 ps. The relaxed performance

requirement wireless communication applications such as Zero-G (cable replacement

technology [49]) and PCS [32] demand a CSR of greater than 30 dB, and Zig-Bee and

5.3. Frequency Multiplication Circuit Techniques 84

MICS demand a CSR performance of greater than 45 dB [34] [35].

When used for RF carrier or local oscillator frequency synthesis in radio applica-

tions, these broadband spurs must be kept low to meet the power spectral density

(PSD) mask specifications of transmitters and to reduce the interference effects from

(M ± 1) ∗ fRO frequency bands in receivers.

5.3 Frequency Multiplication Circuit Techniques

Several frequency multiplication circuit techniques are presented in the literature for

low power frequency synthesis targeting the relaxed performance short distance wire-

less communication applications [32] [33] [34] [35]. Fig. 5.5 shows the conceptual

block diagram of these reported frequency multiplier circuits. They basically excite

an LC-tank (whose resonant frequency is tuned to M ∗ fRO) with the low frequency

multi-phased edges from a VCO or delay line locked to a crystal reference, to gen-

erate the frequency multiplied output signal. The LC-tank is used to enhance the

load impedance at the resonant frequency and to filter out the unwanted harmonic

components (broadband spurs) in the frequency multiplied output signal.

Del

ay li

ne /

Rin

g os

cilla

tor

Edg

e co

mbi

ner

Vdd

Fin

M*Fin

L C

fM*Fin

Gai

n

Tin/M

Figure 5.5: Frequency multiplication circuit implementation - Conceptual diagram.


Vdd

1P 1N 9P 9N

L C CL

IBiasIBias

Fout+=M*Fin Fout-=M*Fin

(Fin)

(a) Chien et al. [32]

L C

Fin

M*Fin

Rin

g os

cilla

tor

(b) Verma et al. [33]

A1

A2

A2

A3

A9

A1

Vdd

M*Fin

(Fin)

L C

Ibias

(c) Pandey et al. [34]

Figure 5.6: Frequency multiplication circuit techniques.

Chien et al. in [32] used differential amplifiers to excite an LC tank (Fig. 5.6a)

with the multi-phased low frequency signals generated from a differential amplifier

based delay line. The DC tail current sources used in all the differential pairs lead to

an increased static power consumption and hence incurs a large power overhead.

In [33], Verma and Lee performed frequency multiplication by extracting the M th

harmonic of a low frequency signal (fRO) from a M-stage ring oscillator using LC-

resonator tuned to a frequency of M ∗ fRO. In a ring oscillator, as the rising edge

propagates through the inverter stages, current surge passes from the inverter output

node to ground. In one time-period of a M-stage ring oscillator, there are M such

occasions when a current pulse is sent to the ground node. The ground node of

all inverters are tied together and the combined current pulse is made to excite an

LC-resonator (Fig. 5.6b) to generate the frequency multiplied output signal.

However, this technique suffers from poor output voltage swing (less than 1/10th

of supply voltage) as a larger ground bounce would reduce the gate overdrive of the

switch and hence, an additional amplifier is required to get the desired voltage swing.

Also, amplifying a high frequency LO signal is costly both in terms of area and power.


[34] and [35] decoupled the resonator from ring oscillator ground node to obtain

a larger signal swing (Fig. 5.6c). They used MOS switches to excite an LC-tank

tuned to M ∗ fRO. However, the output voltage swing in this technique is limited

due to the reliability concerns of MOS switches. The output common mode voltage

in this circuit is at Vdd and a larger output swing makes the Vgd of top NMOS switch

to exceed Vdd by a large value, causing gate oxide breakdown of this transistor. For

a 0.13 µm CMOS technology with 1.2 V supply voltage, the output swing in this

technique is limited to only about 450 mV.

In general, the performance of these reported frequency multiplication circuit

techniques are limited by a poor voltage swing, narrow-band operation, and large area

overhead due to the use of LC-resonators. Furthermore, low on-chip inductor quality

factors [48] limit the carrier to spur ratio improvement (CSR) in these frequency

multiplier circuits.

The nano-meter CMOS process nodes offer very high transition frequencies (185

GHz for 65 nm process) [95] and an improved matching performance (for the same

device area, W ∗ L) [96] [97], and hence encourages the use of digitally assisted RF

circuit techniques in these advanced technology nodes. Also, a digital edge combiner

implementation offers rail-to-rail signal swing, broad-band operation and low area

implementation advantages compared to the reported analog frequency multiplication

circuits. However, an extra care and attention is required to minimize the mismatch

effects in the edge combiner implementation.

In this work, we exploit the higher transition frequencies and the improved match-

ing performance offered by the nano-meter CMOS devices and demonstrate a static

logic gate based frequency multiplier design for low power frequency synthesis target-

ing the relaxed performance wireless communication applications.

5.4. Digital Frequency Multiplier Implementation 87

5.4 Digital Frequency Multiplier Implementation

A frequency multiply by 3 (fout = 3 ∗ fRO) edge combiner implemented using digital

logic gates is shown in Fig. 5.7a. Here A, B, and C are the low frequency (fRO),

multi-phased signals generated from a voltage controlled ring oscillator embedded in

the PLL. A pseudo-differential ring oscillator VCO is used to generate the tightly

coupled equally spaced phases (A, B, & C) with a mismatch of less than ≤ 1o in the

spacing between them [98].

B

C

Low

fre

quen

cy s

igna

lsfr

om V

CO

(f R

O)

(AB + BC + CA)

fout = 3*fRO

A

X

Y

WN = W

WP = R*W

AB BC CA

tA

tB

tC

(a) Edge combiner.

T

A

B

C

AB + BC + CA

T/3

AB CA BC

T/6

T/6

T/6

tA

tA

tA

tB

tB

tB

tC

tC

AB

(b) Edge combiner transient waveforms.

Figure 5.7: Digital edge combiner (or frequency multiplier) implementation.

The digital edge combiner performs logical AND-OR operation of these low fre-

quency signals (A, B, & C) and combines its rising and falling transitions to generate

the frequency multiplied output waveform (AB + BC + CA) as shown in Fig. 5.7b.

Every rising or falling transition in the input signals A, B, and C lead to a rise or fall

transition in the frequency multiplied output signal (edge combining principle).


The rise and fall transitions of input signals A, B and C propagate from the ring

oscillator nodes (or source nodes) to the edge combiner output node Y after a path

delay of tA, tB, and tC respectively. The mismatch between these path delays forces

the transition time instants in the frequency multiplied output signal to deviate from

its ideal value. Hence, introduces a duty cycle distortion effect in the frequency

multiplied transient waveform and result in an increased level of spurious tones at

harmonics of fRO (broadband spurs) in its frequency spectrum. Therefore, matching

of path delays from A to Y, B to Y, and C to Y in a digital edge combiner is very

critical for an ideal frequency multiplication operation.

The matching between the parallel path delays tA, tB, and tC in a digital edge

combiner shown in Fig. 5.7a can be affected due to the following reasons,

• Edge combiner circuit or logic gate topology induced mismatch.

• Layout induced mismatch.

• Process induced device mismatch.

To analyze the effect of these mismatches on the frequency multiplication perfor-

mance, a frequency multiply by 3 digital edge combiner (fout = 3 ∗ fRO) used for 2.4

GHz frequency synthesis from a set of equally spaced 800 MHz input signals (A, B,

and C) is considered. The carrier to spur ratio (CSR) at a close in frequency of ±800

MHz offset from a 2.4 GHz carrier is monitored to quantify the mismatch effects.

5.4.1 Logic Gate Topology Induced Mismatch

The mismatch between rise-times or fall-times of successive rising or falling transitions

in the frequency multiplied output signal result in a duty cycle distortion effect in

its transient waveform. In a digital edge combiner implementation, this is caused

primarily due to the logic gates with more than one input ports such as NAND and

NOR gates. Fig. 5.8 shows the topology of NAND and NOR gates used in the digital

edge combiner implementation. The transition times of output signals from these

digital logic gates (AB, BC, CA and AB + BC + CA) shown in Fig. 5.7 should


be critically matched to minimize the broadband spurs in the frequency multiplied

output signal spectrum.

Let us consider a digital edge combiner design using standard implementation for

NAND and NOR gates shown in Fig. 5.8a. In a standard implementation of 3-input

NOR gate, the rise times and fall times of output signal vary depending upon the

input terminal of signal transition, due to the difference in total capacitance seen by

the signals from each of its input terminals.

Vdd

W W

3RWAB

BC

CA

3RW

3RW

W

VddVdd

RW RW

2WA

B2W

X1

X2

Y1

(a) Standard implementation.

Vdd Vdd Vdd

W W W

RW

RW

RWRW

RW

RW

RW

RW

RW

AB

BC

CA

VddVdd

RW RW

W

W

W

W

A

B

(b) Symmetric implementation.

Figure 5.8: Digital logic gates used in the edge combiner implementation.

For example, a rise transition at the input port AB of NOR gate (Fig. 5.8a) have

to discharge the load capacitance at the output node and the parasitic capacitance at

the intermediate nodes X1 and X2 as well. However, the rise transition at input port

BC have to discharge the load capacitance and the intermediate node capacitance

of X1 and the rise transition at input port CA should discharge only the output

node load capacitance. Thus leading to a difference in fall times of the output signal

depending upon the input terminal of signal transition as shown in Fig. 5.9a.

The mismatch between rise times or fall times of the NAND and NOR gate output

signals affect the time instant of signal transitions in the frequency multiplied edge

combiner output signal and distorts its duty cycle as shown in Fig. 5.9a. This duty

cycle distortion effect introduces a beat tone at a frequency of fRO in the transient

waveform and spurious tones at frequencies of fRO and its harmonics in the frequency


(a) Transient waveforms. (b) Power spectrum.

Figure 5.9: Digital edge combiner waveforms - standard implementation for logicgates.

spectrum of edge combiner output signal as shown in Fig. 5.9b.

The average frequency of the edge combiner output signal (AB + BC + CA) is

M ∗ fRO (Fig. 5.9b). However, the duty cycle distortion effect or the mismatch in

path delays due to a standard logic gate based implementation affects the purity of

the frequency multiplied output signal with an increased deterministic period jitter in

its transient waveform and larger broadband spurs in its frequency spectrum, which

makes this edge combiner implementation not suitable for certain applications.


Figure 5.10: Digital edge combiner waveforms - symmetric implementation for logicgates.

A symmetric implementation of digital logic gates shown in Fig. 5.8b minimizes


the mismatch between rise times or fall times of its output signal by presenting an

equal parasitic capacitance to all of its input terminals and hence minimizes the

topology induced mismatch in the path delays of an edge combiner. Fig. 5.10a

shows the transient waveforms of the digital edge combiner with equal rise times and

equal fall times, implemented using symmetric logic gates. The frequency multiplied

output signal (Y) in Fig. 5.10a shows a negligible duty cycle distortion effect due to

the matched path delays in the edge combiner implementation and hence, eliminates

the broadband spurs in its frequency spectrum as shown in Fig. 5.10b.

5.4.2 Layout Induced Mismatch Effects

The asymmetries in an edge combiner layout such as unequal interconnect lengths or

the unequal parasitic capacitance seen by its critical nets limit the matching between

its parallel path delays (tA, tB, and tC in Fig. 5.7) and hence degrades its carrier to

spur ratio (CSR) performance. Fig. 5.11b shows an example layout implementation

of the frequency multiply by 3 digital edge combiner designed using symmetric logic

gates. The critical nets of the edge combiner are highlighted in the layout (A, B, C,

AB, BC, and CA) and longer interconnect lengths are used to improve the matching

between its parallel paths.

Fig. 5.12a shows the frequency multiplied transient waveform simulated using

the layout extracted net-list of an edge combiner. The simulated transient waveform

exhibit a less duty cycle distortion effect with a smaller timing error in its transition

time instants. The corresponding frequency spectrum of the edge combiner output

signal is shown in Fig. 5.12b. The spurious tones at harmonics of fRO in the frequency

spectrum are generated due to the mismatch induced by the parasitics of the edge

combiner layout and resulted in a degraded CSR performance of ≃54 dB. The carrier

to spur ratio can be improved by following careful layout practices along with shielding

of critical interconnects using supply and ground traces, fully matched interconnect

lengths, and dummy cells.


B

C

Low

fre

quen

cy s

igna

lsfr

om V

CO

(f R

O)

(AB + BC + CA)

fout = 3*fRO

A

X

Y

WN = W

WP = R*W

AB BC CA

(a) Schematic. (b) Layout.

Figure 5.11: Digital edge combiner (fout = 3 ∗ fRO).


Figure 5.12: Effect of layout parasitics on the frequency multiplied output signal.

5.4.3 Process Induced Device Mismatch

On-chip random local variations affect the matching between devices used in the edge

combiner implementation and hence, introduces mismatch between its parallel paths.


Monte Carlo simulations are carried out on a digital edge combiner circuit shown

in Fig. 5.11a implemented using symmetric logic gates to demonstrate the device

mismatch effects. The NMOS and PMOS transistor widths in an unit inverter are

chosen as W and R ∗ W , respectively, where R is the relative strength of PMOS and

NMOS transistors (Fig. 5.11a). The NAND and NOR gates in the edge combiner

are sized to match the driving strength of this reference inverter.

Figure 5.13: Monte Carlo simulation results of carrier to spur ratio (CSR) for theedge combiner circuit shown in Fig. 5.11a, W = 3µm, R = 1, M = 3, fout = 2.4 GHz,and fin = 800 MHz.

Fig. 5.13 shows the statistics of carrier to spur ratio performance of an edge

combiner obtained through Monte Carlo simulation (N = 1000) using the mismatch

data provided by the foundry. The minimum and average CSR of fRO (800 MHz)

spurs in the frequency multiplied output signal spectrum (2.4 GHz) are found to be

40 dB and 47 dB respectively, for an unit transistor width of 3 µm.

The matching between on-chip transistors can be improved by increasing their

dimensions [96] [97]. Therefore, edge combiner design with larger transistor dimen-

sions (W&L) helps improving its matching performance. Increasing both W and L

of a transistor degrades its frequency response. Hence, Monte Carlo simulations are

performed on the edge combiner designs with different transistor widths keeping its

length constant (minimum length offered by the technology), to study its CSR perfor-

mance. Fig. 5.14a, b & c shows the statistics of CSR performance obtained through


(a) Width = 3 µm. (b) Width = 6 µm. (c) Width = 9 µm.

(d) Standard logic gates.

(e) Symmetric logic gates.

Figure 5.14: Monte Carlo simulation results - Effect of transistor widths on the carrierto spur ratio (CSR) performance of the edge combiner.


Monte Carlo simulations performed on edge combiner circuits having unit transistor

widths of 3 µm, 6 µm, & 9 µm respectively.

Larger transistor widths provide faster rise and fall transitions in the edge com-

biner signals and also reduces the mismatch between them. Hence, improves the

CSR performance of an edge combiner effectively and also minimizes its variations as

demonstrated in Fig. 5.14. However, larger transistor widths result in an increased

power consumption in the edge combiner circuit.

Fig. 5.14d & e shows the Monte Carlo simulation results of edge combiners having

different transistor widths, implemented using standard and symmetric logic gates

respectively. In a standard logic gate based implementation, the sources of mismatch

between the edge combiner parallel paths is dominated by the topology of logic gates

used and hence, only a smaller improvement in CSR performance was observed on

increasing the transistor widths.

In the symmetric logic gate based edge combiners, device mismatch due to process

variations dominate the sources of mismatch between its parallel paths. Therefore,

edge combiner designs using larger transistor widths exhibited a significant improve-

ment in its CSR performance as shown in Fig. 5.14e. For a digital edge combiner

design with symmetric logic gates (fout = 2.4 GHz, fin = 800 MHz, and M = 3), a

CSR of 45 dB was observed on using an unit transistor width of 2 µm, consuming

600 µW of power.

Process corners (SS, SnFp, TT, FnSp, FF) affect the rise times and fall times of

signal transitions and also the relative strength of PMOS and NMOS transistors in

the edge combiner. Fig. 5.15 shows the impact of process corners and temperature on

the CSR performance of a digital edge combiner. Fast-Fast (FF) corner with sharp

rise and fall transitions in the edge combiner signals exhibited an improved CSR

performance. The relative strength of PMOS and NMOS transistors affect the duty

cycle of frequency multiplied output signal and hence, alters the power content of its

even harmonics. Fig. 5.16 shows the effect of R on the duty cycle and 2nd harmonic

5.5. Impact of Technology Scaling 96

Figure 5.15: Process corners and temperature effects on the carrier to spur ratioperformance of the edge combiner.

Figure 5.16: Effect of relative strength of PMOS and NMOS transistors (R) on the2nd harmonic power and the duty cycle of edge combiner output signal.

power content of 2.4 GHz edge combiner output signal. The duty cycle of the edge

combiner output signal changes by 8% across the process corners from SS to FF, for

an unit transistor width of 0.4 µm.

5.5 Impact of Technology Scaling

The higher transition frequency (fT = 185 GHz for 65 nm), faster transition times,

and improved matching performance (for the same device area, W ∗ L) [97] offered

by the nano-meter CMOS devices encourages the use of digitally assisted RF cir-

cuit techniques in these advanced process technology nodes. The mismatch between


threshold voltages (VT ) of transistors due to process variations is a main source of

mismatch between the parallel paths of an edge combiner. The difference between

threshold voltages of a pair of MOS transistors is described by its standard deviation

as [97],

σ∆V T =AV T√W ∗ L

=qtox

√

2Ntdepl

ǫ0ǫox

√W ∗ L

(5.5)

(a) NMOS transistor. (b) PMOS transistor.

Figure 5.17: Standard deviation of difference in transistor threshold voltages versusthe inverse square root of the transistor area (W ∗ L), for 130 nm and 65 nm process.

where AV T is the technology conversion constant or matching coefficient measured

in mV µm and is proportional to the gate oxide thickness (tox). Fig. 5.17 shows the

simulated standard deviations of difference between threshold voltages of a pair of

MOS transistors in 65 nm and 130 nm CMOS process technologies.

The constant AV T and the oxide thickness (tox) decreases with the CMOS tech-

nology scaling. Therefore, for a same device area (W ∗L), the scaled CMOS technolo-

gies feature a better matching performance between its devices with a lower σ∆V T as

demonstrated in Fig. 5.17. The digital edge combiners benefit from this improved

matching performance between devices in these nano-meter CMOS technologies and

exhibit an improved carrier to spur ratio performance.

To demonstrate the technology scaling effects on the edge combiner performance,


Table 5.1: Transistor threshold voltage.

Transistor130 nm 65 nm 65 nm

(High speed) (High VT ) (Low VT )NMOS 324 mV 505 mV 270 mVPMOS 251 mV 426 mV 267 mV

Figure 5.18: Impact of process technology on the edge combiner CSR performance.Transistor length chosen as 200 nm for all devices.

Monte Carlo simulations are performed on the edge combiner circuits (Fig. 5.11a)

implemented in 65 nm and 130 nm CMOS process technologies. Table 5.1 lists the

transistor flavors used in the analysis and their threshold voltages (VT ). Fig. 5.18

shows the Monte Carlo simulation results of CSR performance of the edge combiners

implemented using these transistors.

The digital edge combiner designs using 65 nm CMOS transistors exhibited an

improved CSR performance with better matching compared to 130 nm CMOS pro-

cess implementations. Also, the lower threshold voltage devices having larger gate

overdrives helps achieving faster transition times and hence exhibited an improved

CSR performance. Thus, digital edge combiner circuits benefits from the CMOS

technology scaling effects and are readily portable to advanced CMOS process nodes

with an improved performance.

5.6. Frequency multiplication factor - M 99

5.6 Frequency multiplication factor - M

B

C

Low

fre

quen

cy s

igna

lsfr

om V

CO

(f R

O)

(AB + BC + CA)

fout = 3*fRO

A

X

Y

AB BC CA

B

C

Low

fre

quen

cy s

igna

lsfr

om V

CO

(f R

O)

A

AB BC CD DE EA

E

D

fout = 5*fRO

(AB + BC + CD+ DE + EA)

(a) Digital edge combiner schematic, M = 3 and 5.

(b) Divider power consumption. (c) CSR performance, M = 3 and 5.

Figure 5.19: Edge combiner implementation, divider power consumption and CSRperformance.

The frequency multiplication technique minimizes the power consumption of fre-

quency synthesizers by reducing the frequency of operation of its VCO and divider

circuits. Larger multiplication factor (M) reduces the frequency of operation of PLL

5.7. Frequency Synthesizer - Simulation Results 100

more. However, its effect on the frequency synthesizer power consumption and spec-

tral performance must be analyzed to make a design choice on the value of M.

Impact of M on power savings - Fig. 5.19b shows the power consumption of

divider circuit in PLL versus the frequency multiplication factor of edge combiner.

The values of M greater than 5 do not result in any significant power savings as shown.

Furthermore, a larger M requires more number of phases to be generated from the

ring oscillator and also result in more number of spurious tones in the frequency

spectrum of edge combiner output signal. Therefore, it is sufficient to discuss for the

cases of M = 3 and 5.

Impact of M on phase noise performance - The VCO phase noise performance

improve by a factor of 20*log(M) due to its low frequency operation ( f0

M). When

multiplied in frequency (fout = M ∗ fRO), it worsens by the same factor leading to no

net change in the phase noise performance.

Impact of M on CSR performance - Fig. 5.19a shows the digital edge combiner

schematics for the frequency multiplication factors 3 and 5. Fig. 5.19c shows the

power consumption and mean CSR performance of edge combiner circuits with M

= 3 and 5 extracted from Monte-Carlo simulations. A larger M increases the power

consumption of edge combiner and also result in degraded CSR performance due to

more mismatches.

Therefore, a design choice of M = 3 for the digital edge combiners offer a bet-

ter CSR performance (greater than 40 dB) with less mismatches and also result in

significant power savings in the frequency synthesizer design.

5.7 Frequency Synthesizer - Simulation Results

The block level description of a low power, 2.4 GHz frequency synthesizer architecture

using digital frequency multiplication technique is shown in Fig. 5.20. The PLL

operates at a lower frequency of 800 MHz to reduce the power consumption from its


VCO and divider circuits. A static logic gate based digital edge combiner (fout =

3 ∗ fRO) generates the 2.4 GHz RF carrier by combining the equally spaced 800 MHz

signals tapped from different stages of a ring oscillator VCO embedded in the PLL.

The frequency synthesizer is implemented in 0.13 µm RF CMOS process with a

1.2 V supply voltage. A brief discussion on the simulation setup is as follows,

−

+

PFD

VCO

Iref

Iref

Rz

Cz

Cp

UP

UPB

DN

DNB

VCO Control Voltage

Iup

Idn

Ffb

Fref

+

-C1

+

-Cn-1

+

-Cn

CP

LPF

+

+

-

-

VCO Control Voltage

VCO Unit Cell

Cvar

Cvar

Vdd Vdd Vdd

M0 M1 M3

BFSK Modulation Control

Edge

AB BC CA

A

B

C

ProgrammableDivider, N

2.4 GHz

PLL - 800 MHz

Combiner

(AB + BC + CA)

(Frequency Synthesis)

Vdd Vdd Vdd

B0 B1 B5

PVT Calibration Control

Equally spaced 800 MHzsignals from VCO

VddVdd

+

-

+

-

+

-

Figure 5.20: Frequency synthesizer - block level description.

Phase locked loop - A Type II, 3rd order integer-N charge-pump PLL is used to

synthesize the low frequency input signals to the edge combiner. The PLL generates

800 MHz equally spaced signals from a 1.667 MHz reference to have a channel spacing

of 5 MHz in the up-converted 2.4 GHz frequency band.

The phase frequency detector (PFD), divider and charge-pump (CP) are imple-

mented using the standard tri-state dead zone free phase detector, down counter and

current steering charge-pump architectures respectively.

The loop filter parameters are Rz = 60 kΩ, Cz = 200 pF, and Cp = 15.2 pF

designed for a loop BW of 100 KHz and phase margin of 60o. The loop filter capacitors

are implemented using gate capacitance of NMOS transistors to reduce the area


occupied by large capacitors on-chip.

Coupled ring oscillators [98] and cascaded multi-phase injection locked oscillators

[99] [35] provide tightly coupled, equally spaced signals (≤ 10 mismatch) with faster

rise and fall times. In this work, we have used a pseudo differential voltage controlled

ring oscillator [98] shown in Fig. 5.20 with varactor and bias current tuning to

generate the equally spaced 800 MHz signals.

Digital edge combiner - A frequency multiply by 3 digital edge combiner (fout =

3 ∗ fRO) implemented using conventional digital logic gates having an unit transistor

width of 3 µm is used to generate the 2.4 GHz RF carrier by combining the equally

spaced 800 MHz signals from VCO.

VCO performance comparison - Table 5.21 compares the performance of 2.4 GHz

VCOs with and without edge combiner circuits. The 2.4 GHz ring oscillator VCO

without edge combiner circuit achieves a phase noise of -91.5 dBc/Hz at 1 MHz offset

from a 2.4 GHz carrier consuming 4.477 mW power from 1.2 V supply voltage. The

corresponding oscillator figure-of-merit (FoM) is given as [100] [101],

FoM (dB) = −L(∆f) + 20log(

f0

∆f

)

− 10log(P (mW )). (5.6)

Table 5.2: VCO performance.

2.4 GHz VCO 800 MHz VCO800 MHz VCO

+ EC (2.4 GHz)Power, (mW) 4.477 2.744 3.475

Phase noise @ 1 MHz-91.5 -100.5 -91.79

offset, (dBc/Hz)FoM , (dB) 152.594 154.178 154

where, L(∆f) is the phase noise at ∆f offset, f0 is the oscillation frequency, ∆f

is the offset frequency from f0, and P is the power consumption in mW.

The simulated FoM of 2.4 GHz VCO is 152.594 dB. In a VCO with edge combiner,

the oscillator core operates at a lower frequency of 800 MHz and the EC generates 2.4

GHz carrier signal by combining its equally spaced signals. At a given offset frequency


(a) 2.4 GHz VCO. (b) EC + 800 MHz VCO.

Figure 5.21: VCO phase noise performance.

from RF carrier, the phase noise of frequency multiplied output signal (2.4 GHz) will

be higher than that of the low frequency input signals (800 MHz) from VCO core by

20 ∗ log10(M), (for M=3, 20 ∗ log10(3) ≃ 9.5dB).

Fig. 5.21 shows the simulated phase noise characteristics from the 2.4 GHz VCOs

with and without edge combiner circuits. The 800 MHz VCO achieves a phase noise

of -100.5 dBc/Hz consuming 2.744 mW power (FoM = 154.178 dB) and the frequency

multiplied 2.4 GHz output signal achieves a phase noise of -91.79 dBc/Hz (FoM =

154 dB). The simulated FoM numbers of the VCOs are high, because they include

the additional power consumption from the buffers used to drive out the VCO phases

and the edge combiner output signals.

To obtain power savings in VCO circuit by using frequency multiplication tech-

nique, the total power consumed by the low frequency VCO and the edge combiner

circuits must be less than that of a 2.4 GHz VCO. Therefore, in this design, the

maximum allowed power consumption for an edge combiner design is 1.733 mW. The

width of the transistors in the edge combiner implementation can be chosen based

on the CSR performance requirement and the amount of power savings in the VCO

design. An edge combiner design using an unit transistor width of 3 µm exhibited a

mean CSR performance of ≃ 47 dB consuming a 730 µW of power (Fig. 5.14e).

PLL performance comparison - Two PLL designs with 2.4 GHz VCO (P LL1)

5.8. Chip Implementation and Measured Results 104

Table 5.3: Summary of PLL performance (simulation)

P LL1 P LL2

(2.4 GHz) (800 MHz + EC)Process, (µm) 0.13 0.13

Vdd, (V ) 1.2 1.2Frequency, (GHz) 2.4 2.4

Power, (mW)PFD + CP 0.55 0.55

Divider + Buffers 4.515 1.513VCO + Buffers 4.477 3.475

PLL (total power), (mW) 9.542 5.538Phase noise of VCO

-91.5 -91.79@ 1 MHz offset, (dBc/Hz)

CSR, (dB) - 40 dB a

Area, (mm2) 0.32 0.33aWorst case estimate from the Monte-Carlo simulations

and 800 MHz VCO + EC (P LL2) circuits respectively are simulated and Table 5.3

summarizes their performance results.

The VCO and divider circuits in P LL2 operate at a lower frequency of 800 MHz

and hence results in a huge power savings in P LL2 compared to P LL1. However,

the performance of P LL2 is limited by the generation of broadband spurs in its

output signal frequency spectrum due to the non-ideal effects in the edge combiner

implementation. In this design, a worst case carrier to spur ratio of broadband spurs

(including VCO and edge combiner mismatch effects) in P LL2 was found to be 40

dB in simulations. The carrier to spur ratio performance can be further improved

by following careful layout practices and by increasing the transistor dimensions in

both VCO and edge combiner designs, or by using low threshold voltage and high fT

devices.

5.8 Chip Implementation and Measured Results

Chip prototypes containing the proposed digital frequency multiplier based 2.4 GHz

frequency synthesizer (Chip 1) and a conventional charge-pump PLL which operates


(a) Chip 1. (b) Chip 2.

(c) Test setup used in the measurements.

Figure 5.22: Chip micrograph in 0.13 µm CMOS process and test setup used inmeasurements. Chip 1 contains frequency multiplication based transmitter circuitsand chip 2 contains a conventional 2.4 GHz PLL for receiver LO generation.

directly at 2.4 GHz (Chip 2) are designed and fabricated in United Microelectronics

Corporation 0.13 µm mixed mode and RF CMOS 1.2/3.3 V 1P8M process. Fig.

6.2 shows the die photograph of the fabricated chips and the test setup used in


measurements. The description and measured performance of building blocks of the

proposed frequency synthesizer architecture are as follows.

Current steering charge-pump

The current steering charge-pump circuit used in the PLL is shown in Fig. 5.23a and

is designed to source or sink programmable currents in the range 3 µA to 100 µA from

a reference current source of 10 µA. Fig. 5.23b shows the measured output current

characteristics of the charge-pump. A maximum charge-pump mismatch current of

3.75 µA and 6.5 µA are observed in the VCO control voltage range of 0.3 to 0.9 V

for the charge-pump output currents 50 µA and 100 µA respectively.

−

+

Vdd

Iup

Icp

Vdd

Vdd

Vdd

IdnM1M2 M3

M4

M5

M6M7

UPUPB

DNDNB

CP

Isource

10 uA

10 uA

1 : 1

1 : K

1 : K

VCOcontrol voltage

(a) Current steering charge-pump. (b) Output current characteristics (K = 5 and 10).

Figure 5.23: Current steering charge-pump circuit used in the PLL and its measuredoutput current characteristics.

Pseudo-differential voltage controlled ring oscillator (VCO)

Fig. 5.24 shows the pseudo-differential ring oscillator circuit used in the PLL. The

VCO uses varactor and bias current tuning to generate frequencies in the range 783

to 850 MHz achieving a gain of 54 MHz/V. The digital edge combiner up-converts

the VCO output signals to a 2.35 - 2.55 GHz frequency range.


+ +

- -

Vctrl

Cvar

Cvar

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

C2 C3 C4 C5 C6C1

unit cell

A

B

C

Vdd Vdd Vdd Vdd Vdd Vdd

B0 B1 B5 M0 M1 M3

PVT calibration bits BFSK modulation control

Figure 5.24: Pseudo-differential voltage controlled ring oscillator circuit.

Figure 5.25: Measured VCO transfer characteristics (B5 to B0) in the up-converted2.4 GHz frequency band.

The varactor in the VCO is controlled using loop filter voltage during the PLL

closed operation for a stable and programmable frequency synthesis. The bias current

tuning using bits B5 to B0 allows for PVT calibration and M3 to M0 enables digital

frequency modulation with programmable frequency deviations. Fig. 5.25 shows the

measured VCO transfer characteristics in the up-converted 2.4 GHz frequency band,

for different combination of PVT calibration bit settings (B5 to B0).

Frequency synthesizer closed loop measurements

The frequency synthesizer shown in Fig. 5.20 is programmed to generate a 2.4 GHz

output signal from a 1.667 MHz reference source (N = 480 and M = 3).


(a) Frequency spectrum. (b) Phase noise characteristics.

Figure 5.26: PLL closed loop measurement results (fout = 2.4 GHz).

The charge-pump current is programmed to 100 µA. The loop filter parameters

are Rz = 60 kΩ, Cz = 200 pF, and Cp = 15.2 pF designed for a PLL loop bandwidth

of 100 KHz and phase margin of 60o.

Fig. 5.26a shows the measured frequency spectrum of 2.4 GHz signal generated

from the frequency synthesizer with the PLL operating in its closed loop and open

loop configurations. Fig. 5.26b shows the corresponding phase noise characteristics

of 2.4 GHz signal measured from the edge combiner output.

The frequency synthesizer achieves a phase noise of -96.01 dBc/Hz at 1 MHz offset

from a 2.4 GHz carrier, consuming 8.2 mA current from a 1.3 V supply voltage. The

measured phase noise performance is comparable with the other ring oscillator based

frequency synthesizer implementations reported in [33] and [49] targeting low-power,

relaxed performance requirement wireless standards and can be improved further by

burning additional power in the ring oscillator.

Digital edge combiner

A digital implementation of the frequency multiply by 3 (fout = 3∗fRO) edge combiner

is shown in Fig. 5.20. The edge combiner generates 2.4 GHz RF carrier by combining

the equally spaced 800 MHz signals tapped from different stages of voltage controlled

ring oscillator embedded in the PLL. The NAND and NOR gates in the edge combiner


are implemented using its standard implementation style as shown in Fig. 5.8a (W

= 3 µm).

(a) Power spectrum of 2.4 GHz frequency multiplied output signal.

(b) Transient waveform - 2.4 GHz. (c) Transient waveform - 2.5 GHz.

(d) Transient waveform - 2.4 GHz. (e) Transient waveform - 2.5 GHz.

Figure 5.27: Digital edge combiner - measurement results.


Fig. 5.27a shows the measured frequency spectrum of a 2.4 GHz frequency multi-

plied output signal generated from the digital edge combiner. The broadband spurs

at harmonics of 800 MHz in the frequency spectrum are large, mainly due to the use

of standard implementation for digital logic gates which created unequal path delays

in the edge combiner design. As a result, a degraded CSR performance of 24.01 dB

was observed in the measurements.

Fig. 5.27b & c shows the measured transient waveforms of 2.4 GHz and 2.5 GHz

frequency multiplied output signals generated by the edge combiner. The frequency

multiplied 2.4 GHz and 2.5 GHz transient waveforms exhibited a beat tone at its

input frequencies 800 MHz (Fig. 5.27b) and 833.33 MHz (Fig. 5.27c) respectively,

due to the unequal path delays in the edge combiner design. The average frequencies

of the measured transient waveforms from the edge combiner are at 3 ∗ fRO, how-

ever, their jitter and broadband spur performance are degraded due to its non-ideal

implementation.

Performance comparison

Two PLLs with and without edge combiner circuits are designed and fabricated to

demonstrate power efficiency of the frequency multiplication technique.

• P LL1 : 800 MHz PLL with edge combiner circuits to generate 2.4 GHz RF

carrier (Fig.6.2a).

• P LL2 : 2.4 GHz PLL without edge combiner (different chip under the same

process technology, Fig.6.2b).

The 800 MHz VCO and edge combiner circuits in P LL1 are replaced with a 2.4

GHz VCO in P LL2, having all the other components identical. Fig. 5.27d & e

compares the transient waveforms measured from P LL1 and P LL2, at 2.4 GHz and

2.5 GHz frequencies, respectively.

P LL1 (10.7 mW) is power efficient than P LL2 (20.3 mW), because the VCO and

divider circuits operate at a lower frequency of 800 MHz in P LL1, whereas at 2.4 GHz


Table 5.4: Frequency Multiplication Performance Comparison

[32] [33] [35]This Work

800 MHz 2.4 GHzPLL + EC PLL

Process, (µm)0.35 0.24 0.13 0.13 0.13

CMOS CMOS CMOS CMOS CMOSVdd, (V) 3.3 1.5 1.2 1.3 1.3

Architecture LC LC LC Digital logic -Fout, (GHz) 0.9 0.9 0.4 2.4 2.4

PN, (dBc/Hz)-127 @ -94 @ -105.2 @ -96.01 @ -91.48 @

330 KHz 1 MHz 1 MHz 1 MHz 1 MHzCSR, (dB) 30 40 44.4 24.01 -

Power, (mW) 130 - 0.09a 10.7b 20.3c

Area, (mm2) 1.2 0.2 0.04 0.33 0.32aInjection locked ring oscillator and EC with off-chip LC-tank load.b(VCO+EC+Buff) = 8.4 mW and (PFD+CP+Divider+Buff) = 2.3 mW.c(VCO+Buff) = 13.7 mW and (PFD+CP+Divider+Buff) = 6.6 mW.

in P LL2. However, P LL1 suffers from broadband spurs generated primarily due to the

use of standard implementation (Fig. 5.8a) for digital logic gates in the edge combiner

design, whereas P LL2 does not have these spurs (trade-off in spectral purity). The

power numbers reported include the power consumption from buffers and other I/O

drivers integrated on-chip. Table 5.4 summarizes the measured performance of two

PLLs and its performance comparison with other reported frequency multiplication

circuit techniques.

Discussion on CSR performance

Chien et al. in [32] demonstrated a differential amplifier based frequency multi-

plier for LO generation in 900 MHz transceivers targeting PCS applications (IS-137

AMPS/TDMA dual-mode standard) with a CSR of 30 dB. However, the DC tail

current sources used in all the differential pairs lead to an increased static power

consumption in this technique and hence incurs a large power overhead with narrow

band operation.

In [33] & [49], Verma and Lee performed frequency multiplication by extracting

5.9. Summary 112

the M th harmonic of a low frequency signal (fRO) from a M-stage ring oscillator using

an LC-resonator tuned to a frequency of M ∗ fRO. However, this technique suffers

from poor output voltage swing (less than 1/10th of supply voltage) and amplifying

a high frequency LO signal is costly both in terms of area and power. The prototype

demonstrated a LO generation for Zig-bee and cable replacement applications, and

also suggested to use band-preselect filtering in the architecture to avoid out-of-band

interference effects [33].

[35] uses MOS switches to perform frequency multiplication and demonstrated

a low power 400 MHz transmitter design targeting MICS band. However, the pre-

sented architecture has the drawbacks of single channel operation with low data-rate

transmission, off-chip LC components and also suffers from poor frequency accuracy

(modulation performed by pulling crystal frequency).

The presented multiply by 3 digital frequency multiplier in this work offers broad-

band operation with low power and low area implementation advantages, and also

benefits from the CMOS technology scaling. A CSR performance of above 40 dB can

be easily achieved in the proposed frequency multiplier design by using symmetric

logic gates in the edge combiner design, following careful layout practices, by increas-

ing the transistor dimensions in both VCO and edge combiner designs, or by using

low threshold voltage and high fT devices with improved matching performance.

5.9 Summary

We have presented a digital frequency multiplier design for low power frequency syn-

thesis in the relaxed performance, short distance wireless communication applications.

The proposed digital frequency multiplier design offers a broadband operation with

low power and low area implementation advantages compared to the reported analog

implementations. Moreover, the digital frequency multiplier implementation benefits

from the improved performance of digital circuits in the nano-meter CMOS process

5.9. Summary 113

technologies.

The power savings advantage of the proposed frequency synthesizer design was

demonstrated through measured performance from two PLL chips with and without

digital frequency multiplier circuits implemented in 0.13 µm CMOS process. The

implemented 2.4 GHz frequency synthesizer prototype using the proposed digital fre-

quency multiplier design exhibited improved power savings in frequency synthesis op-

eration. However, the prototype suffers from degraded broadband spur performance

with a measured CSR of 24.01dB, which is primarily due to the mismatch in the edge

combiner parallel paths created primarily due to the use of standard implementation

of digital logic gates in it design.

The presented frequency multiply by 3 digital edge combiner design using sym-

metric logic gates can easily achieve a CSR of 40 dB as demonstrated through various

simulations. Careful layout practices, larger transistor dimensions, lower threshold

voltage devices and implementation using advanced technology node devices (65nm

or less) further improves its CSR performance (in the order of 50 dB).

Therefore, the presented frequency multiply by 3 digital edge combiner can be

readily used for low power frequency synthesis in relaxed performance wireless com-

munication applications such as Zero-G (cable replacement technology [49]), PCS (30

dB), Zig-Bee and MICS (45 dB).

Chapter 6

2.4 GHz BFSK/ASK Transmitter

In this chapter, we present a custom designed energy efficient 2.4 GHz BFSK/ASK

transmitter architecture using the proposed low power frequency synthesizer design

technique and a class-D power amplifier. Chip prototype of the proposed transmitter

design is implemented in 0.13 µm CMOS technology. The transmitter achieves energy

efficiencies of 0.91 nJ/bit and 6.1 nJ/bit for ASK and BFSK modulations with data

rates 20Mb/s & 3Mb/s respectively, consuming 14 mA current from a 1.3 V supply

voltage.

6.1 Introduction

A low power, fully integrated radio-on-a-chip (RoC) is essential for short distance,

battery operated wireless communication applications such as body area networks and

wireless sensor networks. The rising number of new applications with an increased

density of sensor nodes demand energy efficient and performance efficient sensor node

implementations for its long duration of operation.

The RF transmitter and frequency synthesizer circuits in these sensor nodes typ-

ically consume a significant percentage of its total power due to its high frequency

of operation [4] [7]. The frequency synthesizer circuits in these applications are usu-

ally shared between transmitter and receiver circuits to minimize the overall system

power consumption. The transmitter circuits are typically realized using PLL based

architectures in these applications due to its simpler design, fully integrated solution,

low power and low area implementation advantages [8] [9] [10] [11].

The high density of sensor nodes and its various performance requirements such

as low power consumption, single chip solution, high data-rate transmission, and long

114

6.2. Energy Efficient Transmitter Architecture 115

duration operation presents several design challenges for the transmitter circuits in

these applications.

In this chapter, we present a custom designed energy efficient 2.4 GHz BFSK/ASK

transmitter architecture targeting these relaxed performance sensor network applica-

tions. The transmitter uses the low power frequency synthesizer design technique

presented in Chapter 5 to achieve an improved energy efficiency. The spectral perfor-

mance improvement techniques presented in Chapters 3 & 4 are also been used in the

transmitter design to reduce the magnitude of spurious tones in its output frequency

spectrum.

6.2 Energy Efficient Transmitter Architecture−

+

PFD

VCO

Iref

Rz

Cz

Cp

UP

UPB

DN

DNB

VCO Control Voltage

Iup

Idn

Ffb

Fref

+

-C1

+

-Cn-1

+

-Cn

CP

LPF

+

+

-

-

VCO Control Voltage

VCO Unit Cell

Cvar

Cvar

Vdd Vdd Vdd

M0 M1 M3

BFSK Modulation Control

Edge

AB BC CA

A

B

C

PA

ASKModulation

ProgrammableDivider

2.4 GHz

PLL - 800 MHz

Combiner

Control

(AB + BC + CA)

PA

(Frequency Synthesis)

(Class - D)

Vdd Vdd Vdd

B0 B1 B5

PVT Calibration Control

Equally spaced 800 MHzsignals from VCO

+

-

+

-

+

-

Vdd Vdd

Reference spur suppression

circuits

Figure 6.1: Low power 2.4 GHz BFSK/ASK PLL-based transmitter architecture.

Fig. 6.1 shows the block level description of the proposed 2.4 GHz BFSK/ASK

transmitter architecture suitable for short distance, relaxed performance communica-

tion applications. The transmitter building blocks are integer-N charge-pump PLL,

6.3. Frequency Synthesizer 116

digital edge combiner, reference spur suppression circuits, and a class-D power am-

plifier (PA).

The PLL operates at a lower frequency of 800 MHz to minimize the power con-

sumption from its VCO and divider circuits. A frequency multiply by 3 digital edge

combiner generates the up-converted 2.4 GHz RF carrier by combining the equally

spaced 800 MHz signals tapped from different stages of a ring oscillator VCO embed-

ded in the PLL. A class-D power amplifier (PA) drives the 50Ω antenna load and the

pulse width modulation (PWM) of RF carrier is used to control the output power

delivered by the power amplifier.

The reference spur suppression circuits discussed in Chapter 3 are used in the

proposed transmitter architecture to minimize the magnitude of spurious tones at

reference frequency offsets, thereby reducing the in-band interference effects in the

communication system performance.

The BFSK modulation is done in PLL, by directly modulating the VCO with a

Manchester encoded data (to remove the loop BW effects) and the ASK modulation

is performed by directly modulating the PWM control voltage of the power amplifier.

The prototype of the proposed transmitter architecture is implemented in UMC

0.13 µm Mixed-Mode and RF CMOS 1.2V/3.3V 1P8M process. The TX occupies an

on-chip area of 0.4 mm2. Fig. 6.2 shows the chip micro-graph of the transmitter and

the test setup used in the measurements.

6.3 Frequency Synthesizer

The proposed transmitter architecture achieves an improved energy efficiency per-

formance by minimizing the power consumption in its frequency synthesizer circuits.

The block level description of the frequency synthesizer circuit used in the transmit-

ter for 2.4 GHz carrier generation is shown in Fig. 6.1. The frequency synthesizer

consists of three main building blocks: low frequency PLL, a digital edge combiner,



(c) Test setup used in the measurements.

Figure 6.2: Chip micro-graph in 0.13 µm CMOS process and the test setup used inmeasurements.

and reference spur suppression circuits. The description, design and measured perfor-

mance of these circuits are presented in detail in Chapters 3,4, & 5. In this section,

we summarize the design details and measured performance of these circuits.

6.3.1 Phase locked loop

The PLL uses a type II, 3rd order integer-N charge-pump based architecture as shown

in Fig. 6.1. The low frequency PLL generates 800 MHz modulated signals from a


1.667 MHz reference frequency to have a channel spacing of 5 MHz in the up-converted

2.4 GHz frequency band. The description of PLL blocks are as follows,

• Phase frequency detector - The PFD is implemented using a standard tri-state

dead-zone free phase detector architecture.

• Charge-pump - A current steering charge-pump circuit is used to source or sink

programmable currents in the range 3 µA to 100 µA from a reference current

source of 10 µA. Nominal CP output currents of 50 µA & 100 µA are used in

the PLL design.

• Loop filter - The loop filter parameters are Rz = 60 kΩ, Cz = 200 pF, and Cp =

15.2 pF designed for a loop BW of 100 KHz and phase margin of 60o. The loop

filter capacitors are implemented using gate capacitance of NMOS transistors

to reduce the area occupied by large capacitors on-chip.

• VCO - A pseudo differential voltage controlled ring oscillator (VCO) with var-

actor and bias current tuning is used in the PLL to generate frequencies in the

range 783 MHz to 850 MHz achieving a gain of 54 MHz/V.

• Divider - The frequency divider in the PLL feedback path is implemented using

standard digital down counter circuits.

6.3.2 Digital edge combiner

A frequency multiply by 3 digital edge combiner (fout = 3 ∗ fRO) implemented using

conventional digital logic gates having an unit transistor width of 3 µm is used to

generate the 2.4 GHz RF carrier by combining the equally spaced 800 MHz signals

tapped from different stages of ring oscillator VCO embedded in the PLL.

Fig. 6.3, 6.4, & 6.5 shows the performances of the frequency synthesizer circuits

measured from the test chip. Table 6.1 presents the performance summary of the

proposed frequency synthesizer design.


(a) CP output current characteristics. (b) VCO transfer characteristics (B5 to B0).

Figure 6.3: Charge-pump and VCO measurements.

(a) Frequency spectrum. (b) Phase noise characteristics.

Figure 6.4: PLL closed loop - measured results (fout = 2.4 GHz).

(a) Frequency multiplied output signal. (b) Frequency spectrum, span = 4.5 GHz.

Figure 6.5: Digital edge combiner - measured results (fout = 2.4 GHz).


Table 6.1: Frequency synthesizer performance summary.

800 MHz PLL + EC 2.4 GHz PLLSimulation Measured Measured

Process, (µm) 0.13 0.13 0.13Vdd, (V ) 1.2 1.3 1.3

Frequency, (GHz) 2.4 2.4 2.4Power, (mW)PFD + CP +

2.1 2.3 6.6Divider + BuffersVCO + Buffers 7.575a 8.4 b 13.7

PLL (total power), (mW) 9.675 10.7 20.3Phase noise of VCO

-91.79 -96.01 -91.48@ 1 MHz offset, (dBc/Hz)

CSR, (dB) 40 c 24.01 d -Area, (mm2) 0.33 0.33 0.32

aVCO = 3.475 mW, I/O buffers = 4.1 mWbincludes power consumption from I/O bufferscUsed symmetric implementation for logic gates in EC design.dUsed standard implementation for logic gates in EC design.

The non-ideal effects in the edge combiner design create unequal path delays in

its implementation and introduce broadband spurs in the frequency spectrum of edge

combiner output signal as shown in Fig. 6.5b. In the case of transmitter applications,

these broadband spurs form out-of-band interference sources and hence, its magni-

tudes must be kept below the PSD mask specifications of a wireless standard. The

relaxed performance short distance wireless communication applications such as PCS,

Zig-bee or MICS demand a CSR performance of 30 dB and 45 dB respectively.

The measured CSR performance from the implemented frequency synthesizer pro-

totype is low (24.01 dB) due to the use of standard implementation for digital logic

gates in the EC design. A frequency multiply by 3 digital edge combiner with a fewer

number of logic gates, having symmetric implementation, can easily achieve a CSR

of 40 dB (worst case) and can be readily used in these custom designed transmitter

applications. A few design guidelines to further improve the CSR performance of the

digital edge combiner to the order of 50 dB are also presented in Chapter 5.


6.3.3 Reference spur suppression circuits

Severely deteriorated channel length modulation effect of nano-meter CMOS transis-

tors makes the charge-pump mismatch current a dominant source of reference spurs in

CP-PLLs [3]. These reference spurs affect the wireless communication performance

by introducing unwanted in-band interference signals and by down-converting the

interference signals present in the adjacent channel frequencies [1].

Table 6.2: Reference spur suppression performance summary.

Simulation MeasuredProcess, (µm) 0.13 0.13

Vdd, (V ) 1.2 1.3fout, (GHz) 2.4 2.4

PLL bandwidth, (KHz) 100 100CP output current, (µA) 55 55

CP mismatch current, (%)10 (loop disabled) 9.1 (loop disabled)0.5 (loop enabled) 0.55 a (loop enabled)

Reference spur, (dBc)-66.5 (loop disabled) -22.42 (loop disabled)-82 (loop enabled) -31.47b (loop enabled)

Static phase error, (ps) < ± 30c < ± 70d

a4-bit calibrationbdominated by parasitic coupling through substrate and supply in this implemen-

tation.cTP F D = 5 ns.dLimited due to the use of large PFD reset delay

The reference spur suppression block shown in Fig. 6.1 minimizes the charge-pump

mismatch current (∆I = Iup − Idn) by adaptively adjusting the body bias voltage of

PMOS transistors in the CP with respect to the VCO control voltage, and hence

minimizes the magnitude of reference spurs. The design and measured performance

of these circuits are presented in detail in Chapter 3. Table 6.2 summarizes the

measured performance of these circuits.

6.4. Class-D power amplifier 122

6.4 Class-D power amplifier

Switch mode power amplifiers are very attractive for constant envelope modulation

transmitters as they provide higher efficiency than linear PAs [102]. The Class D

power amplifiers have been traditionally used for its simpler implementation. Fig.

6.6 shows the schematic of class D power amplifier used in this work.

Vdd

Vdd

Vdd

Lb

Rload

Bond Wire

M1

M2

IN1

IN2

Final Stage

M5

M6

M7

M8

Vdd

RFin

M3

M4

Rd

Cd1

Cd2

Vcontrol

P

N

Driver stagePWM Control

L Cs

CESD

C1

5 nH5 nH

340 fF 50Ω

1 pF

Figure 6.6: Class-D power amplifier.

Figure 6.7: Measured PA output power (50Ω load) Vs PWM control voltage.

The PA consists of three stages: pulse width modulator (PWM, combination of

Rd, Cd1, and Cd2 shown in Fig. 6.6) to vary the output power level, high side & low

side driver buffers to drive PMOS & NMOS transistors in the final stage and a class-

D output driver (M1 and M2) with matching network. The PA provides continuous

6.5. Transmitter Modulation and Transmission Performance 123

Figure 6.8: Measured S22 at the output of PA.

output power control with a constant supply voltage through PWM and a reduced

DC power consumption at lower output power levels.

The PA was designed to have 0 dBm output power with a simulated efficiency of

23%. Fig. 6.7 shows the measured output power of PA (-9.6 dBm to -26 dBm) as

a function of PWM control voltage. The measured power levels are low due to the

parasitical effect of bond-wires, ESD capacitance and the PCB track. Fig. 6.8 shows

the S22 characteristics measured from the output of power amplifier. The measured

S22 at 2.4 GHz is -6.15 dB.

A power amplifier design with high power efficiency is essential for an energy

efficient transmitter implementation. In this work, we mainly focus on the frequency

synthesizer circuits to improve the performance of transmitters. Therefore, we have

used a conventional and a relatively simple power amplifier design to demonstrate the

transmitter operation.

6.5 Transmitter Modulation and Transmission Performance

The proposed transmitter architecture is verified with BFSK and ASK modulation

schemes. The BFSK modulation is performed by directly modulating the VCO with

a Manchester encoded data. The modulation control bits (M3 to M0) in the VCO

provide programmable frequency deviations of 500 KHz, 800 KHz and 1.2 MHz for


BFSK modulation. Fig. 6.9b shows the measured BFSK modulation spectrum for

a data rate of 1 Mb/s with the carrier frequency and frequency deviation set to 2.4

GHz and 1.2 MHz respectively.

(a) Transmission quality of BFSK modulated RF carrier.

(b) BFSK modulation spectrum. (c) FSK error Vs modulation data rate.

Figure 6.9: BFSK modulation performance for "1010" data pattern measured usingvector signal analyzer (VSA).

Fig. 6.9a shows the transmission quality of the BFSK modulated RF carrier with a

data rate of 1 Mb/s, measured using the vector signal analyzer (VSA). The measured


FSK error is 3.33 % and the corresponding BER is less than 10−3. The FSK error can

be minimized by increasing the frequency deviation or by reducing the data rate [40].

Fig. 6.9c shows the measured FSK error versus transmission data rate, with the

frequency deviations set to 500 KHz, 800 KHz and 1.2 MHz. A maximum data rate

of 3 Mb/s with a 6.61% FSK error was measured for the BFSK modulation with a

frequency deviation of 1.2 MHz and 2.4 GHz RF carrier.

(a) Data rate = 4 Mb/s. (b) Data rate = 10 Mb/s.

(c) Data rate = 20 Mb/s.

Figure 6.10: Measured ASK transient waveform from TX using "1010" data pattern.

Amplitude shift keying (ASK) modulation is performed by directly modulating

the PWM control voltage of the power amplifier with the digital base-band data.

Fig. 6.10a,b, & c shows the ASK modulated transient waveforms measured from the

power amplifier output with the data rates 4, 10, & 20 Mb/s respectively. The rise

and fall times of ASK modulated carrier envelope are less than 10 ns for an amplitude


change of 150 mV.

The transmitter consumes 14 mA current (including I/O buffers) from a 1.3 V

supply voltage and occupies an area of 0.4 mm2. Table 6.3 & 6.4 present the summary

of measured performance from the transmitter and its comparison with other designs

reported in the literature.

The BFSK modulation is performed in the PLL. The low power frequency synthe-

sizer design using frequency multiplication technique primarily improves the BFSK

modulator efficiency. The performance of modulators are compared using the follow-

ing modulator efficiency figure of merit [38],

Modulator efficiency, (nJ/bit) =Modulator power consumption

Data rate(6.1)

The measured BFSK modulator efficiency is 3.6 nJ/bit. The improved modulator

performance is primarily due to the power savings in the frequency synthesizer design

using frequency multiplication technique.

The performance of transmitters are evaluated based on the following figure of

merit (FOM) [106] [107],

FOM, (nJ/bit) =TX power consumption

Data rate(6.2)

FOM in Eqn. 6.2 defines the energy efficiency of a transmitter and is equal to

the average amount of energy required to transmit a single bit of data. The energy

efficiency (FOM) measured from the transmitter prototype are 0.91 nJ/bit and 6.1

nJ/bit for ASK and BFSK modulations with data rates 20Mb/s & 3Mb/s respectively.

The maximum output power measured from power amplifier is -9.6 dBm. The

normalized energy efficiencies of TX with the transmitting power (F OMPout

) are 55

nJ/bit.mW for BFSK and 8.3 nJ/bit.mW for ASK modulations. The normalized

energy efficiencies are degraded due to the poor impedance matching characteristics

and the low output power levels measured from the power amplifier.

6.5

.T

ransm

itterM

odulatio

nan

dT

ransm

ission

Perfo

rman

ce127

Table 6.3: Transmitter Performance Comparison - BFSK.[40] [17] [38] [10] [11] [103] [8]

This workESSCIRC CICC TVLSI CICC A-SSCC TVLSI RFIC

Process, (µm) 0.18 0.18 0.18 0.15 0.18 0.18 0.13 0.13Supply voltage, (V ) 1.5 1 1.8 1.5 1.55 1.8 1.8 1.2 1.3TX power, (mW ) 19.5 22.9 9.2 8.53 18 41.22 17 18.2a

Data rate, (Mb/s) 1.5 2 10 2 2 1 2 3Frequency, (GHz) 0.402 2.4 2.4 2.4 2.4 2.4 2.4 2.4

Phase -110.12 -99 -112 -107.5 -109 -108 -120 -96.01noise, (dBc/Hz) @ 1 MHz @ 1 MHz @ 500 KHz @ 1 MHz @ 1 MHz @ 1 MHz @ 3.5 MHz @ 1 MHz

Pout, (dBm) -9 4 -28 - 0 0.1 -2 -9.6TX area, (mm2) 1.57 - 0.1 0.88 1 0.8 0.6 0.4

Modulator6.53 2.34 0.92 1.78 6.48 - 6.25 3.6

efficiency b, (nJ/bit)FOMc, (nJ/bit) 13 5.725 0.92 2.13 9 41.22 8.5 6.1

aFrequency synthesizer = 10.7 mW and PA = 7.5 mW.bModulator efficiency, (nJ/bit) = Modulator power consumption

Data ratecFOM, (nJ/bit) = T X power consumption

Data rate

6.6. Summary 128

Table 6.4: Transmitter Performance Comparison - ASK.[104] [105]

This workVLSI-C JSSC

Process, (µm) 0.13 0.18 0.13Supply voltage, (V ) 0.65 1.4 1.3TX power, (mW ) 1.35 3.8 to 0.91 18.2a

Data rate, (Mb/s) 0.33 1 20Frequency, (GHz) 1.9 0.917 2.4

Phase -124 -114.3 -96.01noise, (dBc/Hz) @ 100 KHz @ 1 MHz @ 1 MHz

Pout, (dBm) 0.8 -11.4 to -2.2 -9.6TX area, (mm2) 0.96 0.27 0.4FOMb, (nJ/bit) 4.1 3.8 to 9.1 0.91

aFrequency synthesizer = 10.7 mW and PA = 7.5 mW.bFOM, (nJ/bit) = T X power consumption

Data rate

6.6 Summary

We have presented a custom designed energy efficient 2.4 GHz BFSK/ASK modu-

lation PLL based transmitter design suitable for short distance relaxed performance

wireless communication applications. The proposed transmitter architecture achieves

an improved energy efficiency performance by minimizing the power consumption of

its frequency synthesizer circuits using a digital frequency multiplication technique.

Reference spur suppression circuits are also used to improve the spectral performance

of the proposed transmitter.

Chip prototype of the proposed transmitter design is implemented in 0.13 µm

CMOS technology and its performance is verified for BFSK and ASK modulation

schemes. The transmitter achieves energy efficiencies of 0.91 nJ/bit and 6.1 nJ/bit

for ASK and BFSK modulations with data rates 20Mb/s & 3Mb/s respectively, con-

suming 14 mA current from a 1.3 V supply voltage.

Chapter 7

Conclusion and Future Works

7.1 Conclusion

In recent years, there has been a huge rise in interest in the short distance wireless

communication applications such as Internet of Things (IoT), health monitoring with

wearable technology, air pollution and water quality monitoring, and traffic monitor-

ing. The number of sensor nodes in these applications has also increased tremendously

in the order of few hundreds in a short period of time.

The RF transmitter circuits form a key component of these sensor nodes. The

transmitter circuits are typically realized using PLL based architectures in these sen-

sor network applications due to its simpler design, fully integrated solution, low power

and low area implementation advantages. The growing demands of sensor network

applications such as longer duration of operation, larger number of sensor nodes,

and single chip solution of sensor nodes presents several design challenges for these

PLL based transmitters such as low power implementation, high data-rates, improved

spectral performance, and fully integrated single chip solution.

This thesis focuses on the low power design techniques and spectral performance

improvement techniques for the PLL based transmitters targeting relaxed perfor-

mance, short distance, battery operated wireless communication applications.

Spectral performance improvement techniques

The non-ideal effects in the PLL implementation or the parasitic coupling from other

circuits integrated on the same chip introduces spurious tones in the frequency spec-

trum of PLL output signal. In transmitter applications, these spurious tones form

129

7.1. Conclusion 130

unwanted interference signals affecting the performance of communication systems

present nearby. When shared with receiver for LO generation, these spurious tones

down converts the unwanted interference signals and affects the system BER perfor-

mance.

The charge-pump mismatch current is a dominant source of reference spurs in

the nano-meter CMOS PLL implementations, due to its worsened channel length

modulation effect. In this work, we have presented a charge-pump mismatch current

calibration technique using an adaptive body bias tuning of its PMOS transistors

with respect to the VCO control voltage. The proposed technique compensates for

the DC current mismatch and the mismatch due to channel length modulation ef-

fect in the charge-pump, and hence improves the performance of CP-PLLs in these

implementations.

Measurements from a test chip fabricated in UMC 0.13 µm CMOS process show

an improved charge-pump current matching characteristics using the proposed cali-

bration technique with a CP mismatch current of less than 0.3 µA (0.55 %) over the

VCO control voltage range of 0.3 V to 1 V. The closed loop PLL measurements using

the proposed technique show a ≃9 dB improvement in the reference spur performance

and a reduced static phase error of within ±70 ps across the output frequency range

2.4 - 2.5 GHz.

A single chip solution of sensor nodes with its analog (transmitter & receiver

circuits, voltage reference circuits) and digital (micro-controller or DSP, and ADC’s)

circuits integrated on the same die is preferred for its low power, low cost, and reduced

size implementation. The parasitic interactions between these analog and digital sub-

systems integrated on the same substrate degrades the performance of analog circuits.

The digital buffers in a clock distribution network usually have very large drive

strengths and hence inject a significant amount of periodic switching noise currents

in the substrate. The periodic voltage fluctuations generated in the common sub-

strate couple to the sensitive nodes of a charge-pump PLL, frequency modulates the

7.1. Conclusion 131

VCO, and introduces spurious tones in the frequency spectrum of PLL output signal.

Thereby affecting the transmitter and receiver performance.

In this work, we experimentally demonstrated the effects of periodic switching

noise generated from the digital buffers on the performance of charge-pump PLLs.

The sensitivity of PLL performance metrics such as output spur level, phase noise,

and peak-peak deterministic period jitter are monitored against the variations in the

properties of a noise injector digital signal. Measurements from a test chip fabricated

in UMC 0.13 µm CMOS process shows that a pulsed noise injection with the duty

cycle of noise injector signal reduced from 50% to 20%, resulted in a 12.53 dB reduc-

tion in its output spur level and a 107 ps reduction in its Pk-Pk deterministic period

jitter performance.





Low power design techniques

Synthesis of RF carrier signal (in transmitter) and local oscillator signal (in receiver)

in any Radio-on-Chip consume a significant percentage of its total power. The fre-

quency multiplication based PLL architectures reduce the frequency of operation of

VCO and divider circuits and hence result in a huge power savings in its design.

In this work, we have presented a digital frequency multiplier design for low power

frequency synthesis in the relaxed performance, short distance wireless communica-

tion applications. The digital implementation of frequency multiplier circuits of-

fer a broadband operation with low power and low area implementation advantages

compared to the reported analog techniques. Moreover, the digital implementation

benefits from the improved performance of digital circuits in the nano-meter CMOS

7.1. Conclusion 132

process technologies.

Chip prototypes of 2.4 GHz CP-PLLs with and without digital frequency multi-

plier circuits are fabricated in UMC 0.13 µm CMOS technology. The 2.4 GHz PLL

using the proposed digital frequency multiplication technique (10.7 mW) consumed

a much reduced power compared to a conventional implementation (20.3 mW). How-

ever, the implemented low power PLL prototype suffers from poor broadband spur

performances generated due to the non-ideal implementation of the proposed digital

edge combiner circuits.

Techniques to improve the spectral performance of the proposed frequency mul-

tiplier design with a CSR of above 30 dB for PCS and above 45 dB for Zig-Bee

and MICS applications are also demonstrated in this work. The presented multiply

by 3 digital frequency multiplier design with a very few logic gates having circuits

with symmetric implementation can easily achieve a CSR of greater than 40 dB as

demonstrated through various simulations. Careful layout practices, larger transistor

dimensions, lower threshold voltage devices (VT ) and implementation using advanced

CMOS process devices (65nm or less) further improves its CSR performance to the

order of 50 dB.

Finally, we have presented a custom designed energy efficient 2.4 GHz BFSK/ASK

modulation, PLL based transmitter design suitable for short distance relaxed perfor-

mance wireless communication applications. The presented transmitter architecture

achieves an improved energy efficiency performance by minimizing the power con-

sumption of its frequency synthesizer circuits using the proposed digital frequency

multiplier circuits. A class-D power amplifier is used to drive the 50Ω antenna load.

Furthermore, reference spur suppression circuits are also used in the PLL to improve

the spectral performance of the transmitter.

Chip prototype of the proposed transmitter design is implemented in 0.13 µm

CMOS technology and its performance is verified for BFSK and ASK modulation

schemes. The transmitter achieves energy efficiencies of 0.91 nJ/bit and 6.1 nJ/bit

7.2. Future Directions 133

for ASK and BFSK modulations with data rates 20Mb/s & 3Mb/s respectively, con-

suming 14 mA current from a 1.3 V supply voltage.

7.2 Future Directions

In this thesis, we have proposed low power design techniques and spectral performance

improvement techniques in the frequency synthesizer circuits to achieve an energy

efficient transmitter operation. In the process, we have used a conventional and a

relatively simple class-D power amplifier design to drive the 50Ω antenna load and to

demonstrate the transmitter operation. An improved power amplifier design having

higher power efficiency will further enhance the energy efficiency performance of the

transmitter. Therefore, the power amplifier design used in the proposed transmitter

architecture requires further research to improve the overall energy efficiency of the

transmitter.

The fabricated chip prototypes of the proposed designs are operated with a supply

voltage of 1.3 V in the measurements. A lower supply voltage design for frequency

synthesizer and power amplifier circuits will reduce the overall power consumption

and further improve the energy efficiency performance of the transmitter. Therefore,

low voltage design techniques and implementations for these circuits must be looked

at to further improve the energy efficiency performance.

With the lower supply voltage operation, CP-PLLs suffers from several issues

including degraded charge-pump performance and limited VCO tuning range. An

all-digital PLL (ADPLL) architecture may help to solve these problems [108] [109].

With the improved performance of digital circuits in the nano-meter CMOS process

technologies, it will be valuable to look into the low-voltage and low-power design

techniques for ADPLLs, which may also help to improve the frequency synthesizer

performance with reduced on-chip area. Furthermore, a digital loop filter in ADPLL

is immune to the substrate coupling effects and hence improves the mixed signal

7.2. Future Directions 134

integration performance of the system.

The recent rise in interest in the bio-medical and IoT communication applications

demand ultra low power radio implementations for both short distance and long dis-

tance communication. A low power transmitter design without compromising on its

properties such as programmable channel frequency, and stable and accurate output

frequency along with multiple frequency band operation is quite challenging. The pro-

posed energy efficient transmitter design technique promises all the aforementioned

properties and therefore a good candidate for further studies.

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