Low Power Inter-Chip Wi l C i ti U iWireless Communication UsingInductive Coupling and Monocycle Signaling

Han, Sang WookGeonwook YooGeonwook YooDae Young Lee

Dec 3, 2007 Final Project 1EECS413 F07 Group4

IntroductionSystem-on-a-chip

IntroductionLogicM MSystem on a chip

Much time to developLow yield (high cost)

Logic

DR

AM

DR

AM

MPEGy ( g )

System-in-a-package

DSP MPU IO ROM

System in a packageWired interconnection Wireless interconnection

Wirebonding(Courtesy: Hynix)

Micro-bump3D-via

Capacitive coupling

2Dec 3, 2007 Final Project EECS413 F07 Group4

Overall Design & OperationOverall Design & Operation

CLK_TXTransmitter hi

p

DATA IN

Coupled

Tx C

hDATA_IN

I TX

D =

15µ

m

Coupled Inductors

ip

I_TX

I_RX

ReceiverDATA_OUT

CLK_RX

Rx

Chi

3Dec 3, 2007 Final Project EECS413 F07 Group4EECS413 F07 Group4

Monocycle SignalingMonocycle Signaling

1 2R k L LI ω=

22 2 2 21 2 1 2 1 2 1 2(1 ) ( )TV R R k L L L R R Lω ω⎡ ⎤− − + +⎣ ⎦

MonopulseMonocycle

4Dec 3, 2007 Final Project EECS413 F07 Group4EECS413 F07 Group4

Transmitter OperationTransmitter OperationCLK_TX

Pulse generator

123

A_I

N (V

)

V0

0 1 2 3 4 5 601

DA

TA

0123

_TX

(V)

DATA_IN /DATA_IN

I_TXV1

0 1 2 3 4 5 60

CLK

012

V 0 (V)

Pulse Delay & MUX H-Bridge 0 1 2 3 4 5 6

-2-10

V 1 (V)

3

4x 10

-4

X10 1 2 3 4 5 6

-202

x 10-4

I_TX

(A)

0

1

2

3

_TX

(A)

X2X4

0 1 2 3 4 5 6Time (ns)

* DATA_IN pulse train is pseudo-randomly generated byPerl script1.6 1.7 1.8 1.9 2

-3

-2

-1

I_

5

pTime (ns)

Dec 3, 2007 Final Project EECS413 F07 Group4EECS413 F07 Group4

Receiver OperationReceiver OperationI_RX

CLK_RX

reC

ense

V_biasP

r

Se

Sensing delay : 230 ps

SA_OUT1SA_OUT2

Sensing delay : 230 psOverall receiver delay :400 psMin. pulse width for I RX: 150ps

DATA_OUT/DATA_OUT

6Dec 3, 2007 Final Project

pu se d o _ 50ps

EECS413 F07 Group4

Corner simulation and BERCorner simulation and BER1.5

x 10-5

TT 0

1

TT_0SS_0SS_75FF_0FF_75

-2

10-1

0

0.5

X (A

)

10-3

102

ER

-0.5

0

I_R

X

10-4

BE

Minimum Current Level

SS corner-1

FF cornerSS corner

6

10-5

100 200 300 400 500 600 700 800-1.5

Time (ps)

Corner simulation Bit error rate

-5 0 5 1010

-6

Eb/N0 (dB)

7Dec 3, 2007 Final Project

Corner simulation Bit error rate

EECS413 F07 Group4

Coupled InductorsCoupled InductorsLayout Parameter Value

Distance (d) 15µm

Wire Width (w) 1µm

Wire Space (s) 0 5µmWire Space (s) 0.5µm

Diameter (l) 20µm

Turn (n) 3

Layer (m) 3

Extracted Parameters Value

L 1.8nH

R 240Ω

C 25fFC 25fF

k 0.312

M 0.542nH

8Dec 3, 2007 Final Project EECS413 F07 Group4

Frequency AnalysisFrequency Analysisx 10

-4

ModelS-parameter

0 2 0 25

2

(A)

0.1

0.15

0.2

) Mon

ocyc

le

0 1

0.15

0.2

0.25

) Mon

opul

se

0

1I_R

X

5 10 15 200

0.05

F (GH )

V_TX

(V)

5 10 15 200

0.05

0.1

Frequency (GHz)

V_TX

(V)

OptimalFreq.

109

1010

0

0.08

0.1

Frequency (GHz) Frequency (GHz)

1.5x 10

-5

cle 6

x 10-6

lseWorking

Freq

0 02

0.04

0.06

V_R

X (V

)

0.5

1R

X (A

) Mon

ocyc

2

3

4

5

RX

(A) M

onop

ulFreq.

109

1010

0

0.02

Frequency (Hz)

5 10 15 20

0

Frequency (GHz)

I_R

5 10 15 200

1

Frequency (GHz)

I_R

9Dec 3, 2007 Final Project EECS413 F07 Group4

LayoutLayout

20µm 20µm

Pulse Generator

H

RS latch

InPulse Delay &

MUX

H-Bridge

Back-to-back

inverters

IsolationFE

TIs

olat

ion

FET

(a) Transmitter (b) Receiver(a) Transmitter ( )

10Dec 3, 2007 Final Project EECS413 F07 Group4

PerformancePerformance10

00 Toshiba

NTT NECs=pJ

/b]

NTT

Hit hi

Keio ’04NECIntel TI

RambusFlexIO Fujitsuth

[mW

/Gb/

100

Parameter Value

Channel Bandwidth 1Gb/sHitachi

SunTeraChip

FlexIO Fujitsu

SFTKeio ’06 This

Workwer

/Ban

dwid

10 Channel Pitch 20µm

Power Dissipation 2.18mW

-Transmitter 0 87mWSFT Work

Pow 1

-Transmitter 0.87mW

-Receiver 1.31mW

Total Area 400µm2

Power/Bandwidth 2.18mW/Gb/s

Area/Bandwidth 400µm2/Gb/s

LVS & DRC clean&

11Dec 3, 2007 Final Project EECS413 F07 Group4

Thank youThank you.

12Dec 3, 2007 Final Project EECS413 F07 Group4