low-power low-noise cmos imager design

180
Low-Power Low-Noise CMOS Imager Design: in Micro-Digital Sun Sensor Application Proefschrift ter verkrijging van de graad van doctor aan de Technische Universiteit Delft, op gezag van de Rector Magnificus prof. ir. K.C.A.M. Luyben, voorzitter van het College voor Promoties, in het openbaar te verdedigen op maandag 2 juli 2012 om 12.30 uur door Ning XIE elektrotechnisch ingenieur geboren te Jilin, Jilin Province, P.R. China

Upload: others

Post on 11-Jan-2022

13 views

Category:

Documents


0 download

TRANSCRIPT

Page 1: Low-Power Low-Noise CMOS Imager Design

Low-Power Low-Noise CMOS Imager Design:

in Micro-Digital Sun Sensor Application

Proefschrift

ter verkrijging van de graad van doctor aan de Technische Universiteit Delft,

op gezag van de Rector Magnificus prof. ir. K.C.A.M. Luyben, voorzitter van het College voor Promoties,

in het openbaar te verdedigen

op maandag 2 juli 2012 om 12.30 uur

door

Ning XIE elektrotechnisch ingenieur

geboren te Jilin, Jilin Province, P.R. China

Page 2: Low-Power Low-Noise CMOS Imager Design

Dit proefschrift is goedgekeurd door de promotor: Prof. dr. ir. A.J.P. Theuwissen Samenstelling promotiecommissie: Rector Magnificus, voorzitter Prof. dr. ir. A.J.P. Theuwissen Technische Universiteit Delft, promotor Prof. dr. P.J. French Technische Universiteit Delft Prof.dr.ir. G. Meijer Technische Universiteit Delft Prof.dr. P. Magnan ISAE, Frankrijk Prof.dr.ir. R. Dekker Technische Universiteit Delft Dr. B. Buttgen MESA Imaging, Zwitserland Dr. M. Graef Technische Universiteit Delft Prof.dr.ir. H. Huijsing Technische Universiteit Delft,reservelid ISBN: 978-94-6191-348-7

Printed by: Ipskamp Drukkers B.V. Josink Maatweg 43 7545 PS Enschede The Netherlands Copyright © 2012 by Ning Xie Cover design: Yu Chen All rights reserved. No part of this publication may be reproduced or distributed in any form or by any means, or stored in a database or retrieval system, without the prior written permission of the author.

PRINTED IN THE NETHERLANDS

Page 3: Low-Power Low-Noise CMOS Imager Design

To my beloved parents and Yu

致我亲爱的父母和陈雨

Page 4: Low-Power Low-Noise CMOS Imager Design
Page 5: Low-Power Low-Noise CMOS Imager Design

I

Table of Contents Chapter 1 Introduction to Attitude Sensors and Digital Sun Sensors Applied for Micro-Satellites ...... 1

1.1 Introduction to attitude sensors ........................................................................ 3 1.1.1 Relative attitude sensors ............................................................................ 4 1.1.2 Absolute attitude sensors ........................................................................... 4

1.2 Micro-satellite requirements............................................................................. 6 1.3 Challenges and motivation of the µDSS .......................................................... 8 1.4 Thesis outline ................................................................................................... 9 1.5 References ...................................................................................................... 11

Chapter 2 Introduction to CMOS Image Sensors .... 13

2.1 Overview of solid-state image sensors........................................................... 14 2.2 Performance evaluation of CMOS image sensors.......................................... 16

2.2.1 Quantum efficiency and responsivity ...................................................... 16 2.2.2 Full well capacity, dynamic range and signal-to-noise ratio ................... 17 2.2.3 Conversion gain ....................................................................................... 19

2.3 Pixel architecture ............................................................................................ 20 2.4 Noise in CMOS image sensors....................................................................... 22 2.5 Analog processing chain in CMOS image sensors ........................................ 24 2.6 References ...................................................................................................... 25

Chapter 3 Overview of the Micro-Digital Sun Sensor...................................................................................... 27

3.1 Working principle of the Micro-Digital Sun Sensor ...................................... 28 3.1.1 Working principle.................................................................................... 28 3.1.2 Block diagram.......................................................................................... 29 3.1.3 Miniaturization of the μDSS.................................................................... 30 3.1.4 Optical design in the µDSS ..................................................................... 32

3.2 Overview of the incident angle determination ............................................... 33 3.2.1 Relation between the centroid location and sunlight incident angle ....... 33 3.2.2 Determination of the pixel array size....................................................... 34 3.2.3 Determination on the size of region of interest ....................................... 35

3.3 Overview of the centroiding algorithm .......................................................... 38

Page 6: Low-Power Low-Noise CMOS Imager Design

II

3.3.1 Introduction to the centroiding algorithm ................................................ 38 3.3.2 Noise effect from the Analog-to-Digital converter to the algorithm accuracy............................................................................................................. 39 3.3.3 An approach to reduce noise effect: the multiple-aperture digital sun sensor................................................................................................................. 41

3.4 Low power consumption approach by the APS+ ........................................... 43 3.4.1 Conventional detection method................................................................ 43 3.4.2 Acquisition-Tracking readout method ..................................................... 44 3.4.3 Albedo immunity with the acquisition-tracking method ......................... 45

3.5 Low noise approach by the APS+................................................................... 46 3.5.1 Conventional readout method .................................................................. 46 3.5.2 The proposed quadruple sampling method .............................................. 47

3.6 Radiation consideration in the APS+ design .................................................. 48 3.7 Summary......................................................................................................... 49 3.8 References....................................................................................................... 50

Chapter 4 Low-Power Approach to the APS+ ..........53

4.1 Introduction to Winner-Take-All (WTA) ....................................................... 54 4.1.1 Basic WTA principle................................................................................ 54 4.1.2 WTA in image sensor processing ............................................................ 55

4.2 Achieving profiling in the APS+ with the WTA principle ............................. 56 4.2.1 Pixel design principle required by the WTA............................................ 57 4.2.2 Complete pixel structure design for the APS+......................................... 58 4.2.3 Column profiling enabled by the specific pixel design............................ 60 4.2.4 Pixel modification for row profiling ........................................................ 63 4.2.5 Summary of pixel design and layout implementation.............................. 64 4.2.6 Profiling process in the sun acquisition mode.......................................... 67

4.3 Resolution of the WTA principle.................................................................... 69 4.3.1 Qualitative analysis of the resolution in the WTA circuit........................ 69 4.3.2 Analytical analysis of the resolution in the WTA circuit......................... 73

4.4 Profiling affected by the WTA resolution in the APS+.................................. 74 4.4.1 Profiling with several “winners” in competition...................................... 74 4.4.2 iscussion on the sunspot region in the APS+ ........................................... 78 4.4.3 Discussion on the dark region in the APS+ ............................................. 82 4.4.4 WTA resolution improvement ................................................................. 83

Page 7: Low-Power Low-Noise CMOS Imager Design

III

4.5 Summary ........................................................................................................ 84 4.6 References ...................................................................................................... 84

Chapter 5 Low-Noise Approach to the APS+........... 86 5.1 Reset noise in a 3-T APS pixel....................................................................... 87 5.2 Overview of the conventional readout method .............................................. 88 5.3 Overview of the quadruple sampling method ................................................ 91

5.3.1 Qualitative analysis.................................................................................. 91 5.3.2 Quantitative analysis................................................................................ 92 5.3.3 Measurement results ................................................................................ 94 5.3.4 The noise floor effect on algorithm accuracy .......................................... 94

5.4 Consideration of offset due to parasitic capacitors ........................................ 96 5.4.1 Motivation behind the parasitic capacitor consideration ......................... 96 5.4.2 Algorithm accuracy affected by the coupling capacitors ........................ 98 5.4.3 Layout modification for coupling capacitor reduction ............................ 99

5.5 Images captured by the APS+ ...................................................................... 100 5.6 Summary ...................................................................................................... 102 5.7 References .................................................................................................... 103

Chapter 6 APS+ Measurement Results................... 104 6.1 APS+ pixel characteristic measurements ..................................................... 105

6.1.1 Pixel output swing ................................................................................. 105 6.1.2 Photon Transfer Curve measurement .................................................... 106 6.1.3 Quantum efficiency measurement ......................................................... 110

6.2 APS+ function measurement in the acquisition-tracking operation............. 112 6.2.1 Working flow......................................................................................... 112 6.2.2 APS+ output window............................................................................. 112

6.3 Measurement results in the acquisition/tracking modes............................... 113 6.4 APS+ accuracy measurements ..................................................................... 116

6.4.1 APS+ centroiding accuracy at room temperature.................................. 116 6.4.2 APS+ noise at high temperatures........................................................... 117

6.5 APS+ power consumption measurements.................................................... 118 6.5.1 Power consumption of the APS+ at room temperature ......................... 118 6.5.2 Power consumption of the APS+ at high temperatures ......................... 120

6.6 Comparison with the state-of-the-art............................................................ 121 6.7 µDSS in-package.......................................................................................... 123

Page 8: Low-Power Low-Noise CMOS Imager Design

IV

6.7.1 The APS+ layout and chip micrograph.................................................. 123 6.7.2 The µDSS package................................................................................. 124

6.8 Conclusion .................................................................................................... 125 6.9 References..................................................................................................... 125

Chapter 7 Summary and Future Work.....................127 7.1 Summary....................................................................................................... 128 7.2 Future work................................................................................................... 129

7.2.1 4T pixel applied to APS+....................................................................... 129 7.2.2 Column ADC implementation ............................................................... 130 7.2.3 Optimized readout method by column ADC ......................................... 131 7.2.4 Further component integration............................................................... 132 7.2.5 Light intensity detection......................................................................... 133 7.2.6 Other potential applications with WTA technology .............................. 135

7.3 References..................................................................................................... 136

Summary....................................................................137 Samenvatting.............................................................143 Appendix ....................................................................149

A.1 The APS+ timing diagram in the acquisition and tracking mode................ 149 A.2 The calculation of offset due to parasitic bus capacitors ............................. 154

A.2.1 Case 1: “rst_sample” pulse comes first ................................................. 156 A.2.2 Case 2: “sig_sample” pulse comes first ................................................ 160

A.3 The APS+ application program ................................................................... 164

Abbreviations ............................................................166 Acknowledgements...................................................169 About the Author....................................................... 171

Page 9: Low-Power Low-Noise CMOS Imager Design

1

Chapter 1

Introduction to Attitude Sensors and Digital Sun Sensors Applied for Micro-Satellites

Page 10: Low-Power Low-Noise CMOS Imager Design

Introduction to attitude sensors and digital sun sensors applied for micro-satellite

2

In the twenty-first century, portable and wearable electronic devices are becoming increasingly more indispensable in our daily lives: from electronic consumer products such as smart phones and digital video cameras, to scientific and medical devices such as cardiac pacemakers and artificial retina vision chips. However, in all these applications, the limited battery capacity is a bottleneck: every device has to be recharged periodically, either by a cable or by a wireless recharger. In the future scenario, reliance on battery power could be eliminated by means of energy harvesting technology, which yields power from ambient sources such as solar power, thermal energy and kinetic energy. Supported by this technology, the operation of the devices can be completely autonomous. However, due to low conversion efficiency, energy harvesting can only be applied in low-power applications. Therefore, low-power design is extremely crucial for an autonomous system.

Besides low power consumption, low noise is another critical requirement for many electronic devices. Since noise introduces random disturbance to a useful information signal, it sets the fundamental limit of the detectable signal level in an electronic system. Therefore, noise performance needs to be optimized at the low-signal level for high-resolution applications.

Complementary Metal-Oxide-Semiconductor (CMOS) image sensors are the electronic transducers which convert optical signals into electronic signals by CMOS technology. They were invented in the 1960s, and have been developed rapidly over the last few decades. With the CMOS technology, CMOS imagers are able to integrate all functions onto a camera-on-chip and achieve low power consumption. In many battery-powered applications where endurance capability is limited by the battery capacity, power consumption needs to be as low as possible. For this reason, the CMOS imagers applied to cellular phones, PDAs and other portable devices should be optimized for power consumption. For many biomedical applications, low power is crucial for miniaturization. For instance, an endoscopy capsule, which records the image of a digestive tract, needs to be miniaturized in size in order to be swallowed by the patient. Thus, the CMOS imager used by the endoscopy capsule requires ultra-low power consumption in order to minimize the power supply, which limits the total size of the micro-system. In aerospace applications, the power budget is rigid because power is supplied by the limited solar cells mounted on the vehicle. Higher power consumption requires a larger

Page 11: Low-Power Low-Noise CMOS Imager Design

Introduction to attitude sensors and digital sun sensors applied for micro-satellite

3

solar cell, which increases both the total vehicle weight and size, thus leading to higher launching costs. Therefore, the low-power criterion is a design challenge for CMOS imagers used in aerospace application.

Besides power consumption, noise is another key characteristic of CMOS image sensors. The noise of a CMOS image limits the minimum signal it can detect. In order to improve image quality, dynamic range and signal-to-noise ratio need to be increased, both of which can be achieved by reducing the noise level. Thus, low-noise performance is critical especially for low-light and high-dynamic applications, for instance automotive driver assistant systems, night vision and medical imaging.

In this thesis, a specialized CMOS imager for digital sun-sensor application is presented. On the one hand, the low-power criterion is addressed in this application because the sun sensor is applied to a satellite, where the power budget is critical due to the limited capability of the solar cells which can be loaded. On the other hand, low noise is also required because the noise affects the desired accuracy specification. Thus, this CMOS image sensor is proposed as a test vehicle for the study of power and noise optimization.

In the rest of this chapter, since digital sun sensors form a category of attitude sensors, an overview of different types of attitude sensors is presented in the first section. In the second section, the specific requirements in micro-satellite application are discussed. It is concluded that among all attitude sensor architectures, the digital sun sensor is the best option for this application. The design challenges are discussed in the third section. Lastly, the organization of this thesis will be described.

1.1 Introduction to attitude sensors

For a spacecraft, its attitude information needs to be monitored during operation. This information is necessary for pointing the solar cell panels towards the sun, pointing the high gain antenna towards the earth, or acquiring the attitude for a payload which moves relative to the main spacecraft.

An attitude sensor determines a spacecraft’s current angular departure with respect to a defined frame of reference. There are two categories of attitude sensors based on different frames of reference: relative attitude sensors and absolute attitude sensors.

Page 12: Low-Power Low-Noise CMOS Imager Design

Introduction to attitude sensors and digital sun sensors applied for micro-satellite

4

1.1.1 Relative attitude sensors

The output of a relative attitude sensor reflects the attitude change with respect to an initial orientation. The most widely used relative attitude sensor is the gyroscope. It is a device which senses three-dimensional rotation without observing external objects. One type of gyro is the hemispherical resonator, which can be driven into oscillation. The orientation of the oscillation is fixed in inertial space. Thus, the motion of the vehicle with respect to the inertial space can be measured by detecting change in the oscillation orientation [1.1]. However, the gyro output is affected by drift and random noise; therefore, it needs to be corrected by an absolute attitude sensor. Meanwhile, its large size and heavy mass make it unsuitable for the space applications where mass is critical, e.g. a micro- or nano-satellite.

1.1.2 Absolute attitude sensors

Absolute attitude sensors detect a spacecraft’s orientation by sensing reference objects or fields which are outside the spacecraft. They are categorized by different references:

Earth horizon sensor is an optical instrument that senses infrared radiation from the earth’s surface. This sensor provides orientation with respect to the earth. It is less precise than sensors based on stellar observation. The accuracy differs from 0.1º in a near earth orbit to 0.01º in a Geostationary Earth Orbit (GEO). Its application is restricted to spacecraft with a circular orbit [1.2].

Magnetometer detects the strength of a magnetic field in one direction. Thus, three magnetometers are required for three-axis measurement. The sensed magnetic field strength and direction is compared to a map of the earth’s magnetic field, which is stored in the memory. Once the position of the vehicle is determined; its attitude can be inferred accordingly. The measurement inaccuracy is mainly introduced by the alignment error from mounting, and interference with electrical spacecraft activity. The accuracy varies from 0.5º to 3º in different positions in the magnetic field [1.3].

Sun sensor, which can also be called a sun tracker, uses the sun, which is the brightest star in the firmament, as the reference frame. The orientation of the spacecraft is detected by sensing the angular position with respect to the sun. Sun

Page 13: Low-Power Low-Noise CMOS Imager Design

Introduction to attitude sensors and digital sun sensors applied for micro-satellite

5

sensors are classified into two different conceptual categories based on their different detection methods: analog sun sensors and digital sun sensors.

An analog sun sensor uses the solar cells on the satellite as the detecting components. At a certain position in the orbit, the sunlight intensity illuminating the solar cells is not uniform. Thus, the currents from different solar panels differ. The orientation can be derived by monitoring the different currents [1.7]. The biggest advantage of analog sun sensors is that no additional hardware is needed on the spacecraft for attitude sensing. Therefore, it is very attractive in low-cost applications.

However, an analog sun sensor has some disadvantages. First of all, its accuracy is low. Usually an analog sun sensor consists of two to six solar panels. The sun angle is achieved based on only a couple of current outputs, thus the resolution is lower compared to other types of attitude sensors. Secondly, it is affected by the albedo effect. Albedo is sunlight reflected by the earth’s surface or sea surface that illuminates the sun sensor. The analog sun senor cannot distinguish sunlight from albedo light. Thus additional correction computation with an albedo model is required and is implemented by an on-board computer [1.8]. The need for an on-board computer also increases the total cost.

On the contrary, because of its specific architecture, a digital sun sensor inherently achieves both higher resolution than an analog sun sensor, and immunity to albedo. A digital sun sensor can be constructed with a pinhole camera. The sunlight illuminates a pixel array through a pin hole. Different pixels on the array are illuminated depending on the sunlight incident angle. The orientation information can be derived from the projective image on the detector’s plane. By using a large number of pixels on the array, digital sun sensors usually obtain much higher resolution than an analog sun sensor. Furthermore, since the albedo light intensity is several orders lower than the sunlight, the images projected by the albedo can be easily distinguished and discarded by the attitude computation in a digital sun sensor. In addition, another important advantage of a digital sun sensor is the possibility to make full use of the solid-state integrated circuit technology. It can be highly integrated with algorithm circuits and Analog-to-Digital converters (ADC) with CMOS technology. The detail of CMOS imaging technology will be discussed in Chapter 2.

Page 14: Low-Power Low-Noise CMOS Imager Design

Introduction to attitude sensors and digital sun sensors applied for micro-satellite

6

Star tracker is an optical device that images the position of stars. The orientation of the spacecraft is determined by comparing the star map, which is already known, with the stars observed by the star tracker. It achieves the highest accuracy among all types of attitude sensors.

The working principle of star trackers is similar to that of digital sun sensors. Their sensing components both are composed of a camera. The difference is that star tracker captures the image of stars instead of the sun. After the stars in the image are located and identified, the orientation of the spacecraft is determined by comparing the detected stars with a firmware star map. In this case, all the stars in the image are used for attitude calculation, thus the S/N ratio and accuracy are increased by statistical means. A star tracker is able to obtain an accuracy in the arcsecond range. A typical autonomous star tracker consumes 5~15Watts at an update rate of 0.5-10Hz. The mass is in the range of 1~7kg [1.6] [1.9] [1.10].

The accuracies achieved by the absolute attitude sensors above are summarized in Table 1.1. As can be seen, the star tracker is the most accurate amongst all sensors; the digital sun sensor and earth horizon sensor achieve medium accuracy; and the analog sun sensor and magnetometer have the lowest accuracy.

Table 1.1 Accuracy achieved by different types of absolute attitude sensors.

Type Accuracy

Earth horizon sensor 0.01º~0.1º [1.2]

Magnetometer 0.5º~3º [1.3]

Analog sun sensor 0.5º [1.4]

Digital sun sensor 0.1º [1.5]

Star tracker 1~20 arcseconds [1.6]

1.2 Micro-satellite requirements

The term “miniaturized satellites” refers to the artificial satellites which are characterized as being low weight and small in size, usually less than 500kg. Compared with the large satellites, which are heavier than 1000kg, miniaturized satellites have the advantage of being low cost: large satellites need large rockets for

Page 15: Low-Power Low-Noise CMOS Imager Design

Introduction to attitude sensors and digital sun sensors applied for micro-satellite

7

launching, while miniaturized satellites require smaller and cheaper launch vehicles. In addition, the design cost is greatly reduced by miniaturized satellites since they allow for mass production technology. Besides the cost issue, miniaturized satellites are able to accomplish missions that are impossible with large satellites: gathering data from multiple points in formation, in-orbit inspection of the large satellites, as well as scientific missions.

Micro-satellites constitute a specific category of miniaturized satellites with a wet mass between 10 to 100kg. Other categories include nano-satellites with a wet mass in the range of 1 to 10kg, and pico-satellites between 0.1 to 1kg. Although micro-satellites are classified by mass and size, they have the same advantages and design challenges as miniaturized satellites. The following discussion will be narrowed down to micro-satellites because they form the specific application of the proposed sensor design.

The major challenge for attitude sensor design on a micro-satellite is miniaturization. First of all, in order to reduce mass and weight, the attitude sensor should be as compact as possible so that less additional firmware is required. Secondly, it should also consume low power. Due to the limited satellite size, micro-satellites can only carry solar cells that are relatively small. Thus, the power consumption budget for the attitude sensor is rigid; it has to satisfy the function specifications such as resolution, accuracy, and the field of view with the lowest power consumption. The specifications for the demanding sun sensor are listed as below in Table 1.2 [1.11].

Table 1.2 Design specification.

Specification Number Unit

Size 51×51×14 3mm

Weight <30 grams

Power <100 mW

Field of view 47×47±2 degree

Accuracy 0.1 (3σ) degree

Page 16: Low-Power Low-Noise CMOS Imager Design

Introduction to attitude sensors and digital sun sensors applied for micro-satellite

8

Every attitude sensor structure introduced in the previous section has its own advantages and disadvantages with respect to the specifications in Table 1.2. The earth horizon sensor and magnetometer are both too large and too heavy to fit into a micro-satellite. Analog sun sensors cannot meet the accuracy requirements according to the accuracy performance listed in Table 1.1. Although the star tracker achieves the highest resolution, it consumes too much power due to its complicated algorithm. Thus, it is not suitable in this specific application. In the mean time, a digital sun sensor fulfills the requirements in all aspects of size, accuracy and power consumption. Therefore, it can be concluded that the best attitude sensor applied to this micro-satellite application is a digital sun sensor. This specific sun sensor, which has been optimized for this application, is called the micro-digital sun sensor (µDSS).

1.3 Challenges and motivation of the µDSS

Digital sun sensors have a development history of more than a decade. However, the µDSS design still faces many challenges in the aspects of power consumption and accuracy requirements.

In terms of power consumption, the most straightforward approaches to achieve low power could be employing a sensor driven by a low power supply or reducing the number of pixels of the sensor. The first generation of digital sun sensors had a 5V power supply [1.5]. In recent years, digital sun sensors tend to be powered by 3.3V for analog circuits and 1.8V for digital [1.12]. Besides the power supply, the number of pixels also affects the power consumption because a higher pixel count requires an increase in the bandwidth of the analog chain. However, reducing the pixel number is very unattractive for sun sensors because the number of pixels should be determined by the resolution specification. Therefore, a creative readout method needs to be proposed in order to lower the power consumption without reducing the pixel count.

Accuracy is another important performance parameter of sun sensors. It reflects how close the measurement data points tend to deviate from their mean value. In Table 1.2, accuracy is defined as three standard deviations (σ). High accuracy requires low noise. Unfortunately, every element in a measurement system introduces temporal noise which affects its accuracy, including the imager, the

Page 17: Low-Power Low-Noise CMOS Imager Design

Introduction to attitude sensors and digital sun sensors applied for micro-satellite

9

readout circuit, the algorithm circuit, and the ADC. Prior works have analyzed and studied the noise optimization of the analog circuits [1.14]. This thesis proposes a readout principle which suppresses the thermal noise from the image sensor.

In conclusion, the aim of this thesis is to design a low-power, low-noise µDSS in CMOS imaging technology. The approaches to this goal can be summarized by following three aspects:

• The key element of the µDSS system is a sensor chip named APS+. In order to achieve a miniaturized µDSS system, the APS+ integrates all the functions on a single chip. It has a light detector, an ADC, and an algorithm circuit integrated as a System-on-Chip (SoC).

• In order to reduce the power consumption, the APS+ adopts an acquisition-tracking operation mode. This operation is enabled by a Winner-Take-All (WTA) principle. A creative pixel design is proposed in order to realize the WTA principle.

• In order to reduce the thermal noise of the image sensor, a quadruple sampling is applied on the APS+. Thermal noise of the image sensor is greatly reduced by this method.

1.4 Thesis outline

This thesis consists of seven chapters. The outline is depicted in Figure 1.1.

Page 18: Low-Power Low-Noise CMOS Imager Design

Introduction to attitude sensors and digital sun sensors applied for micro-satellite

10

Figure 1.1 Thesis outline.

Chapter 2 briefly summarizes the background knowledge on CMOS image sensors. The sensor performance evaluation, pixel architectures and noise sources are discussed, and the analog signal processing chain is presented.

Chapter 3 discusses the working principle of the µDSS. It is composed of a sensor chip APS+, a membrane with a pinhole, and a communication block. This thesis mainly focuses on the design of the APS+. The APS+ is a complete autonomous sensor. It determines the centroid location of the projected sunlight image on the pixel array and outputs the coordinates.

Chapter 4 describes the low-power approach in the APS+ design. Low-power consumption is achieved by a two-step acquisition/tracking operation mode. The sensor first detects the coarse location of the projective image in the acquisition mode, then determines the fine centroid coordinates in the tracking mode. This low-power operation mode is enabled by a WTA principle, which is realized by a

Page 19: Low-Power Low-Noise CMOS Imager Design

Introduction to attitude sensors and digital sun sensors applied for micro-satellite

11

specific 3-T APS pixel design. With this pixel design, profiling can be achieved in an equivalent readout time for two lines. The reduction in readout load greatly reduces power consumption.

Chapter 5 describes the low-noise approach in the APS+ design. In order to reduce the reset noise and 1/f noise, which are the major noise sources in 3-T APS pixel, a quadruple sampling method is implemented. The measurement results show that the total thermal noise is reduced by this means.

Chapter 6 presents the measurement results of the APS+ in practical working conditions. At room temperature, the APS+ achieves an accuracy (3σ) of 0.01º with a power consumption of 21mW at a 10fps update rate. As a space application, the APS+ is also tested under high temperature up to 80ºC. The test results prove that the APS+ is still reliable at such high temperatures.

Chapter 7 summarizes this thesis and discusses future work.

1.5 References

[1.1] N. Venkateswaren et al., “Precision pointing of imaging spacecraft using gyro-based attitude reference with horizon sensor updates”, Sadhana, vol. 29, part 2, pp. 189-203, Apr. 2004.

[1.2] V. Pisacane, Fundamental of Space Systems, 2nd ed., Oxford: OUP, p. 262, 2005, ISBN: 0195162056.

[1.3] V. Pisacane, Fundamental of Space Systems, 2nd ed., Oxford: OUP, p. 258, 2005, ISBN: 0195162056.

[1.4] Datasheet from CubeSatShop website: {http://www.cubesatshop.com/index.php? page=shop.product_details&product_id=18&flypage=flypage.tpl&pop=0&option=com_virtuemart&Itemid=65&vmcchk=1&Itemid=65}, accessed Nov. 2011.

[1.5] Data sheet from Sinclair Interplanetary website: {http://www.sinclairinterplanetary. com/digitalsunsensors}, accessed July 2011.

Page 20: Low-Power Low-Noise CMOS Imager Design

Introduction to attitude sensors and digital sun sensors applied for micro-satellite

12

[1.6] C. Liebe, “Star trackers for attitude determination”, IEEE Aerospace and Electronic Systems Magazine, vol. 10, issue 6, pp. 10-16, 1995.

[1.7] C. Cosner et al., “Modeling analog sun sensor current output”, Proceedings of the 1st IEEE Regional Conference on Aerospace Control Systems, pp. 156-160, May 1993.

[1.8] P. Appel, “Attitude estimation from magnetometer and earth-albedo-corrected coarse sun sensor measurements”, Proceeding of 4th IAA International Symposium on Small Satellites for Earth Observation, vol. 56, issues 1-2, pp. 115-126, Jan. 2005.

[1.9] A. Eisenman et al., “The advancing state-of-the-art in second-generation star trackers”, Proceeding of 1998 IEEE Aerospace Conference, vol. 1, pp. 111-118, 1998.

[1.10] C. Liebe, “Accuracy performance of star trackers: a tutorial”, IEEE Transaction on Aerospace and Electronic Systems, vol. 38, issue 2, pp. 587-599, 2002.

[1.11] J. Leijtens et al., “Now is the time for the sunsensor of the future”, International Conference on Space Optics, Oct. 2010.

[1.12] F. Boldrini et al., “Attitude sensors on a chip: feasibility study and breadboarding activities”, 32nd Annual AAS Guidance and Control Conference Proceedings, Breckenridge, CO, USA, pp. 1197-1216, Feb. 2009.

[1.13] M. Snoeij et al., “Multiple-ramp column parallel ADC architectures for CMOS image sensors”, IEEE Journal of Solid-State Circuits, vol. 42, no. 12, pp. 2968-2977, 2007.

[1.14] M. Snoeij et al., “An 80μVrms temporal noise 82dB dynamic range CMOS image sensor with a 13-to-19b variable resolution column parallel folding integration/cyclic ADC”, Proceeding of IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, pp. 400-402, 2011.

Page 21: Low-Power Low-Noise CMOS Imager Design

13

Chapter 2

Introduction to CMOS Image Sensors

In this chapter, the background knowledge on CMOS image sensors is introduced. After the overview in the first section, the performance evaluation, pixel architectures and noise sources are discussed in the following sections. In the last section, the analog processing chain of a CMOS imager is outlined.

Page 22: Low-Power Low-Noise CMOS Imager Design

Introduction to CMOS image sensors

14

2.1 Overview of solid-state image sensors

Charge-coupled devices (CCDs) and CMOS sensors are the two types of technologies used for manufacturing solid-state image sensors. CCD and CMOS imagers were both invented in the late 1960s. They opened up a new era for the imaging industry, and have threatened the traditional image recording technologies, such as film and video tubes.

The CMOS image sensor prototype was proposed by IBM [2.1], Westinghouse [2.2] and Fairchild [2.3] in the late 1960s. However, during those early days, passive pixel sensors (PPSs) were the technology of choice, because the feature size of the technology was so large that it could not accommodate any active components. The performance of PPS CMOS image sensors was not acceptable due to poor driving capacity and high reset noise. Thus, CMOS image sensors were almost completely abandoned in those days.

CCDs were first reported in 1970 by Willard Boyle and George Smith from Bell Labs [2.4]1. Although CCDs were originally invented as analog memory devices, they quickly became the dominant solid-state image sensor technology over the next 20 years. Compared with CMOS imagers, CCDs produced far superior images in terms of dark current, image uniformity, quantum efficiency and fill-factor with the fabrication technology available. Although the thermal noise level of CCDs and CMOS sensors are comparable, CCDs have a fixed-pattern noise (FPN) advantage over CMOS because of the way they operate: photon-generated electrons are processed mostly in the charge domain where no mismatch among active transistors is introduced, and a common output amplifier is used. Thus, it has achieved great success in most imaging applications, including video cameras, digital still cameras and as scientific imagers.

Although the prototype of CMOS active pixel sensors (APSs) was originally proposed in 1968, APSs were not attractive for the next 20 years due to the technology limitations [2.5]. However, in the 1990s the investigation on CMOS imagers came back with a focus on APS [2.6]. An APS is defined as a sensor with

1 They were rewarded the Nobel Prize in physics in 2009 for their great contribution for CCD.

Page 23: Low-Power Low-Noise CMOS Imager Design

Introduction to CMOS image sensors

15

one or more active components located within each pixel. Compared with a PPS, the active in-pixel component significantly increases the speed of APS sensors and improves the signal-to-noise ratio (SNR) because of the buffering capacity provided by the source follower transistor and the relatively low reset noise due to the in-pixel reset transistor solution. The APS became feasible with the advent of deep submicron CMOS process, which made CMOS imagers a viable alternative to CCDs. With APS imagers, the integration of on-chip functional blocks with a sensor element became possible. The first successful high performance CMOS image sensor was reported by the Jet Propulsion Laboratory (JPL) in 1995. The performance of CMOS image sensors was further rapidly improved after the pinned photodiode (PPD) was introduced into CMOS imagers [2.7]. Nowadays CMOS image sensors are widely used in both high-volume products such as mobile imaging and internet-based web cameras, and high-end consumer products such as digital, still and video cameras.

The differences between CMOS image sensors and CCDs mainly arise from their different readout structures. In a CCD, charge is shifted through vertical and horizontal CCDs, and readout serially. In a CMOS image sensor, voltages are readout one row at a time, similar to random access memory using row and column decoders. Each architecture has its advantages and disadvantages. One main advantage of CCDs readout principle is that charge transfer is passive; therefore it does not introduce temporal noise or pixel FPN. Unlike CCDs, the active devices in a CMOS imager introduce both temporal noise and FPN. However, the serial readout of CCDs results in a limited readout speed. It is also power consuming because it requires various high-voltage, high-rate clocks. On the contrary, the random access readout of CMOS image sensors provides a high readout speed and potential region-of-interest (ROI) operation with low power. At the same time, CMOS image sensors are fabricated in a standard technology, which enables its integration with other analog and digital processing circuits.

This thesis focuses on the design of a miniaturized digital sun sensor implemented using CMOS imaging technology. It stresses low power consumption and high integration between the sensor and the processing circuit. In reference to this specific application, a CCD is not preferred due to the difficulty of integrating CCDs with CMOS transistors and the incapability of ROI operation. In addition,

Page 24: Low-Power Low-Noise CMOS Imager Design

Introduction to CMOS image sensors

16

CCDs are radiation-soft because displacement damage caused by radiation is fatal to CCDs due to its serial readout principle [2.5].

Therefore a CMOS image sensor has been designed for the Micro-Digital Sun Sensor (μDSS) project. The performance evaluation of CMOS image sensors will be briefly discussed in the following sections of this chapter.

2.2 Performance evaluation of CMOS image sensors

A CMOS image sensor is a semiconductor device which converts an optical image into electronic signals by the CMOS technology. Many of the evaluation parameters of a CMOS imager are eventually determined or limited by the pixel design. In this section, these performance characteristics are introduced in detail.

2.2.1 Quantum efficiency and responsivity

The photodetector used by CMOS image sensors, as well as CCDs, is intrinsically a reverse-biased positive-negative (PN) junction photodiode. The operation principle is based on the photoelectric effect. In this phenomenon, photons that penetrate into the silicon excite electron-hole pairs which are separated by the electrical field across the junction. Quantum Efficiency (QE) evaluates the photodiode’s electrical sensitivity to light as a function of wavelength. QE is defined as:

- ( )( )( )

e

ph

NQEN

λλλ

= , (2.1)

where Ne-(λ) is the number of electrons generated and collected by a pixel and Nph(λ) is the number of photons that arrive at the pixel; λ stands for the wavelength.

Another light sensitivity characteristic is responsivity, R(λ), which is defined as the ratio of the photocurrent to the optical input power and is given by [2.8]:

2

2

[ / ] ( )( ) ( )[ / ] ( )

ph e

ph ph

I A cm qN qR QEP W cm E N hc

λ λλ λλ

−= = = , (2.2)

where Iph is the photocurrent, P is the optical input power, q is the electron charge, Eph is the photon energy, h is Planck’s constant, and c is the speed of light.

Page 25: Low-Power Low-Noise CMOS Imager Design

Introduction to CMOS image sensors

17

Equations (2.1) and (2.2) indicate that the spectral response can be represented in two ways: QE and responsivity. Figure 2.1 is an example which demonstrates the difference between the two characteristics [2.8]. In this example, the QE is 0.5 from 400nm to 700nm; it decreases after 700nm. The decrease implies the incapability of the photodiode to collect the electrons emitted by light with a longer wavelength that penetrate deeper into the semiconductor. The responsivity linearly increases as a function of wavelength from 400nm to 700nm, because Eph is inversely proportional to the light wavelength, as indicated by (2.2).

Figure 2.1 Spectral response: (a) QE; (b) responsivity; redrawn from [2.8].

QE is always less than one in a silicon photodetector. A couple of sensitivity losses could happen during the photon-electrical transformation. They include: photon reflection and absorption at the interferences in the multi-layer silicon photodetector structure; the generation-recombination and trapping of electron-hole pairs at the SiO2-Si interface; the generation-recombination of electron-hole pairs outside the depletion layer; and the photon loss, which is not absorbed in silicon [2.9]. The QE of a photodiode mainly depend on the geometry and doping concentrations of the photodetector [2.10].

2.2.2 Full well capacity, dynamic range and signal-to-noise ratio

Under normal illumination intensities, the photon-generated current in a photodiode is very small (in the range of femto- to picoamperes), thus the current is quite difficult to measure directly. For this reason, photodiodes are mostly used in

Page 26: Low-Power Low-Noise CMOS Imager Design

Introduction to CMOS image sensors

18

an integration mode: the photon current is integrated and read out as charge (in CCDs) or voltage (in APSs) at the end of the integration time [2.11].

This operation is illustrated in Figure 2.2(a) [2.11]. The photodiode is first reset to Vres by the reset switch; after the reset, the photocurrent iph is integrated on the diode capacitance CD; at the end of integration, the diode voltage VD is read out. The accumulated charge versus time under two different illumination intensities is depicted in Figure 2.2(b). In the case of low light, the charge (as well as VD) is almost a linear function of integration time. While in the case of high light, the diode saturates when the accumulated charge is equal to the full well capacity, which is the maximum amount of charge the diode capacitance is able to hold.

Figure 2.2 (a) Pixel operating in integration; (b) charge versus time with two light intensities.

The dynamic range (DR) of a CMOS imager is defined as the ratio between the full well capacity and noise floor, which is the total noise under dark condition. The Signal-to-Noise Ratio (SNR) of a CMOS imager is the ratio between the signal and the noise at a given input level [2.8]. They are represented by:

[ ]sat

dark

NDR 20log dBn

⎛ ⎞= ⎜ ⎟

⎝ ⎠, (2.3)

[ ]sig

tot

NSNR 20log dB

n⎛ ⎞

= ⎜ ⎟⎝ ⎠

, (2.4)

Page 27: Low-Power Low-Noise CMOS Imager Design

Introduction to CMOS image sensors

19

where Nsat is the well capacity and ndark is the noise floor, which are both expressed in electrons; Nsig is the signal charge, and ntot is the total temporal noise at the signal level, which are both expressed in electrons.

2.2.3 Conversion gain

In an APS, the output of a pixel is an analog voltage. The signal path of an image sensor from the incident photon flux to the output voltage is depicted in Figure 2.3. The conversion gain (CG) expresses how much voltage change is obtained at the source follower output node by one electron [2.8]. It is defined as:

[ / ]SFD

qCG = A V eC

μ −i , (2.5)

where q is the elementary charge (1.602 × 10−19 C), CD is the capacitance of the charge detection node, and ASF is the source follower amplification in voltage, which is approximately 0.8 due to the body effect [2.12].

Figure 2.3 Signal conversion path of an image sensor; redrawn from [2.10].

The conversion between the signal charge and signal voltage is obtained by the definition:

sig sigV CG N= i , (2.6)

where Vsig and Nsig are the signal voltage and signal charge, respectively.

CG is usually measured indirectly by a noise measurement. Photon shot noise is introduced due to statistical quantum fluctuations of the light. It has a root-mean-square value proportional to the square root of the number of arrival photons at the pixel. This relation is expressed as the following equation:

shot sigN N= , (2.7)

where Nshot is the photon shot noise in electrons. The relation between shot noise in voltage and signal charge is:

Page 28: Low-Power Low-Noise CMOS Imager Design

Introduction to CMOS image sensors

20

shot shot sigv CG N CG N= =i i , (2.8)

where vshot is the shot noise voltage. If (2.6) and (2.8) are combined, the following relation between shot noise voltage and signal voltage could be obtained:

2shot sigv CG V= i . (2.9)

Equation (2.9) can be depicted as a Photon Transfer Curve (PTC). When shot noise is the dominant noise source in an image sensor, the conversion gain can be

obtained as the slope of 2shot sigv /V . This technique will be discussed in detail in

Chapter 6.

2.3 Pixel architecture

In the previous section, the pixel characteristics and signal conversion path were discussed. In this section the different pixel architectures will be described. Among all architectures, pixels are categorized into PPSs and APSs depending on whether an amplifier is implemented in-pixel. PPSs were adopted only in the early stages of CMOS image sensors, when the feature size was too large to accommodate an amplifier transistor in pixel. Right after the submicron CMOS technology made APSs possible, they took the place of PPSs and became a main stream CMOS imager. Therefore, only APSs will be introduced in this section.

Figure 2.4 3T active pixel.

Three-transistor (3-T) and pinned photodiode active pixels are the most widely used APS structures. The scheme of a 3-T pixel is depicted in Figure 2.4. It employs a p-n junction photodiode (PD) and a readout circuit consisting of three transistors:

Page 29: Low-Power Low-Noise CMOS Imager Design

Introduction to CMOS image sensors

21

a photodiode reset transistor (RST), a row-select transistor (RS), and a source-follower transistor (SF). The current source component of the follower amplifier is shared by a column of pixels [2.5].

Figure 2.5 4-T active pixel.

The pinned photodiode or four-transistor (4-T) active pixel is shown in Figure 2.5. It consists of a pinned diode which adds a transfer gate (TX) and a floating diffusion (FD) node to the basic 3T APS pixel architecture. With a pinned diode, the photon collection area is located away from the surface in order to reduce the surface defect noise (such as dark current). At the end of integration, the photon charges collected by the pinned diode are transferred to the FD node for readout.

Each APS structure has its advantages and disadvantages [2.10] [2.13]. A 4-T pixel has one more transistor, resulting in either a larger pixel or a lower fill factor than a 3T pixel. The pinned layer results in a very small full well capacity for photon-generated charge collection and lower quantum efficiency than a 3-T pixel. On the other hand, the use of a transfer gate and an FD node in the 4T pixel decouples reset and readout operation from the integration period, enabling correlated double sampling (CDS), which will be discussed in the following section. Moreover, the conversion gain of a 3-T pixel is primarily determined by the diode capacitance, while in a 4-T pixel the FD node capacitance could be selected independently from the photodiode, thus the conversion gain could be optimized for specific applications.

Page 30: Low-Power Low-Noise CMOS Imager Design

Introduction to CMOS image sensors

22

2.4 Noise in CMOS image sensors

Figure 2.6 shows the locations where various noises are generated in a CMOS image sensor [2.14]. The noise sources can be categorized as temporal noise or spatial noise.

Figure 2.6 Noise sources in a CMOS image sensor.

Temporal noise is independent across pixels and varies from frame to frame in the time domain. The sources of temporal noise include photon shot noise, reset noise, 1/f noise, dark current shot noise, etc. Temporal noise sets the fundamental limit on image sensor performance.

In addition to temporal noise, CMOS image sensors also suffer from spatial noise or FPN, which is introduced by the device and interconnect mismatches across the image sensor array. Major sources of FPN include the offset FPN, gain FPN leading to photo response nonuniformity (PRNU), and dark signal nonuniformity (DSNU) caused by FPN resulting from dark current variation. Column FPN, which is caused by column circuit mismatch, is the most easily visible FPN.

Figure 2.7 Sampling principle for (a) CDS; and (b) DDS.

The offset FPN due to device mismatch and reset noise can be cancelled by correlated double sampling (CDS) [2.10]. The sampling principle of CDS is illustrated in Figure 2.7(a) for a 3-T pixel. VPD is the voltage at a photodiode. With CDS, each pixel output is sampled twice: once right after reset (S1), the other at the

Page 31: Low-Power Low-Noise CMOS Imager Design

Introduction to CMOS image sensors

23

end of integration (S2). The final result, which is expressed as the following equations, is obtained by subtracting the two samples:

1 2 sigS S S V= − = , (2.10)

where S is the signal level, in this case indicated as Vsig. The noises in S1 and S2

(N1, N2) and the noise in the final result (NCDS) using CDS are expressed as

following:

2 2 2 21, 1,1/1 reset therm f offsetN n n n n= + + + , (2.11)

2 2 2 2 22, 2,1/2 shot reset therm f offsetN n n n n n= + + + + , (2.12)

21, 2,2 2

CDS shot therm thermN n n + n= + , (2.13)

where nshot is the shot noise, nreset is the reset noise, n1,therm and n2,therm are the thermal noise of the readout circuit of S1 and S2, n1,1/f and n2,1/f are the 1/f noise of the two samples, and noffset is the offset FPN due to device mismatch. Equation (2.13) shows that the CDS suppresses both offset FPN and reset noise. Since n1,therm and n2,therm are non-correlated, the power of the thermal readout noise is doubled. The 1/f noise component in the read noise can be suppressed if the interval between the two samplings is so short that the 1/f noise is correlated. This is the case with 4-T APSs, where CDS is performed at the FD node directly without any regard for the integration time.

With a 3-T APS pixel, an operation called delta double sampling (DDS) is commonly used. The sampling principle of DDS is illustrated in Figure 2.7(b). With DDS, the pixel output is sampled once after integration (S2) and once after the next reset (S3). Similar as CDS, the video signal is achieved also by subtracting the two samples which is expressed as:

3 2 sigS S S V= − = . (2.14)

The noise components in S3 are expressed as following:

Page 32: Low-Power Low-Noise CMOS Imager Design

Introduction to CMOS image sensors

24

2 2 2 23, 3, 3,1/3 reset therm f FPNN n n n n= + + + , (2.15)

where n3,reset, n3,therm, n3,1/f , and nFPN are the reset noise, readout thermal noise, 1/f noise and FPN in S3, respectively. The noise (NDDS) in the final result with DDS is:

2 2 2 2 22, 3, 2, 3,DDS shot reset reset therm thermN n n n n n= + + + + . (2.16)

In (2.16), since the reset noise in S2 and S3 are non-correlated, only offset FPN and 1/f noise are suppressed; both the reset noise power and the thermal component of the read noise power are doubled.

From the discussion above, the disadvantage of a 3-T pixel compared to a 4-T pixel is the remaining reset noise. In this thesis, a quadruple sampling method will be applied on a 3-T APS in order to suppress the reset noise as well as offset FPN and 1/f noise. This will be discussed in Chapter 5.

2.5 Analog processing chain in CMOS image sensors

Although CMOS image sensors may vary in resolution, frame rate and other characteristics, most of them employ a similar analog processing chain, the block diagram of which is shown in Figure 2.8.

The analog chain of a CMOS imager can be divided into five blocks based on their functionalities: a photon sensitive pixel array, a column sample-hold (S-H) array, a column decoder, a row decoder and a chip-level processing circuit.

The pixel array is the photon detector. A row of the pixel outputs are readout concurrently in combination with the in-pixel circuit and the column sample-hold (S-H) array. At this end, a row decoder outputs control signals to ensure that only a single row of the pixel array is connected to the column circuit. The sampling results of the connected row are stored on capacitors in the S-H array. At this end, a column decoder outputs control signals to connect a single column S-H circuit to the chip-level circuit in succession. Once the specific column is connected, the sampling on the S-H circuit is processed by the chip-level circuit. In this case, the name of the “chip-level” circuit implies that a single circuit is used to readout all the signals on this chip.

Page 33: Low-Power Low-Noise CMOS Imager Design

Introduction to CMOS image sensors

25

Figure 2.8 Block diagram of an analog processing chain in a CMOS image sensor.

In this chapter, most of the characteristics and architectures of CMOS image sensors were described. The proposed µDSS, which is intrinsically a CMOS imager, will be designed and verified according to these aspects in the following chapters of this thesis.

2.6 References

[2.1] J. Horton et al., “The scanistor: a solid-state image scanner”, Proceeding of IEEE, vol. 52, pp. 1513-1528, 1964.

[2.2] M. Schuster et al., “A monolithic mosaic of photon sensors for solid state imaging application”, IEEE Transactions on Electron Devices, vol. ED-13, pp. 907-912, 1966.

[2.3] G. P. Weckler, “Operation of p-n junction photodetectors in a photon flux integration mode”, IEEE Journal of Solid-State Circuits, vol. 2, pp. 65-73, 1967.

[2.4] W. S. Boyle et al., “Charge-coupled semiconductor devices”, Bell System Technical Journal, vol. 49, pp. 587-593, 1970.

[2.5] P. Noble, “Self-scanned image detector arrays”, IEEE Transactions on Electron Devices, vol. ED-15, pp. 202-209, Apr., 1968.

Page 34: Low-Power Low-Noise CMOS Imager Design

Introduction to CMOS image sensors

26

[2.6] E. Fossum, “Active pixel sensors: are CCD’s dinosaurs?”, Proceeding of SPIE, Charge-Coupled Devices and Solid-State Optical Sensors III, vol. 1900, pp. 2-14, 1993.

[2.7] N. Teranishi et al., “No image lag photodiode structure in the interline CCD image sensor”, IEDM Technology Digest, pp. 324-327, Dec. 1982.

[2.8] J. Nakamura et al., Image Sensors and Signal Processing for Digital Still Cameras, pp. 53-93, 2006, ISBN 0-8493-3545-0.

[2.9] A. Theuwissen, “Image capturing, image sensors, technologies and applications”, CEI-Europe Course, Copenhagen, Denmark, pp. 223-232, 2007.

[2.10] A. Gamal et al., “CMOS image sensors”, IEEE Circuits and Devices Magazine, vol. 21, issue 3, pp. 6-20, May-June 2005.

[2.11] A. Theuwissen, “Image capturing, image sensors, technologies and applications”, CEI-Europe Course, Copenhagen, Denmark, pp. 74-87, 2007.

[2.12] B. Razavi, Design of Analog CMOS Integrated Circuits, pp. 67-76, 2001, ISBN 0-07-118839-8.

[2.13] O. Yadid-Pecht et al., CMOS Imagers: From Phototransduction to Image Processing, pp. 105-113, May 2004, ISBN 1402079613.

[2.14] A. Theuwissen, “Image capturing, image sensors, technologies and applications”, CEI-Europe Course, Copenhagen, Denmark, pp. 287-347, 2007.

Page 35: Low-Power Low-Noise CMOS Imager Design

27

Chapter 3

Overview of the Micro-Digital Sun Sensor

The Micro-Digital Sun Sensor (μDSS) is a completely autonomous and highly integrated sun sensor. It achieves a high resolution, low power consumption and has a light mass. These characteristics make it ideally suitable for micro-satellite applications. This chapter gives an overview of the μDSS on the system level.

In this chapter, the basic working principle of the μDSS is explained in Section 3.1. The block diagram and specific optical elements of this system are also presented. In Section 3.2, the relation between the sunspot centroid and sunlight incident angle is discussed. In Section 3.3, an overview of the centroiding algorithm is presented. Afterwards, design challenges for the sensing chip of the μDSS, which is called the APS+, are discussed. The low power consumption and low-noise design approaches with the APS+ are introduced in Section 3.4 and Section 3.5, respectively. Lastly, in Section 3.6, the radiation hardness consideration in the APS+ design is analyzed.

Page 36: Low-Power Low-Noise CMOS Imager Design

Overview of the micro-digital sun sensor

28

3.1 Working principle of the Micro-Digital Sun Sensor

3.1.1 Working principle

The Micro-Digital Sun Sensor (μDSS) is an autonomous digital sun sensor applied to micro-satellites. This project was developed by Delft University of Technology (TU Delft) in cooperation with TNO2 (Delft, the Netherlands). TU Delft designed the APS+ sensing chip, while TNO designed the sensor system architecture. This thesis will thus focus on the design of the APS+. At this moment, the μDSS system has been completely calibrated and tested. The scientific micro-satellite equipped with this sun sensor will be launched in 2012.

Figure 3.1 Working principle of the μDSS.

The μDSS determines the satellite orientation by sensing the angle between the satellite and the sun. It is intrinsically a pinhole camera: a lensless camera with an aperture simplified as a pinhole. Different pixels on the array are illuminated

2 TNO (‘Nederlandse Organisatie voor Toegepast Natuurwetenschappelijk Onderzoek’ or ‘Netherlands Organization for Applied Scientific Research’) is a non-profit organization in the Netherlands that focuses on applied science.

Page 37: Low-Power Low-Noise CMOS Imager Design

Overview of the micro-digital sun sensor

29

depending on the sunlight incident angle. The orientation information can be derived from the projective image on the detector’s plane. The working principle is depicted in Figure 3.1. In this illustration, the sun is the point light source. The CMOS image sensor is placed on the substrate, with a membrane above its focal plane. The pinhole is located at the center of this membrane. Sunlight passes through the pinhole and projects an image onto the pixel array of the CMOS image sensor. By reading out the position of the sunlight-projected image, the sunlight incident angle (θ) can be calculated. Furthermore, the satellite’s attitude is determined based on the sunlight incident angle.

3.1.2 Block diagram

Figure 3.2 shows the cross section and block diagram of the μDSS system. As indicated in the block diagram, the μDSS is composed of an image sensor chip called the APS+, a solar cell, and an RF module. The solar cell supplies power to the whole system, and the RF block facilitates communication between the μDSS system and the other elements on the satellite.

The critical component in the μDSS is the APS+ sensing chip. It is composed of a CMOS Active Pixel Image Sensor (APS), an A-to-D converter (ADC) and a digital processing circuit. The functions of these sub-blocks are listed below:

APS: The APS is the photosensitive element in the system. It converts the incoming light signals into voltage signals. The APS is composed of a pixel array, sample-hold array and readout circuit. The output signal is read out in the analog domain.

Chip-level ADC: A 12-bit pipeline ADC is implemented. It reads out the analog signal from the APS and outputs the digital signals to the centroid algorithm circuit.

Digital processing circuit: The Digital processing circuit includes the centroid algorithm circuit, I/O interface circuit and Timing and Control circuit. The centroid algorithm determines the centroid coordinate of the sunlight projected image on the focal plane based on the APS outputs. Through the I/O interface, the μDSS receives commands from the outside and outputs the centroid coordinate. The Timing and Control circuit generates the timing and control signals for the APS.

Page 38: Low-Power Low-Noise CMOS Imager Design

Overview of the micro-digital sun sensor

30

Figure 3.2 (a) Cross section of the μDSS system; (b) block diagram.

The key component of the µDSS system is the APS+. In order to satisfy all the target specifications, the APS+ design must be optimized. The APS+ design will be discussed in detail in Chapter 4 and Chapter 5.

3.1.3 Miniaturization of the μDSS

As discussed in Chapter 1, the µDSS has specific requirements in many aspects due to the microsatellite application. It should be minimal in size and power consumption, while maintaining the accuracy performance. These specifications are summarized again in Table 3.1.

Page 39: Low-Power Low-Noise CMOS Imager Design

Overview of the micro-digital sun sensor

31

Table 3.1 Design specifications of the µDSS.

Specification Number Unit

Size 51×51×14 3mm

Weight <30 grams

Power <100 mW

Field of View 47×47±2 degree

Accuracy 0.1 (3σ) degree

Radiation tolerance 20-30k rad

The µDSS achieves miniaturization in size and mass mainly from the system-level design. Figure 3.3 presents the different generations of the digital sun sensors [3.1][3.2]. The left two are the first and second generations of digital sun sensors developed by TNO (Delft, the Netherlands). The one on the right is the μDSS. As is clearly shown, the μDSS achieves a significant reduction in size and mass. The miniaturization was realized with several approaches.

Figure 3.3 Three generations of digital sun sensors; (a), (b): first and second generation digital sun sensors; (c): the μDSS.

First of all, the μDSS is fully autonomous since the power supply is provided by a solar cell which is mounted on top of the housing, and a wireless data interface is also integrated (as shown in Figure 3.2).

Page 40: Low-Power Low-Noise CMOS Imager Design

Overview of the micro-digital sun sensor

32

Secondly, the SoC APS+ chip greatly contributes to the miniaturization. Together with the pinhole, the APS+ is actually a camera-on-a-chip device. It integrates the active pixel array, control signal generator, ADC, I/O interface and digital processing circuit on-chip. This highly integrated approach effectively reduces the size of the whole system. In addition, the APS+ also leads to the size reduction of the solar cell. In the case of autonomous powering, the size of the solar cell has to be sufficient to supply the peak current required by all the components. One of the main distinctive APS+ features is its optimization in power consumption. Since the current required by the sun sensor chip is lowered, the size of the solar cell can be reduced accordingly.

Compared with previous generations, the μDSS offers a smaller size, lighter weight and lower power consumption. This miniaturized sun sensor is intrinsically cost-efficient, thus it is ideal for large quantity manufacturing. This highly integrated sun sensor can also be produced as a space-grade off-the-shelf product.

3.1.4 Optical design in the µDSS

Figure 3.4 Optical structure of the µDSS.

The Figure 3.4 illustrates the optical structure of the µDSS. One important optical element is a spectrum filter for light attenuation. The area power density (W/m2) of the sun radiation reaching the µDSS depends on many environmental conditions, the attitude angle of the satellite, etc. It has a typical, average value of 1500 W/m2. If sunlight of this intensity goes through the pinhole without attenuation, the pixels will be constantly saturated. Therefore, it is definitely necessary to have an attenuation filter above the membrane which limits the amount of sunlight to a

Page 41: Low-Power Low-Noise CMOS Imager Design

Overview of the micro-digital sun sensor

33

reasonable level, as shown in Figure 3.4. The filter will be defined in the way that the pixels illuminated by the sunlight are close to saturation level. Moreover, the sunlight power density is spread over the entire frequency spectrum. In the “red” light part, the “red” photons penetrate deeper into the silicon in the pixel and might introduce extra cross-talk among pixels. This cross-talk will reduce the accuracy of the measurements. For this reason, the filter is also required to limit the incoming light to the “green” part, or even better the “blue” part of the visible spectrum. This filter has to be designed according to the quantum efficiency of the pixel. The quantum efficiency of the pixel in the µDSS is discussed in Chapter 4.

As illustrated in Figure 3.4, the spectrum filter is located at the bottom side of the sapphire window. The filter layer is a couple of microns thick. An indium tin oxide (ITO) layer is deposited on top of the sapphire window. The ITO layer is a transparent conducting oxide layer which is connected to the grounded housing. With the ITO layer, the sunlight can go through the pinhole and will arrive at the APS+ surface, while the charge generated by cosmic radiation will be discharged through the housing.

The membrane is coated with different materials on both sides. The top side of the membrane is an aluminum layer; while the bottom side is black. In this way, the influence from the reflected light will be minimized.

The diameter of the pinhole is approximately 50μm to 65μm. The focal length (F) is 1085μm. These two parameters are determined by the centroid algorithm, which was designed by TNO (Delft, the Netherlands).

3.2 Overview of the incident angle determination

3.2.1 Relation between the centroid location and sunlight incident angle

The system sketch in Figure 3.5 illustrates the relation between the centroid of the projected sunspot and the sunlight incident angle. Here l is the distance between the sunspot centroid and the center of the pixel array. θ is the sunlight incident angle.

Page 42: Low-Power Low-Noise CMOS Imager Design

Overview of the micro-digital sun sensor

34

We assume ' p cx x x= − ; ' p cy y y= − ; here x’ and y’ are the coordinates in the O’-

X’-Y’ plane. The focal length F is 1085μm. The relation between l, θ and F is:

2 2' '

tan arctan( ) arctan( )x yll F

F Fθ θ

+= ⇒ = =i . (3.1)

Since F is a constant value, θ can be expressed as a function of l: 2 2( ) ( ' ' )f l f x yθ = = + . Thus, after the l is determined by centroid detection, the

respective angle between the satellite and the sun can be calculated by processing circuits.

3.2.2 Determination of the pixel array size

In the µDSS, the size of the pixel array is determined by the Field of View (FoV) requirement. The pixel array should be large enough to track the sunspot centroid in the complete FoV. At the same time, the pixel array should not be too large so that the chip area fits the limited space on the micro-satellites.

Parameter Definition

O-X-Y CMOS image sensor axis

O’-X’-Y’ CMOS image sensor center axis

x c, y c Image sensor array centroid coordinate

x p ,yp Sunlight image centroid

coordinate α Y-axis incident angle β X-axis incident angle θ Sunlight incident angle

l Distance between

sunspot centroid and pixel array center

F Distance between mask hole and CMOS sensor

(focal length) Figure 3.5 System sketch of the μDSS.

Page 43: Low-Power Low-Noise CMOS Imager Design

Overview of the micro-digital sun sensor

35

Equation (3.1) reveals the relation between the incident angle (θ) and the sunspot displacement (l). Since the function of the tangent is not linear, the displacement shift is larger when the sunlight incident angle becomes larger. This relation is shown in Figure 3.6. It indicates that, in order to achieve the original FoV of ±56º, the range of the displacement l will be ±1.61mm. Thus, the minimum pixel array size is 512×512 with a pixel pitch of 6.5µm. However, in practice, the chip area of 5mm×5mm is not large enough for a 512×512 pixel array and its readout circuit. For this reason, in the prototype chip introduced in this thesis, the real pixel array size is 368×368. With this pixel array, the available FoV becomes ±47º.

Figure 3.6 The relation between sunspot displacement (l) and incident angle (θ).

3.2.3 Determination on the size of region of interest

The μDSS determines the centroid location in two steps: first in the acquisition mode, it scans the complete pixel array and locates the region of interest (ROI) where the sunspot is roughly located; after that in the tracking mode, it zooms into the ROI and reads out the fine location of the centroid. The ROI is illustrated in Figure 3.7. This readout method will be introduced in Section 3.3. In this section, the size of the ROI is defined based on the relation between the sunlight incident angle and the sunspot displacement.

Page 44: Low-Power Low-Noise CMOS Imager Design

Overview of the micro-digital sun sensor

36

Figure 3.7 Illustration of the ROI.

The ROI should be large enough so that sufficient sunlight-intensity information can be achieved for centroid calculation. In addition, since the ROI is decided in the acquisition mode but readout in the tracking mode, the location of the sunspot could have changed during the mode switching time. Therefore, the displacement shift due to the change in the satellite’s position should also be considered when the ROI is decided. However, if the ROI is too large, the extra pixel noise as well as readout noise will introduce an error into the calculation. Thus, a compromise has to be made when the ROI size is determined.

The size of the sunspot is defined by the pinhole, which is approximately 10×10 pixels. The displacement shift (Δl) is decided by the incident angle (θ) and the angular variance during the time interval (Δθ). Their relation can be derived from (3.1):

2 2cos cosF Fl tθ θθ θ

Δ = Δ = ∂ Δi i i , (3.2)

where θ∂ is the instant angular velocity of the satellite, and Δt is the time interval. The relation in (3.2) is illustrated in Figure 3.8. In this figure, the displacement shifts under three angular variances (1-3º) are presented. The figure shows that this relation is also not linear. With the same angular variation, the displacement shift differs depending on the incident angle.

Page 45: Low-Power Low-Noise CMOS Imager Design

Overview of the micro-digital sun sensor

37

Figure 3.8 Relation between the displacement shift (Δl), the incident angle (θ) and the angular variance (Δθ).

In the μDSS application, the satellite circles the earth in a low earth orbit in about 90 minutes. Thus, the normal angular velocity is 360/(90*60) = 0.07degrees/s. However, in reality, the angular velocity is influenced by disturbances caused by many factors, for example variations in the earth’s magnetic field or the attitude changing operation of the satellite. In these situations, the large instant angular velocity ( θ∂ ) could lead to significant angle variance (Δθ) in the short time interval between acquisition and tracking modes. In a harsh environment, the angular variance could be up to 3 degrees. In this case, considering the worst case in Figure 3.8 (the largest incident angle), the displace shift will be no more than 5 pixels (0.03mm).

In conclusion, considering the sunspot size and the displacement shift in a harsh environment, an ROI with 21×21 pixels satisfies all the requirements. In practice, a window of 25×25 pixels will be readout, with two redundant pixels at each side of the ROI.

Page 46: Low-Power Low-Noise CMOS Imager Design

Overview of the micro-digital sun sensor

38

3.3 Overview of the centroiding algorithm

3.3.1 Introduction to the centroiding algorithm

By directly reading out the pixels in the region of interest (ROI), the centroid can only be located in pixel resolution. The μDSS achieves a sub-pixel resolution with a “double balance method for centroiding” developed by TNO (Delft, the Netherlands) [3.3].

Figure 3.9 Illustration of the centroid algorithm.

Figure 3.9 illustrates the centroid algorithm. The active ROI has 21×21 pixels while the complete window has 25×25 pixels. The ROI is divided into several areas; they are labeled as A to E in the figure, and are represented by different colors.

It is assumed that: SXA = sum of pixel output in area-A (1×21 pixels),

SXB = sum of pixel output in area-B (9×21 pixels),

SXC = sum of pixel output in area-C (1×21 pixels),

SXD = sum of pixel output in area-D (9×21 pixels),

SXE = sum of pixel output in area-E (1×21 pixels).

Page 47: Low-Power Low-Noise CMOS Imager Design

Overview of the micro-digital sun sensor

39

The centroiding is determined by two sub-windows in the ROI. First, a window of 20×20 pixels is created around the pixel in the center of the ROI. This window consists of areas A, B, C and D. It is divided into two equal parts: A+B and C+D. Next, the window is shifted by one column. This second window consists of areas B, C, D and E. It is also divided into two equal parts: B+C and D+E. The XPOS, which is the centroid position on the x-axis, can be determined by the imbalance between the two sub-windows:

XC XD XA XBPOS

XC XD XA XB XB XC XD XE

(S S ) (S S )X =[(S S ) (S S )] [(S S ) (S S )]

+ − ++ − + + + − +

. (3.3)

Areas A and E are expected to be non-illuminated areas. As long as the background is uniformly distributed, we can assume that SXA= SXE. Under this assumption, (3.3) can be simplified as:

XD XBPOS

XC XA

S S1 1X =2 2 S S

−+

−i . (3.4)

XPOS achieves sub-pixel resolution and is expressed in pixel units. When the centroid is located exactly in the center of the ROI, XPOS = 1/2. For simplicity, X'POS is defined as the sunspot centroid location referring to the center of the ROI. The expression for X'POS is:

XD XBPOS

XC XA

S S1X' =2 S S

−−

i . (3.5)

X'POS is also expressed in pixel units. If the centroid is to the right to the ROI center, X'POS>0; if the centroid is to the left to the ROI center, X'POS<0.

The centroid position referring to the ROI center on y-axis, Y'POS, can also be determined in the same way as X'POS.

3.3.2 Noise effect from the Analog-to-Digital converter to the algorithm accuracy

There are many noise sources in a CMOS image sensor. Some noise comes from the pixel, such as dark and photon shot noise, reset noise and 1/f noise. Some noise

Page 48: Low-Power Low-Noise CMOS Imager Design

Overview of the micro-digital sun sensor

40

is introduced by the readout circuit and the on-chip Analog-to-Digital converter (ADC). The noise from the ADC has a negative effect on the algorithm accuracy.

In the APS+ design, a 12-bit pipeline ADC with an S/N ratio of 65dB was implemented. However, the centroid algorithm applied to the μDSS requires 10-bit outputs. Only the upmost 10-bit ADC outputs are used by the algorithm.

The 12-bit ADC has an input-referred noise of 377μV [3.4]. Its single-ended full input range is 700mV. Therefore, the ADC equivalent noise is: 377µV/700mV×4096 = 2.2DN. Since only 10 bits are used, the equivalent noise of the 10-bit ADC will be: NADC = 2.2/4 = 0.6DN.

With the 10-bit ADC, since the light attenuation filter in the µDSS (as shown in Figure 3.4) will be calibrated such that the sunspot centroid pixel will be nearly saturated or even 10% above saturation, the ADC output level for the centroid area will be NSAT = 1023DN.

The ADC output of the pixels in the non-illuminated area of the ROI can be achieved by measurement. This dark background output is: NDARK = 37DN.

In the µDSS, each pixel output needs two analog-to-digital conversions (this will be discussed in Section 3.5 and Chapter 5.). This means that each pixel output will have a readout noise of NPIX = ADC2 N 2 0.6 0.9DN× = × = .

The numerator of (3.5) consists of the subtraction of SXD-SXB. SXD and SXB are both the sum of 189 (9×21) pixels. Consequently, the ADC readout noise in the

numerator should be: NNUM = PIXN 0.9 17.5DN2 189 2 189× = × =× × .

The denominator of (3.5) is the subtraction of SXC-SXA. Similar to the numerator, the readout noise introduced by the ADC in the denominator is:

DEN PIXN 2 21 N 2 21 0.9 5.8DN= × × = × × = .

As far as the ADC readout noise, (3.5) is modified as below:

XD XB NUMPOS

XC XA DEN

S -S N1X' = 2 S -S N

±×

±. (3.6)

Assume that the sunspot centroid is located exactly in the center of the pixel array. In this case, the result of SXD-SXB will be 0. For a sunspot with a size of 9×9

Page 49: Low-Power Low-Noise CMOS Imager Design

Overview of the micro-digital sun sensor

41

pixels, the result is SXC-SXA = 9×(NSAT- NDARK) = 9×(1023-37) = 8874DN. The value of NDEN is 5.8DN; and it can be ignored compared with SXC-SXA.

Therefore in this case, the X'POS deviation is derived from (3.6):

POS1 0 17.5X = 0.00102 8874

±× = ± pixels . (3.7)

The aim for the centroid algorithm is to achieve a sub-pixel resolution of 1/64 pixels = 0.0156 pixels. Under this assumption, the calculation in (3.7) shows that the ADC readout noise will not be a limit to the aim resolution.

Equation (3.6) also gives a clue as to how the X'POS deviation can be improved. On the one hand, with a larger sunspot size or a lower dark value (NDARK), the X'POS deviation will decrease, because the value of the denominator is increased. On the other hand, with a smaller ROI, which means a smaller numerator value, the X'POS deviation can also be decreased.

The discussions above only take into account the effect from the ADC readout noise. In reality, the pixel shot noise is one of the most important noise sources. However, in the μDSS system, the spectrum filter is adjusted to make sure that the pixels illuminated by the sunlight spot are near or above the saturation level. In this condition, the shot noise of the pixels above saturation will be greatly reduced.

Besides the shot noise, there are other pixel noise sources, including reset noise, 1/f noise, etc. The method to minimize these noise sources will be discussed briefly in the Section 3.5.

3.3.3 An approach to reduce noise effect: the multiple-aperture digital sun sensor

The μDSS is a digital sun sensor which utilizes a single aperture. Some other digital sun sensors employ a multi-aperture approach [3.5]. In principle, the pixel temporal noise is inversely proportion to the square root of the number of apertures. Therefore, accuracy can be increased by having a large number of apertures. The number of aperture varies from tens to several hundreds [3.6][3.7][3.8][3.9]. In principle, it is very difficult to machine apertures smaller than a few hundred micron meters with metal. As a result, the Micro Electro Mechanical System

Page 50: Low-Power Low-Noise CMOS Imager Design

Overview of the micro-digital sun sensor

42

(MEMS)-based sun sensors were developed, as illustrated in Figure 3.10. The MEMS fabrication techniques can enable extremely high-precision apertures with lithography techniques.

Figure 3.10 Principle of the MEMS-based digital sun sensor.

The mask above the focal plane is a small piece of silicon wafer with an evaporated layer of gold on the top side. The small pinholes are located in the gold layer. This silicon wafer (500µm thick) is mounted above the focal plane. The MEMS digital sun sensors are also pinhole cameras just as the single-pinhole sun sensors, but with multiple apertures. The sunlight intensity is high enough to penetrate the silicon wafer through the pinholes. In this way, multiple sunlight-projected images will be achieved on the image sensor array.

One of the drawbacks of this type of sun sensor is that the assembly and alignment errors will significantly impact the whole system accuracy. In addition, multiple sun images will be readout for centroid calculation. Although the pixel temporal noise will be averaged in the final result, the multiple sampling and readout will introduce extra readout noise as well. Thus, the readout circuit should be very carefully designed. The multiple sampling also requires the algorithm circuit to have more calculation capability, which will increase the circuit complexity. Another issue which has to be acknowledged is the earth albedo. Since multiple apertures exist in the system, the albedo sunlight may come into the field of view of some apertures. The albedo may have some impact on the system accuracy or even fatal errors. An albedo correction circuit may solve this problem, but again this increases the circuit complexity. Therefore, the accuracy improvement has to be weighed with the readout noise, assembly error and circuit complexity.

Page 51: Low-Power Low-Noise CMOS Imager Design

Overview of the micro-digital sun sensor

43

3.4 Low power consumption approach by the APS+

As discussed in Chapter 1, low power consumption is one of the design challenges for the µDSS. The low power is realized with a specific APS+ design, which is the sensing chip in the µDSS. This section briefly introduces the low-power approach. The design detail is discussed in Chapter 4.

3.4.1 Conventional detection method

As indicated in Figure 3.1, in the μDSS system, the size of the sunspot is approximately 10×10 pixels, while the size of the image sensor pixel array is 368×368 pixels. The conventional readout method of formal digital sun sensors determines the sunspot centroid based on the readout result of the complete pixel array [3.10]. In order to update the centroid result with a certain frame rate, the bandwidth of the readout circuit and ADC must be much higher than the frame rate. This will greatly increase power consumption. In addition, since the size of the sunspot is extremely small compared to the whole pixel array, the conventional method wastes most of the time and power on reading out the pixels that do not contain any useful information. Due to the above reasons, the power consumption of a conventional digital sun sensor could be the order of several watts [3.10].

In recently years, some digital sun sensors have adopted a power saving readout method: a two-step acquisition-tracking (coarse-fine) readout method [3.11]. Once powered on, the sensor first works in the sun acquisition mode and estimates the coarse sun coordinates. A pixel window is addressed around the estimated coordinates at the end of this mode. Afterwards the sensor works in sun-tracking mode. The final centroid coordinates of the sun image are determined based on the readout result of the window determined in the previous cycle. During the acquisition mode, the coarse coordinates are determined by searching through the complete pixel array. The amplitude of each pixel is compared with a pre-defined threshold level. Power consumption can be reduced to several hundreds of milliwatts with this method by “windowing” [3.12]. However, the acquisition mode still consumes a large amount of power. The reason is that during the acquisition mode the complete frame has to be scanned. The power consumed in the acquisition mode could be more than 1.5 times greater than in the tracking mode [3.12].

Page 52: Low-Power Low-Noise CMOS Imager Design

Overview of the micro-digital sun sensor

44

Therefore, the total power consumption can be further reduced by decreasing the power consumption in the acquisition mode.

3.4.2 Acquisition-Tracking readout method

In order to achieve a lower power consumption, the APS+ implements an optimized acquisition-tracking readout method. In the acquisition mode, the sun sensor still estimates the coarse coordinates of the sun image. Unlike the other digital sun sensors, the APS+ utilizes a specific pixel design which is able to implement a fast, low-power WTA principle in the acquisition mode. The WTA principle means that at the end of the integration time, every column or row bus holds the amplitude of the most heavily illuminated pixel (the “winner”) on each particular column or row. The profiling on column and row directions is illustrated in Figure 3.11. At the end of the acquisition mode, the APS+ determines a ROI based on the profiling which is achieved by the WTA operation. With the WTA principle, estimating the coarse sunspot center can be completed within an equivalent readout time for two lines. Under a certain frame rate, the bandwidth of the readout circuit and ADC could be greatly reduced, thus a great power reduction can be realized.

Figure 3.11 “Winner-Take-All (WTA)” principle.

After sun acquisition, the sun sensor is switched to tracking mode. During this mode, the APS+ reads out the specified ROI as a conventional image sensor. The size of the ROI is only 25×25 pixels. The final centroid is determined based on the readout results at the end of the tracking mode.

Page 53: Low-Power Low-Noise CMOS Imager Design

Overview of the micro-digital sun sensor

45

In conclusion, the APS+ implements the complete detection in two steps. The readout time for the centroid decision requires the readout time for two lines (sun acquisition) plus the readout time for 25×25 pixels (sun tracking). Compared with the size of the complete pixel array, the APS+ greatly reduces the readout burden. In this way, the power consumption is further reduced compared to the existing methods mentioned above.

The pixel design which realizes the WTA principle will be discussed in detail in Chapter 4.

3.4.3 Albedo immunity with the acquisition-tracking method

Since the μDSS is composed of a pinhole and an APS, the μDSS is intrinsically insensitive to albedo by the nature of its operation principle. Normally the intensity of albedo-reflected light is much lower than from direct sunlight, although sometimes reflection from the surface of water can still have a very high intensity, e.g. up to about 1/3 of the intensity of sunlight. In order to deal with the reflected light, the light attenuation filter will be adjusted in such a way that the outputs of the APS+ pixels at the centroid of the sun image are close to full scale or to saturation.

In the sun acquisition mode, the APS+ determines the ROI with a threshold set at 70% of the full scale. The outputs from the pixels illuminated by reflected light will be much lower than this level. Therefore, they will not introduce any error to the ROI determination. The WTA principle will not be affected by albedo.

The sun tracking is also not affected by albedo. In the µDSS application, a satellite travels with a speed of about 6 km/s. Thus, in practice, light reflected from the surface of water will only give a very short peak. In the tracking mode, if this peak occurs outside of the ROI, it will be completely neglected in the final calculation. If it occurs inside the ROI, the worst case is that the μDSS ends up with a maximum of one false reading. Since a micro-satellite normally has a control bandwidth of 1Hz, and the μDSS has a frame rate of 10frames/s, the single false reading will be detected and corrected.

Page 54: Low-Power Low-Noise CMOS Imager Design

Overview of the micro-digital sun sensor

46

3.5 Low noise approach by the APS+

Low noise is another design challenge for the APS+ design. This section briefly introduces a specific sampling method which reduces the reset noise in the 3-T active pixel. The implementation of this method will be discussed in Chapter 5.

3.5.1 Conventional readout method

The 3-T active pixel is adopted in the APS+ because of the requirement by the WTA principle. This type of pixel has a relatively simple architecture, as illustrated in Figure 3.12 (a). It consists of a photodiode (PD), a reset transistor (RST), a source follower (SF), and a row select transistor (RS). The major disadvantage of this pixel structure is that it suffers from reset noise [3.13][3.14][3.15]. Reset noise can be eliminated by means of correlated double sampling (CDS). However, with a 3-T active pixel, it is generally impossible to implement on-chip CDS since a 3-T APS is operated in “read-first-reset-later” mode. CDS can only be implemented when the APS adopts a full-frame buffer, which definitely increases the electronic complexity.

Figure 3.12 (a) 3-T active pixel structure; (b) DDS timing diagram.

Page 55: Low-Power Low-Noise CMOS Imager Design

Overview of the micro-digital sun sensor

47

Instead of CDS, a conventional 3-T APS pixel employs the delta double sampling (DDS) method. With DDS, a pixel is sampled both before and after the reset period. The timing diagram of DDS is presented in Figure 3.12(b). The result of the DDS is the difference between the two samples: S2-S1. This method allows pixel fixed-pattern noise suppression. However, at the same time, the reset noise is increased since the reset noise contents in the two samples are non-correlated. In [3.13], the reset noise in DDS is very well modeled and measured. Both the measurement results and theory calculation prove that in practice the reset noise mean square value is close to kT/2C with a soft reset, and kT/C with a hard reset, where k is the Boltzmann constant, T is the temperature in Kelvin, and C is the photodiode capacity.

3.5.2 The proposed quadruple sampling method

As described in Section 3.4.2, the final centroid result is achieved at the end of the tracking mode. Therefore, a low-noise design is a major consideration in this working mode. In order to decrease the reset noise in the 3-T APS pixel, the APS+ adopts a readout method called “quadruple sampling”. The timing diagram of quadruple sampling is illustrated in Figure 3.13.

Figure 3.13 Timing diagram of quadruple sampling.

With the quadruple sampling method, four samples are taken in a readout cycle. Samples S1 and S4 are taken when RST is active; S2 and S3 are taken at the beginning and the end of the integration time, respectively. The reset noise components in S2 and S3 can be cancelled in the end by subtraction because they are correlated in this case. During a quadruple sampling cycle, first S1 and S2 are taken once the pixel is reset; then the subtraction of S1-S2 is processed in the analog domain, and the result is stored digitally on-chip; after the integration, S3 and S4

Page 56: Low-Power Low-Noise CMOS Imager Design

Overview of the micro-digital sun sensor

48

are taken; and finally S4-S3 is again processed in the analog domain and the result is stored in the digital domain as well. Through the subtractions of S1-S2 and S4-S3, the 1/f noise components are reduced. Next, the digital outputs of the previous results are subtracted in order to cancel the reset noise. In the end, the final output is (S4-S3)-(S1-S2) = S2-S3. In this result, the 1/f noise and reset noise, which are major noise contributors, are reduced and cancelled, respectively. This readout method will be discussed in detail in Chapter 5.

3.6 Radiation consideration in the APS+ design

Although the power consumption is the major specification for APS+ design, radiation tolerance must also be carefully considered, since the sun sensor will be implemented in space applications. In the sun sensor application, the imager is exposed to significantly high levels of cosmic radiation. The APS+ chip, which is shielded by an aluminum layer a couple of millimeters thick, is specified to sustain radiation levels in the order of 20krad to 30krad. The radiance tolerance at this level will allow the APS+ to operate normally in a low earth orbit for several years. The radiation tolerance could be improved by both a hardware radiation resistant design and an algorithm correction approach.

The APS+ is manufactured with a TSMC 0.18μm standard CMOS process. Some radiation measurements have been done with image sensors produced by this process [3.16]. The results prove that this process intrinsically has a radiation tolerance higher than the required 20krad to 30krad.

In addition to the process tolerance, the pixel in the APS+ is also sophistically designed to increase the radiance tolerance. This design can greatly reduce the possibility of a single event latch-up. The pixel design will be discussed in detail in Chapter 4.

The Single Event Upset (SEU) is also taken into account in the APS+ design. An SEU is a change in state caused by ions or electro-magnetic radiation striking a sensitive node in a micro-electronic device. This is one of the most important issues for space applications because of the harsh working conditions in space. An SEU can be caused by a couple of factors. For instance, if a serious upset occurs outside of the imager or during the sun acquisition and there is a mistake in the ROI

Page 57: Low-Power Low-Noise CMOS Imager Design

Overview of the micro-digital sun sensor

49

window determination, the APS+ will no longer produce the sun centroid. In this case, the APS+ will automatically be switched to acquisition mode.

Due to large temperature variations and long-term irradiation hardness, single bad pixels may emerge. If the SEU is caused by a single pixel effect, the radiation-hardened algorithm circuit is able to detect the defect pixel and carries out several corrections accordingly on the centroid result. Only the pixels in the sunlight-illuminated region can affect the centroid result. If the defect pixel is inside the ROI, this single pixel can be detected by checking the intensity of the pixel with respect to the neighboring pixels. First the intensity of all neighboring pixels is compared with the threshold intensity in order to check whether these pixels are sunlight-illuminated pixels. If the intensity is above the threshold, and the pixel’s intensity varies more than 25% from the average of the neighboring pixels, the pixel will be “judged” as a defect pixel, and its value will be replaced by the average of the neighboring pixels.

The correction method discussed above will introduce a smoothing effect. However, TNO has done tests on the previous generations of digital sun sensors. The test results show that the centroid results from this principle can still satisfy the accuracy specification [3.1][3.2].

Some other sun sensors pay special attention to radiation issues and employ special processing in order to increase their robustness against radiation effects [3.17]. IMEC’s DARE logic cell library and layout techniques provide radiation hardness. With these techniques, the radiation tolerance is improved; however, the power consumption is increased at the same time.

Since the standard CMOS process already satisfies the radiation specification, no extra design technique was utilized for radiation hardness in the µDSS.

3.7 Summary

This chapter gave an overview of the µDSS from the system level: the system architecture, operation principle and centroiding algorithm were briefly introduced (Section 3.1, 3.2 and 3.3). The μDSS is a completely autonomous and highly integrated digital sun sensor. It determines the instant respective angle between a satellite and the sun by reading out the centroid of the sunlight projected image.

Page 58: Low-Power Low-Noise CMOS Imager Design

Overview of the micro-digital sun sensor

50

The μDSS achieves miniaturization by adopting a SoC sensing chip called APS+. Low power and low-noise design are the major challenges for the APS+ (Sections 3.4 and 3.5).

The APS+ implements centroid detection in a two-step acquisition-tracking operation mode. In order to reduce power consumption, during the sun acquisition, the APS+ works with a WTA principle. With this principle, the APS+ is able to achieve coarse centroid coordinates with much less readout burden. Thus, the bandwidth of the readout circuit is greatly decreased, leading to much lower power consumption. In order to improve the noise performance, a quadruple sampling method is adopted in the sun tracking mode. With this method, the 1/f noise and reset noise in a 3-T APS pixel can be reduced and canceled, respectively.

In the last part of this chapter (Section 3.6), the radiation consideration in the APS+ design was discussed. The process used by the µDSS satisfies the radiation specification. Meanwhile, the radiation tolerance could also be improved by both a hardware radiation-resistant design and an algorithm correction approach.

With the high performance APS+ chip design and sophisticated system architecture design, the µDSS achieves high resolution, low-power consumption and a light mass. These characteristics make it ideal for a micro-satellite application.

3.8 References

[3.1] C. de Boom et al., “Micro digital sun sensor: system in a package”, Proceeding of International Conference on MEMS, NANO and Smart Systems, pp. 322-328, Aug. 2004.

[3.2] J. Leijtens et al., “Micro systems technology: the way to shrink sun sensors”, Proceeding of International Conference on MEMS, NANO and Smart Systems, pp. 193-194, July 2005.

[3.3] C. de Boom, Internal information by TNO, Delft the Netherlands, May 2011.

[3.4] J. de Meulmeester, Internal document by DALSA Corp, “12-Bit Pipeline ADC Design Report”, June 2008.

Page 59: Low-Power Low-Noise CMOS Imager Design

Overview of the micro-digital sun sensor

51

[3.5] C. Liebe et al., “MEMS based sun sensor”, Proceeding of IEEE 2001 Aerospace Conference, pp. 1565-1572, Piscataway, United States, March 10-17, 2001.

[3.6] C. Liebe et al., “Micro Sun Sensor”, Proceeding of IEEE 2002 Aerospace conference, Big Sky, MT, USA, pp. 2263-2273, March 2002.

[3.7] F. Xing et al., “A novel active pixels sensor (APS) based sun sensor based on a feature extraction and image correlation (FEIC) technique”, Measurement Science and Technology, vol. 19, issue 12, pp. 125203:1-9, Dec. 2008.

[3.8] M. Buonocore et al., “APS-based miniature sun sensor for earth observation nano-satellites”, Acta Astronautica, vol. 56, issue 1-2, pp. 139-145, Jan. 2005,.

[3.9] S. Mobasser et al., “MEMS based sun sensor on a chip”, Proceeding of IEEE Conference on Control Applications (CCA 2003), Istanbul, Turkey, pp. 1483-1487, June 2003.

[3.10] T.-H Ding et al., “Micro-digital sun sensor with CMOS APS”, Journal of Tsinghua University (Science and Technology), pp. 203-206, Feb. 2008.

[3.11] F. Boldrini et al., “Applications of APS detector to GNC sensors”, 4th IAA Symposium on Small Satellites for Earth Observation Proceedings, Berlin, Germany, pp. 33-40, Apr. 2003.

[3.12] F. Boldrini et al., “Attitude sensors on a chip: feasibility study and breadboarding activities”, 32nd Annual AAS Guidance and Control Conference Proceedings, Colorado USA, pp. 1197-1216, February 2009.

[3.13] H. Tian et al., “Analysis of temporal noise in CMOS photodiode active pixel sensor”, IEEE Journal of Solid-State Circuits, vol. 36, no. 1, pp. 92-101, Jan. 2001.

[3.14] E. Fossum, “Active pixel sensors: are CCD’s dinosaurs?”, Proceeding of Charge-Coupled Devices and Solid-State Optical Sensors III, SPIE, vol. 1900, pp. 2-14, Feb. 1993.

Page 60: Low-Power Low-Noise CMOS Imager Design

Overview of the micro-digital sun sensor

52

[3.15] E. Fossum, “CMOS image sensors: electronic camera-on-a-chip”, IEEE Trans. Electron Devices, vol. 44, no. 10, pp. 1689-1698, Oct. 1997.

[3.16] J. Tan et al., “Radiation effects on CMOS image sensors due to x-rays”, Proceeding of International Conference on Advanced Semiconductor Devices & Mircrosystems, Smolenice, Slovakia, pp. 279-282, Oct. 2010.

[3.17] G. Meynants, “Digital sun-sensor on-a-chip for space navigation”, Image Sensors Europe (ISE) 2011, Amsterdam, the Netherlands, March 22-25, 2011.

Page 61: Low-Power Low-Noise CMOS Imager Design

53

Chapter 4

Low-Power Approach to the APS+

Low power consumption is one of the key requirements for the micro-digital sun sensor. The APS+ achieves low power by reducing the bandwidth of the readout circuit. This reduction is realized by a Winner-Take-All circuit.

Section 4.1 briefly introduces the WTA principle, which was originally a computational principle used for neural network decision-making. It was later employed by image sensors for object detection. In Section 4.2, the WTA principle implemented in the APS+ is presented. The WTA principle is enabled by a specific pixel architecture. The detailed pixel design and the profiling achieved by the pixel structure are presented in this section. After that in Section 4.3, the resolution of the WTA is discussed. In the ideal case, the sole “winner” among all the pixels decides the output level. However, if the output deviations of several pixels are smaller than the resolution value, there will not be a sole “winner” in the circuit. In this case the WTA result is deviated from the ideal level, and the profiling curve’s slope becomes steeper. In Section 4.4, the profiling result affected by the resolution issue is discussed. The method to improve the resolution is also discussed in this section.

Page 62: Low-Power Low-Noise CMOS Imager Design

Low-power approach to the APS+

54

4.1 Introduction to Winner-Take-All (WTA)

WTA is originally a computational principle applied in artificial neural networks particularly for distributed decision-making. When neurons in a certain layer compete with each other for activation, only the neuron with the highest activation stays active while all the other neurons shut down. The network model selects the input with the largest magnitude from a set of inputs by the WTA [4.1]. This principle is implemented as shown by the block diagram in Figure 4.1. The inputs are fed into the system by a number of sensing nodes. Next, they go through a competing circuit in parallel. At the end of the competition, one of the inputs takes over the tail current completely, in other words, a “winner” takes all of the tail current. This specific input is the single “winner”.

Figure 4.1 WTA block diagram.

4.1.1 Basic WTA principle

The competitive network shown in Figure 4.1 can be realized with different structures. The first MOS implementation of the current-mode WTA was proposed by Lazzaro in 1989 [4.2]. A schematic diagram of the two-input WTA circuit proposed in that paper is illustrated in Figure 4.2. In this circuit, the transistors of T1,1 and T1,2 are identical; T2,1 and T2,2 also have the same dimensions.

Figure 4.2 Schematic of a two-input WTA circuit.

Page 63: Low-Power Low-Noise CMOS Imager Design

Low-power approach to the APS+

55

First, the static analysis of the circuit in Figure 4.2 is considered. Assume the two current inputs are identical: I1=I2=Ic. Transistors T1,1 and T1,2 both sink the same amount of current and have the same gate-source voltage; thus, the drain voltages V1 and V2 must be equal. In this case, T2,1 and T2,2 have identical gates, sources and drain voltages. Therefore, they must sink the same current: IT1=IT2=1/2ITAIL.

After the static analysis, the dynamic analysis is considered with the assumption that the input condition is: I1=Ic+δ, I2=Ic. Transistor T1,1 sinks more current than in the previous case. As a result, the gate voltage is increased. Since T1,1 and T1,2 have the same gate-source voltage, the transistor T1,2 tends to sink the same current as T1,1, which is Ic+δ. However, only Ic is provided at the drain of T1,2. To compensate for this, the drain voltage of T1,2, which is V2, is decreased. For a small δ value, T1,2 still operates in saturation, and the current in this transistor is decreased by decreasing the drain voltage (V2), according to the Early effect. For a large δ value, T1,2 is pushed out of the saturation region, and V2 will be approximately 0 volts in the end. In the case of a large δ, sinceV2, which is the gate voltage of T2,2, is decreased, the current through T2,2 is also decreased to approximately 0. As a result, T2,1 takes all of the tail current ITAIL: IT1≈Ic, IT2≈0.

The circuit in Figure 4.2 has two inputs. It can be easily expanded to a WTA circuit with N inputs, where the operation principle remains the same.

From the operation analysis above, it can be concluded that a WTA circuit should satisfy two requirements: first of all, the competitive network must be highly parallel so that the comparison can be implemented in one clock cycle; secondly, the WTA process ends up with the “winner” exclusively taking over the tail current.

Many different WTA structures have been developed from the circuit in Figure 4.2. A detailed comparison of these structures is discussed in [4.3]. In [4.4], a WTA circuit which detects both the winner and runner-up is realized by inhibiting the true “winner” after it has been detected; then the circuit is free to detect the runner-up.

4.1.2 WTA in image sensor processing

In image sensor processing, the parallel processing of a complete image demands a large amount of processing circuits and wiring. However, such a computational circuit could be very costly in terms of power and space. In some specific scientific and commercial applications, the task is to select a certain object and to keep an eye

Page 64: Low-Power Low-Noise CMOS Imager Design

Low-power approach to the APS+

56

on it. These applications include sun trackers, star trackers, laser communication, etc. In these cases, the image sensor can achieve power efficiency and high speed by means of the object-selecting capability. In most cases, this capability can be realized by a WTA circuit which is applied to the image sensor.

The WTA structure proposed in Figure 4.2 is a current-mode WTA circuit. With an additional voltage-current converter, the WTA can be applied to image sensors. There are many structures which can be developed from the schematic in Figure 4.2, and most of them can be integrated with CMOS image sensors. In [4.5], a feedback loop is introduced into the WTA circuit. The output current is fed back to the input via a current mirror, increasing the input current. This feedback efficiently inhibits other nodes from becoming the winner. In [4.6], a one-dimensional element array is described. Background filtering is realized by connecting the APS output and the regular WTA circuit inputs. The advantage is that the threshold value does not have to be defined in advance. In [4.7], a two-dimensional array WTA is implemented by adopting a handshaking procedure.

In the APS+ design, the WTA has more requirements besides the ability to choose a “winner” from a group of input signals. As discussed in Chapter 3, power consumption and the silicon area are both critical. Therefore, the WTA circuit must be a simple structure so that the silicon area and power consumption are not increased by complex computational circuits. Moreover, the WTA circuit itself should also be speed- and power- efficient. Thus, power efficiency and a simple structure are the major design considerations for the WTA circuit in the APS+. The specific design will be discussed in the next section.

4.2 Achieving profiling in the APS+ with the WTA principle

The APS+ determines the sunspot centroid with a two-step acquisition/tracking working mode. Figure 4.3 summarizes the operation, working method and outputs in the different modes. In this figure, the operation in the sun acquisition mode is addressed and summarized by both the chart and the illustration. In this mode, a Region of Interest (ROI) (or the coarse location of the sunspot) is detected through a low-power profiling method which implements the WTA principle. At this moment, the realization of all these functions is based on a special pixel design, which is specifically proposed in the APS+. Therefore in this section, the design of this pixel

Page 65: Low-Power Low-Noise CMOS Imager Design

Low-power approach to the APS+

57

architecture will be presented in detail, followed by a discussion of the profiling results achieved by this pixel structure.

Figure 4.3 Overview of operations in different working modes of the APS+.

4.2.1 Pixel design principle required by the WTA

The basic components which comprise the WTA architecture in an image sensor are depicted in Figure 4.4. Besides the photodiode and WTA competition network, a voltage-to-current converter (V-I) must be implemented in each pixel. In the structure of an APS pixel, a source follower is an existing element which can already work as a voltage-to current converter. Thus, an APS pixel is a good candidate to realize the WTA principle in the APS+.

Figure 4.4 Block diagram of a WTA network of image sensor.

The in-pixel source follower can be implemented by both n-MOS and p-MOS transistors. These two cases are illustrated in Figure 4.5. Consider the case of Figure 4.5(a) with an n-MOS source follower, and assume that PD1 is illuminated with a higher intensity than PD2. By the end of integration, the relation between the two photodiode output voltages will be V1<V2. Since the source nodes of the two source followers are shorted, the SF2 will have a larger gate-source voltage, which means a

Page 66: Low-Power Low-Noise CMOS Imager Design

Low-power approach to the APS+

58

larger drain current than SF1: ISF2> ISF1. Due to the larger current of ISF2, the voltage at the common node (VC) will be decided by V2 in the end, and the current source Itail will be sunk exclusively by SF2. The stabilized level of VC is approximately V2-VTH, where VTH is the threshold voltage of the n-MOS transistor. However, the PD2 is the less illuminated pixel among the two, in other words, it is the “loser” that occupies the tail current. For this reason the n-MOS source follower cannot realize the WTA principle.

Figure 4.5 V-I converter with the n-MOS and p-MOS source followers.

Consider the case in Figure 4.5(b), and again assume PD3 is more illuminated than PD4. After integration, we have V3< V4. The source electrodes of SF3 and SF4 are connected to the column bus, thus the source-gate voltages of the two transistors

have the relation SG3 SG4V >V , resulting in different drain currents: SF3 SF4I >I . The tail

current will be completely sunk by SF3 in the end. The voltage VC will finally stabilize at approximately V3+|VTH,P|, where |VTH,P| is the absolute value of the p-MOS threshold voltage. In this case, VC is decided by the brighter photodiode PD3, or the “winner” of the two. Therefore, in order to implement the WTA principle, a p-MOS source follower should be employed in the pixel structure.

4.2.2 Complete pixel structure design for the APS+

Based on the analysis in the previous section, as long as a p-MOS source follower is implemented in pixel, either a 3-T or a 4-T APS pixel architecture can be used as

Page 67: Low-Power Low-Noise CMOS Imager Design

Low-power approach to the APS+

59

a basic component in the WTA circuit by the APS+. However, at the beginning of this project, a p-MOS transistor was not available in a 4-T pinned photodiode process. For this reason, a 3-T APS pixel was chosen as the pixel prototype.

From the discussions above, a 3-T APS pixel with p-MOS source follower was selected to be the pixel of the APS+. Besides the source follower, the other types of transistors in the pixel, including the reset transistor, row select and column select transistors, also need to be determined. These transistors can be realized by either an n-MOS or p-MOS transistor. In the APS+ application, a p-MOS was selected for its radiation hardness factor: due to radiation, positive charges are trapped in the gate oxide, leading to a net positive gate voltage. For an n-MOS reset transistor, after a sufficient dose of radiation, the device will be turned on by the positive gate charges if no control voltage is applied. As a consequence, the photodiode will be reset unexpectedly. On the contrary, a p-MOS reset transistor exhibits the opposite reaction. The transistor remains off by the positive gate charges, which is the normal status as expected. Therefore in the APS+ design, all other transistors besides the source follower are realized by p-MOS transistors.

Figure 4.6 Pixel structure in the APS+.

In conclusion, the pixel architecture in the APS+ which implements the WTA principle is shown in Figure 4.6. The pixel is similar to a typical 3-T APS, but it has two major differences: firstly, the pixel is composed of only p-MOS transistors in order to implement the WTA principle; secondly, in each pixel, an extra column select transistor (CS) was added besides the conventional row select transistor (RS) in order to enable row profiling. During the column profiling process, the RS transistors are active, while during the row profiling, the CS transistors are active.

Page 68: Low-Power Low-Noise CMOS Imager Design

Low-power approach to the APS+

60

The profiling process enabled by this specific pixel design will be explained in the rest of Section 4.2.

4.2.3 Column profiling enabled by the specific pixel design

Figure 4.7 explains the WTA working principle with an example of three pixels on a column.

Figure 4.7 WTA implemented by the specific pixel structure.

During column profiling, the CS transistors are not active (indicated in grey in Figure 4.7). The complete WTA process is explained as follows (assuming the first photodiode is the most highly illuminated):

1) At first all the pixels are reset at the same time. The voltage on the column bus (VC) is high due to the column current ID.

Page 69: Low-Power Low-Noise CMOS Imager Design

Low-power approach to the APS+

61

2) At the end of integration, the voltage at the first photodiode V1 will be the lowest of the three, because it is the most highly illuminated.

3) All the row select transistors (RS <1:3>) are turned on simultaneously, hence all the source followers in the pixels are turned on. Since V1 is the lowest, the source follower of the first pixel (SF1) will have the highest source-gate voltage and thus the largest current. At the beginning all the source followers (SF <1:3>) are active, so the level of VC drops due to the source follower current. VC will be stabilized after the column current source (ID) is completely sunk by SF1, while all the other source followers are completely turned off. In this case VC is independently decided by V1, which is the output of the brightest or the “winner” pixel. The column profiling is achieved by applying the WTA principle to each column in the pixel array.

The WTA process described above can be implemented simultaneously to all columns. Thus, the readout for the column profiling requires only one row time. In comparison, with the conventional readout method, the column profiling can only be achieved after the complete frame has been read out, which requires 368 row times. Thus the APS+ significantly reduces the power consumption by bringing down the readout bandwidth.

The image of the sunspot and the column profiling achieved by the WTA are both shown in Figure 4.8. It shows that the profiling results successfully indicate the coarse location of the sun image. In practice, instead of a single “winner”, usually more than one pixel is active during the column profiling. The slope of the profiling is decided by both the outputs of the “winner” pixel and the number of active pixels on the specific column. This resolution effect of the WTA principle will be discussed in Section 4.3.

Page 70: Low-Power Low-Noise CMOS Imager Design

Low-power approach to the APS+

62

Figure 4.8 Column profiling achieved by the WTA principle.

Page 71: Low-Power Low-Noise CMOS Imager Design

Low-power approach to the APS+

63

4.2.4 Pixel modification for row profiling

Figure 4.6 shows the pixel architecture in the APS+. An additional column select (CS) transistor is used particularly for the row profiling. During the column profiling, the pixels on the same column are shorted to the column bus by turning on the RS switches in the related pixels. Similarly by turning on the CS switches in each pixel on the row, they are shorted to the row bus, and the row bus voltage is decided by the “winner” pixel through the WTA process.

However, row profiling cannot be implemented directly with the pixel design in Figure 4.6. Since there is no current source on the row bus, the “winner” pixel cannot beat the others by exclusively sinking the current; thus the WTA cannot work. In addition, if row profiling needs to be readout directly from row buses, it needs an extra row readout circuit in addition to the conventional column readout circuit.

Figure 4.9 APS+ pixel structure and pixel array.

These two problems can be solved by modifying the pixel structure: an additional connection between the column bus and row bus in the pixels is made on the diagonal pixels of the array. This is shown in Figure 4.9. With these extra connections, every row bus in the pixel array is shorted to a corresponding column

Page 72: Low-Power Low-Noise CMOS Imager Design

Low-power approach to the APS+

64

bus; for example, the row bus and column bus highlighted in Figure 4.9 are shorted by the connection. During the row profiling, a row bus uses the current source of the corresponding column bus; the WTA results are then available on both the corresponding row and column bus, thus the row profile information can be read out by the column readout circuit as well.

4.2.5 Summary of pixel design and layout implementation

To conclude the pixel design in the previous sections, the pixels in the APS+ have two structures which are illustrated in Figure 4.10.

Figure 4.10 (a) Schematic for pixels on the diagonal; (b) schematic for pixels off the diagonal.

The pixels on and off diagonal are basically the same. They are both composed of a photodiode (PD), a reset transistor (RST), a source follower (SF), a row select transistor (RS), and a column select transistor (CS). The difference between the two is: for the pixels on the top-left to bottom-right diagonal of the pixel array, the row bus (row_bus) is connected to the corresponding column bus (col_bus) while the pixels off the diagonal have no connections. The photodiode in the pixel is composed of an n+ implantation and p-type substrate. The n-wells of all the p-MOS transistors in the pixels are all connected to 3.3V. Descriptions of all the in-pixel signals are presented in Table 4.1.

Page 73: Low-Power Low-Noise CMOS Imager Design

Low-power approach to the APS+

65

Table 4.1 In-pixel signal descriptions.

Name Type Description Vrst Input VDD 1.8V

RST Input Reset pulse, high level is 3.3V, low level is GND

RS Input Row select input, high level is 3.3V, low level is GND

CS Input Column select input, high level is 3.3V, low level is GND

col_bus Input/Output Column bus

row_bus Input/Output Row bus

The pixel pitch of the APS+ is 6.5µm. There are four transistors and one photodiode in each pixel. Figure 4.11 and Figure 4.12 present the layouts of the pixels on and off the diagonal, respectively. As shown in the figures, the large red area at the top of the pixel represents the photodiode. The blue rectangular structures at the bottom of the pixels are the gates of the four in-pixel transistors, from left to right: the reset transistor (RST), source follower transistor (SF), column select transistor (CS), and row select transistor (RS). Two power supplies are connected to each pixel: VDD1.8V and VDD3.3V. VDD1.8V is used to reset the pixel photodiode to 1.8V before integration, while VDD3.3V is the power supplied to all the in-pixel transistors.

Page 74: Low-Power Low-Noise CMOS Imager Design

Low-power approach to the APS+

66

Figure 4.11 Layout of the pixel on the diagonal.

Figure 4.12 Layout of the pixel off the diagonal.

Page 75: Low-Power Low-Noise CMOS Imager Design

Low-power approach to the APS+

67

Figure 4.11 is the layout for the pixel which is placed on the diagonal. In this pixel, the row_bus, which is metal 2, and the col_bus, which is metal 1, are connected with a VIA between the two metals. In this way, these two buses are connected with a hard connection. Figure 4.12 is the layout for the pixel off the diagonal. In this pixel, the row_bus and col_bus are still the same as in the previous pixel. The difference is that there is no longer VIA between the two metals. Therefore, the two buses are not connected in this case. However for the sake of symmetry, the metal 2 on top of metal 1 is covered at the crossing. Without this metal 2, fixed pattern noise could be introduced due to the architecture difference among the pixels.

As the APS+ is an aerospace application, single-event upsets introduced by the potential latch-up problem need cautious consideration. Latch-up is usually triggered by an unexpected current which is injected into the substrate through a junction capacitance, changing the substrate voltage. Two extra contacts in each pixel, which are connected to the n-well and p-substrate, are used to keep the well and substrate at the proper voltage level. In this way, latch-up is further prevented:

1) An extra contact to the n-well in which the p-MOS transistors are located. Each n-well is individually connected to 3.3 V. This contact is labelled as 1

in Figure 4.11 and Figure 4.12.

2) An extra ground contact within each pixel. This contact is labelled as 2 in Figure 4.11 and Figure 4.12.

4.2.6 Profiling process in the sun acquisition mode

The column profiling and row profiling were introduced in the previous sections. Based on the profiling, the ROI can be determined at the end of the acquisition mode. The timing diagram of the complete process in the acquisition mode is shown in Figure 4.13, and the corresponding pixel schematic is shown in Figure 4.9. All the rows in the pixel array are selected when either “All Row Reset”, “Column Profile” or “Row Profile” is active. The row decoder outputs a negative “RST” or “RS” pulse in every pixel when either “All Row Reset” or “Column Profile”, which are inputs to the row decoder, is a positive pulse. When “All Row Reset” is positive, all the pixels in the array are reset simultaneously. During the “Column Profile” pulse, all pixel RS transistors are active and pixels on the same column are shorted.

Page 76: Low-Power Low-Noise CMOS Imager Design

Low-power approach to the APS+

68

“Row Profile” is an input signal that directly controls the CS switches in pixels. During the “Row Profile” negative pulse, the CS transistors are active and pixels on the same row are shorted.

Figure 4.13 Timing diagram of the acquisition mode.

At the end of the integration time, every column bus holds the information of the most highly illuminated pixel (the “winner”) on each particular column, allowing column profiling. After column profiling, the same process is implemented on the row direction, and row profiling is achieved. The complete profiling measurement results are presented in Figure 4.14. At the end of the acquisition mode, the algorithm circuit defines the ROI from the profiling by means of a threshold method and outputs the coarse sunspot centroid coordinates. The ROI is a sub-pixel array of 25×25 pixels. The APS+ is then automatically switched into tracking mode. The operation in the tracking mode will be discussed in the next chapter.

Page 77: Low-Power Low-Noise CMOS Imager Design

Low-power approach to the APS+

69

Figure 4.14 Measurement results from the acquisition mode and ROI decided accordingly.

4.3 Resolution of the WTA principle

4.3.1 Qualitative analysis of the resolution in the WTA circuit

Figure 4.15 shows the column profiling results of a sunspot image using both the WTA principle (in blue) and the direct readout method of one line (in red). The two methods are both able to indicate the coarse location of the sun image; however, with different slopes. The different slopes from the two methods are due to the resolution effect of the WTA, which will be discussed in this section.

Page 78: Low-Power Low-Noise CMOS Imager Design

Low-power approach to the APS+

70

Figure 4.15 Column profiling by the WTA (blue) and by the direct readout method (red).

An example of a WTA circuit composed of n pixels is depicted in Figure 4.16. The working principle of this circuit was already explained in Section 4.2. The resolution analysis is explained by column profiling. During the column profiling process, the RS transistors is active, while the CS transistors are in-active, as depicted in light color in Figure 4.16.

Page 79: Low-Power Low-Noise CMOS Imager Design

Low-power approach to the APS+

71

Figure 4.16 Pixels implementing the WTA principle.

In the ideal case, the column current source ID is exclusively sunk by the “winner” source follower while all the other source followers are completely turned off. However, in practice, when several photodiodes are illuminated by similar intensities, more than one source follower is active and the ID is shared among them. Thus the current of the “winner” source follower is lower than ID, which leads to a lower source follower source-gate voltage under the same gate voltage. In this case, VC is stabilized at a lower level than in the case of a single “winner”. VC is exclusively decided by the “winner” only when the voltage difference between the “winner” and the “runner-up” is higher than a minimum value. This minimum voltage value is defined as the resolution of a WTA circuit.

The area illuminated by the sunlight is approximately 10×10 pixels. The columns and rows in this region may have more than one pixel with very similar outputs, and the difference in voltage is smaller than the resolution value. A certain number of active pixels with the same photodiode voltage on the same column could be a

Page 80: Low-Power Low-Noise CMOS Imager Design

Low-power approach to the APS+

72

simplified example. Figure 4.17 is the simulation result of this case. It shows that when only one pixel is active, VC reaches the ideal level; when the number of active pixels increases, the VC level decreases. In this example, the pixels have the same photodiode voltage of 1.3V. The more active pixels there are, the lower the current will be through each in-pixel source follower, thus resulting in a lower VC level. In other words, the VC level is not only decided by the brightest pixel, but also by the number of active pixels.

Figure 4.17 Column bus voltage as a function of the number of active pixels.

The readout circuit reads out the difference between a reference voltage level and VC. A lower VC value indicates a higher output amplitude. In the center region of the sunspot, not only the light intensity but also the number of bright pixels increases, thus the profiling output amplitude also increases accordingly. This explains the results in Figure 4.15, where in the bright section of the profiling, WTA outputs a steeper slope than the direct readout result. The blue curve is the profiling by the WTA, and the red curve is the readout output of the row which is located in the center of the sunspot. The WTA profiling successfully indicates the approximate location of the sunspot centroid. This explains why the WTA circuit was included in the APS+.

Page 81: Low-Power Low-Noise CMOS Imager Design

Low-power approach to the APS+

73

In the dark region on the image, only dark pixels are presented on a column or row; in other words, there is no “winner” in this case. Thus, the column current is sunk by all the in-pixel source followers, and the current in each source follower will be so low that all the source followers are pushed into the sub-threshold region.

Now that the qualitative analysis has been presented, a quantitative analysis of the resolution effect of the WTA will be presented in the next section.

4.3.2 Analytical analysis of the resolution in the WTA circuit

In an ideal case, assume that in the column of Figure 4.16, the first photodiode is so strongly illuminated that only SF1 is turned on and completely occupies ID. The value of ID is selected such that SF1 operates in the saturation region. We can obtain the relation [4.8]:

2D OX C 1 TH

1 WI μC (V -V -|V |)2 L

= , (4.1)

where μ is the mobility coefficient of holes for the p-MOS transistor, COX is the gate oxide capacitance per unit area, W and L are the width and length of the source follower, respectively, and VTH is the threshold voltage. In this equation, only a first-order approximation is used for simplification; the body effect is not considered. From (4.1), the value of VC can be achieved with:

DC 1 TH

OX

2IV =V +|V |+ WμCL

. (4.2)

Since only SF1 is active, SF2 (as well as SF3) should be turned off, thus we reach another relation:

C 2 THV -V < V . (4.3)

Combining (4.2) and (4.3) can give us the relation between V1 and V2:

D2 1

OX

2IV -V > WμCL

. (4.4)

Page 82: Low-Power Low-Noise CMOS Imager Design

Low-power approach to the APS+

74

Equation (4.4) shows the minimum difference between V2 and V1 required in order to make sure that only SF1 is active. In fact, this value is a parameter called Vd,sat, which shows how much the gate-source voltage has to exceed the threshold voltage in order to produce a certain current level under the saturation condition. In (4.4) it is shown that this value is also the resolution of this WTA circuit. It is the minimum voltage difference required for the “winner” to “beat” all other competitors and exclusively occupy the respective current source. Once several competitors have similar output voltages with a difference smaller than this resolution value, there is no absolute “winner” anymore. Instead, several source followers share the total current.

In conclusion, the resolution of the WTA circuit in the APS+ is presented in (4.4). This value is achieved with the assumption that SF1 and SF2 have no VTH variation. In fact, the threshold voltage variation among different devices could have an effect on the resolution value in (4.4). However, threshold voltage variation is a second-order parameter compared to Vd,sat.

4.4 Profiling affected by the WTA resolution in the APS+

4.4.1 Profiling with several “winners” in competition

In the sun acquisition mode, the coarse centroid location is determined based on the profiling result achieved by the WTA circuit. The resolution value of this WTA circuit was analyzed in the previous section. The resolution effect influences the slope of the profiling. In this section, this influence is studied with the example in Figure 4.16.

In the sun acquisition mode, the light intensity is quite similar throughout the sunspot area. For this reason, a couple of pixels with similar outputs could be active during profiling. In this situation, no unique “winner” beats all the other pixels. Thus, several “winners” decide the column bus voltage VC. The size of the sunspot is about 10×10 pixels. This means that in the worst case, the column current ID is shared by approximately 10 pixels. Under this condition, although the current through each active source follower is much lower than ID, the current level should still be high enough to keep the active source followers working in the saturation region. On the contrary, for a column with all non-illuminated pixels, the ID is sunk by all the source followers of the column. The current through each source follower

Page 83: Low-Power Low-Noise CMOS Imager Design

Low-power approach to the APS+

75

is so low that the transistor is pushed into the sub-threshold region. This situation will be discussed in Section 4.4.3.

If there are several “winners”, the final voltage on the column bus is lower than the ideal value. The profiling output achieves both a higher amplitude and a steeper slope than the ideal single “winner” case, as explained in Section 4.3.1. However, with a steeper slope, the profile result still successfully indicates the rough location of the sunspot centroid. In practice the output profile result will be limited by the ADC dynamic range. The column profile amplitudes in Figure 4.15 are the digital numbers out of the ADC.

If the bright pixels are illuminated by exactly the same light intensity, the column bus current ID will be uniformly distributed among the active source followers. Assume that the number of active pixels is N, the relation can be derived:

2DOX C i TH

I 1 W= μC (V -V -|V |)N 2 L

. (4.5)

Here Vi is the photodiode output voltage of any of these active pixels. The column bus voltage can be derived from (4.5):

DC i TH

OX

2IV =V +|V | WN μ CL

+i i i

. (4.6)

Compared with (4.2), the value of VC in (4.6) is lower. The Vd,sat component in

the result is decreased by a ratio of 1N

. It also indicates that the more “winners” it

has, the lower the value will be for the column bus voltage.

If the bright pixels are illuminated by slightly different light intensities, the column bus voltage will be decided by several pixels. For simplification, it is assumed that the illumination of these active pixels is uniformly increased. If the number of active pixels is j, and the diode output voltage of the most heavily illuminated pixel is V1, then the diode voltage of the k’th pixel will be:

k 1k-1V =V + α; (k=1,2...,j)

j, (4.7)

Page 84: Low-Power Low-Noise CMOS Imager Design

Low-power approach to the APS+

76

where:

D

OX

2Iα= WμCL

.

In the case of two active pixels, if V1 and V2 are the voltages of the active competitors, and (4.1) is included again in the calculation:

21 OX C 1 TH

1 WI μC (V -V -|V |)2 L

= , (4.8)

22 OX C 2 TH

1 WI μC (V -V -|V |)2 L

= , (4.9)

1 2 DI +I =I , (4.10)

where D2 1

OX

2I1V =V + W2 μCL

. From (4.8) to (4.10), the result of VC can be derived

from:

D DC 1 TH TH

OX OX

2I 2I1+ 7V =V +V V1+V 0.91W W4 μC μCL L

+ = + . (4.11)

Compared with (4.2), the value of VC in (4.11) is lower due to the current sharing.

In the case of three active pixels, V1, V2 and V3 are the diode voltages of the respective pixels:

21 OX C 1 TH

1 WI μC (V -V -|V |)2 L

= , (4.12)

22 OX C 2 TH

1 WI μC (V -V -|V |)2 L

= , (4.13)

23 OX C 3 TH

1 WI μC (V -V -|V |)2 L

= , (4.14)

Page 85: Low-Power Low-Noise CMOS Imager Design

Low-power approach to the APS+

77

1 2 3 DI +I +I =I , (4.15)

where D2 1

OX

2I1V =V + W3 μCL

and D3 1

OX

2I2V =V + W3 μCL

.

From (4.12) to (4.15), the result for VC can be achieved from:

D DC 1 TH 1 TH

OX OX

2I 2I3+ 21V =V +V V +V 0.84W W9 μC μCL L

+ = + . (4.16)

Compared with (4.2) and (4.11), the value of VC in (4.16) is reduced further.

From the above two cases, we can see that by increasing the number of active

“winners”, the final result is decreased by a certain ratio (R) of D

OX

2IWμCL

. A hand

calculation chart of the ration R is derived for different number of “winners” in Table 4.2.

In Table 4.2, the reduction ratio (R) is calculated for two cases: the “winners” have the same outputs and have uniformly increased outputs. The numbers in this table clearly show that the reduction ratio decreases as the number of “winners” increases. In addition, with the same number of “winners”, the different R value in the two cases show that the smaller output difference the “winners” have, the lower the column voltage is. The expression of the reduction ratio in Table 4.2 is only valid when the source followers of the “winners” are in the saturation region.

Page 86: Low-Power Low-Noise CMOS Imager Design

Low-power approach to the APS+

78

Table 4.2 Reduction ratio with different numbers of “winners”.

No. of “winners” R (same outputs) R (uniformly increased outputs)

1 1 1

2 0.71 0.91

3 0.58 0.84

4 0.5 0.79

5 0.45 0.75

6 0.41 0.71

7 0.38 0.67

8 0.35 0.64

9 0.33 0.59

10 0.32 0.58

n 1n

21 1 12 2

1 1 12

n n n

i i ii i n i n

n

− − −

= = =

⎛ ⎞ ⎛ ⎞+ − −⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠

∑ ∑ ∑i

4.4.2 Discussion on the sunspot region in the APS+

The discussion in the previous section acts as a theoretical calculation. In practice in the APS+, the pixels located in the sunspot center are always close to saturation level. By measuring the Photon Transfer Curve (PTC), the dynamic range of the pixel can be measured. The measurement will be discussed in Chapter 6. The result from this measurement shows that the photodiode voltage at saturation is approximately 1.1V. Thus, in this section the photodiode level of the “winner” pixels discussed will be 1.1V.

Page 87: Low-Power Low-Noise CMOS Imager Design

Low-power approach to the APS+

79

Under this condition, the value of Vd,sat ( D

OX

2IWμCL

) from the simulation is about

250mV. Assume that there are a couple of active “winners” on a column, and the voltage difference between the most and least illuminated pixel is 250mV. The voltages of all the active pixels can be expressed by (4.7). In Table 4.2, the relation between the number of “winners” and the reduction ratio (R) is presented. When the photodiode voltage is 1.1V, the column bus voltages achieved by the hand calculations based on Table 4.2 and by the circuit simulation are both listed in Table 4.3.

Table 4.3 Calculation and simulation results with different numbers of “winners”.

No. of pixels

Voltages on photodiode (V)

Calculation value (V)

Simulation value (V)

1 1.1 2.430 2.430

2 1.1/1.35 2.430 2.427

2 1.1/1.225 2.407 2.395

3 1.1/1.183/1.266 2.390 2.374

4 1.1/1.625/1.225/1.285 2.377 2.359

5 1.1/1.15/1.20/1.25/1.30 2.367 2.348

Firstly, this table shows that when pixel voltage difference is larger than the resolution value (Vd,sat), as when the inputs are 1.1V and 1.35V (second line in the table), the column bus voltage is decided independently by the pixel with the lower voltage output. In other words, in this case the column bus voltage is exclusively decided by the “winner”.

Secondly, if the voltage variation is smaller than the “resolution”, meaning the number of “winners” has increased, both the calculation and simulation values are decreased. The hand calculation and simulation results are presented in Figure 4.18. In Table 4.3, the photodiode outputs are selected based on (4.7). The figures in this

Page 88: Low-Power Low-Noise CMOS Imager Design

Low-power approach to the APS+

80

table indicate that the calculation result is always higher than the simulation result. This difference between the two values is due to the channel-length modulation, which is not considered in (4.1).

Figure 4.18 (a) Calculation and simulation results of the 1.1V photodiode voltage; (b) results of the column profiling.

Page 89: Low-Power Low-Noise CMOS Imager Design

Low-power approach to the APS+

81

Figure 4.18(a) shows the calculation and simulation results of the column voltage VC functioning with different numbers of active pixels. Two situations will be discussed here: photodiodes voltages are uniformly increased from 1.1V to 1.35V; and all the pixels have the same output voltage of 1.1V. The former case happens in an image at the edge between the dark region and sunspot area, while the latter emulates the case near the centroid of the sunspot.

The results in Figure 4.18(a) indicate that the column voltage VC decreases when the number of active pixels increases. With a certain number of active pixels, the VC level is higher when the photodiode outputs are uniformly increased than in the case of the photodiode outputs remaining the same. This is because in the former case, the current through the most heavily illuminated pixel’s source follower is higher than in the latter case, hence a higher source-gate voltage (VSG) value. As illustrated in Figure 4.16, since the gate voltages are the same (1.1V), the source voltage of the source follower in the former case must be higher than the latter. Therefore, the column voltage VC which follows the source voltage is also higher in the case of increased photodiode voltages.

Figure 4.18(b) shows the column profiling results. The profiling has different slopes in the region labeled 1 to 3. In region 1, the flat slope occurs at the border between the dark and illuminated parts. In region 2, the profiling amplitude dramatically increases with the steepest slope. This region is located near the centroid of the sunspot. Finally, in region 3, where the centroid is located, the slope is flat again. These regions correspond to the parts in Figure 4.18(a), which are also labeled as 1 to 3. From the border of the sunspot to the near centroid region, the column voltage changes rapidly from region 1 to 2, thus leading to a very steep slope in the profiling result in Figure 4.18(b). In region 3 of Figure 4.18(a), although the column voltage still decreases by increasing number of the “winners”, the decrease becomes much smaller when more than seven pixels are active. Therefore, in region 3 of Figure 4.18(b), the slope is flatter than region 2.

The variations between the calculation and simulation result in Figure 4.18(a) are due to the channel length modulation, which is not considered in (4.1). If the photodiode voltages are increased, the source voltages of the source followers will be higher than if the photodiode voltages remain the same, thus resulting in a higher

Page 90: Low-Power Low-Noise CMOS Imager Design

Low-power approach to the APS+

82

source-drain voltage (VSD) level. Therefore, the channel length modulation has a stronger effect on the calculation results in the former case.

4.4.3 Discussion on the dark region in the APS+

In the APS+ application, it can happen that all the pixels on a specific column are not illuminated by the sunlight. As illustrated in Figure 4.8, the dark level of the profiling result is decided by the output of this specific column by the WTA principle. During the column profiling, all these pixels are connected to the column bus. The column current source is uniformly divided by all the source followers because there is no “winner”. The current flowing through each source follower is so low that every source follower operates in sub-threshold region. Thus, the source-gate voltage is very low.

In the APS+, the total column current source of 5μA is shared by 368 in-pixel source followers, resulting in approximately 16nA of current in each source follower if all of them are turned on. The relation between the column bus voltage (VC as shown in Figure 4.15) and the current flowing through the active in-pixel source followers (ISF) is shown in Figure 4.19. The three curves illustrate different photodiode voltages: 1.8V (reset level), 1.75V and 1.7V. The graph clearly shows that when the current is lower than 1μA, the source followers are in the sub-threshold region. On the other hand, the source follower works in the saturation region when the current is increased.

The relation between the column bus voltage (VC as illustrated in Figure 4.16) and the current going through the active in-pixel source followers (ISF) is illustrated in Figure 4.19. The more active “winner” pixels it has, the smaller the ISF is. The three curves illustrate different voltages at the photodiode: 1.8V (reset level), 1.75V and 1.7V. The graph clearly shows that when the current is lower than 1μA, the relation between VC and ISF is nonlinear, thus the source followers are no longer operating in saturation but in the sub-threshold region. Conversely, if only one pixel is readout, the 5μA column current is occupied exclusively by the specific source follower and the source follower operates in saturation.

When a pixel is read out, the readout circuit samples the column bus voltage (VC) twice: when the photodiode is reset and after integration. The readout output is the difference between the two samples of VC. Figure 4.19 shows that when a source

Page 91: Low-Power Low-Noise CMOS Imager Design

Low-power approach to the APS+

83

follower works in different operation regions, the Vsig has different values. For example, as illustrated in Figure 4.19, when the photodiode’s reset level and video level are 1.8V and 1.75V, respectively, if the source followers in the active pixels work in the saturation region, the output level of Vsig is Vsig1; if the source followers work in sub-threshold region, Vsig level is Vsig2. In the APS+, the latter situation happens to the columns with only un-illuminated pixels. Therefore, the dark level of the profiling result is decided by the source followers in the sub-threshold region, which is the Vsig2 level in Figure 4.19.

Figure 4.19 Column bus voltage (VC) output vs. in-pixel source follower current (ISF).

4.4.4 WTA resolution improvement

The WTA resolution, shown by (4.4), is D

OX

2IWμCL

. The resolution is

proportional to the square root of ID. If the pixel design is not changed, a better resolution can be achieved by lowering the column current ID. However, the settling time of the sample/hold array in the readout circuit will be increased by a lower current. A compromise has to be made between the WTA resolution and the settling time.

Page 92: Low-Power Low-Noise CMOS Imager Design

Low-power approach to the APS+

84

In the APS+, the column-level sample/hold capacitors are 2pF and the settling time with a 5μA current source is 1μs. The WTA resolution is about 250mV with the same current source.

4.5 Summary

This chapter described the low power consumption approach to the APS+ design. In the sun acquisition mode, instead of scanning all pixels in the array, the APS+ achieves the profiling of the whole image within a readout time of two lines. Under a certain update frame, the reduction in readout time leads to lower readout bandwidth. Thus, low power consumption is realized in the APS+ by reducing the bandwidth of the readout circuits.

The fast, low-power profiling method is implemented by a WTA circuit which is enabled by a specific pixel design. Thus, in this chapter, the design of this pixel structure and the execution of the profiling operation were comprehensively discussed.

Although the WTA principle is implemented by the specific pixel design, the WTA circuit has a resolution limitation. If the variation of several pixels is lower than the resolution level, the WTA cannot distinguish the sole “winner”, resulting in a steeper profiling slope. This resolution effect was analyzed both in the qualitative and analytical aspects.

In spite of the resolution effect, measurement results prove that the WTA circuit in the APS+ can successfully detect the rough location of the sunspot centroid. Based on this rough location, an ROI is determined. The ROI will be read out with the highest accuracy in the next working mode: sun tracking mode. The operation in this mode will be discussed in the next chapter.

4.6 References

[4.1] G. Carpenter et al., “A massively parallel architecture for a self-organizing neural pattern recognition machine”, Computer Vision, Graphics, and Image Processing, vol. 37, issue 1, pp. 54-115, Jan. 1987.

Page 93: Low-Power Low-Noise CMOS Imager Design

Low-power approach to the APS+

85

[4.2] J. Lazzaro et al., “Winner-take-all networks of O(N) complexity”, Proceeding of Advances in Neural Information Processing Systems, San Mateo, Canada, pp. 703-711, 1989.

[4.3] Z. Sezgin et al., “CMOS winner-take-all circuits: a detail comparison”, Proceeding of IEEE International Symposium on Circuits and Systems, Hong Kong, pp. 41-44, June 1997.

[4.4] D. M. Wilson et al., “Winning isn’t everything”, Proceedings of 1995 IEEE International Symposium on Circuits and Systems, Seattle, WA, USA, pp. 1336-1339, May 1995.

[4.5] S. P. DeWeerth et al., “CMOS current mode winner-take-all circuit with distributed hysteresis”, Electronics Letters, vol. 31, issue 13, pp. 1051-1053, June 1995.

[4.6] A. Fish et al., “CMOS current/voltage mode winner-take-all circuit with spatial filtering”, Proceedings of 2001 IEEE International Symposium on Circuits and Systems, Sydney, Australia, vol. 2, pp. 636-639, May 2001.

[4.7] Z. Kalayjian et al., “Asynchronous sampling of 2D arrays using winner-take-all arbitration”, 1996 IEEE International Symposium on Circuits and Systems, Atlanta, GA, USA, vol. 3, pp. 393-396, May 1996.

[4.8] P. Gray et al., Analysis and Design of Analog Integrated Circuits, New York: Wiley, pp. 38-48, 2001, ISBN:01-2003-5104.

Page 94: Low-Power Low-Noise CMOS Imager Design

86

Chapter 5

Low-Noise Approach to the APS+

Besides low power consumption, low noise is another key requirement for the micro-digital sun sensor. Chapter 5 discusses the low-noise approach implemented in the APS+ which is realized by a quadruple sampling method in the sun tracking mode.

In Section 5.1, the reset noise as a major noise source in a 3-T pixel is discussed. The different reset noise situations in n-MOS and p-MOS reset transistors are analyzed. In Section 5.2, an overview of the conventional Delta Double Sampling (DDS) method is briefly introduced. CMOS imagers suffer from reset noise with this readout method. In Section 5.3 the proposed quadruple sampling method is discussed in both qualitative and quantitative respects. The measurement results prove that the quadruple sampling effectively reduces the total thermal noise which contains the reset noise element. However, with the quadruple sampling method, offset can be introduced by parasitic coupling capacitors. In Section 5.4, this situation is discussed. A well-designed layout can greatly reduce the introduced offset. In the last section, images captured by the APS+ are presented.

Page 95: Low-Power Low-Noise CMOS Imager Design

Low-noise approach to the APS+

87

5.1 Reset noise in a 3-T APS pixel

As discussed in Chapter 2, there are many types of noises in an active pixel sensor (APS) pixel, such as dark and photon shot noise, reset noise and 1/f noise. For a 3-T APS pixel, the reset noise cannot be cancelled by correlated double sampling (CDS). Thus, the reset noise is its drawback compared with a 4-T pinned photodiode. However, the 3-T APS pixel architecture with p-MOS transistors is adopted in the APS+ as required by the WTA principle (Section 4.2).

The reset transistor in a 3-T APS pixel can be either a p-MOS or an n-MOS transistor. The reset with n-MOS is a soft reset while with p-MOS it is a hard reset. The difference in reset noise between n-MOS and p-MOS reset transistors is well analyzed in [5.1]. In the case of an n-MOS reset transistor, the reset transistor is operated in either the sub-threshold region or saturation region at the beginning of the reset depending on the photodiode voltage at the end of previous integration. After a short time, it goes into the sub-threshold region for the rest of reset process.

The reset noise power introduced by an n-MOS reset transistor isph

1 T2 C

k , where k is

the Boltzmann constant, Cph is the photodiode capacitor, and T is the absolute temperature.

The disadvantage of n-MOS reset transistors is image lag. At the beginning of the reset, the transistor can operate in the saturation or sub-threshold region depending on the photodiode voltage level in the last frame, leading to varying reset levels in different frames. This effect is more noticeable in a bright frame following a dark frame. The reset level of the bright frame is higher than the expected level because the reset transistor always operates in the sub-threshold region; in other words, the pixel is not fully reset. Thus, an image lag will be introduced in the bright frame.

In the case of a p-MOS reset transistor, the image lag can be eliminated because the reset transistor operates in the linear region during reset. As a consequence, the final reset voltage is the supply voltage and is independent of the initial photodiode voltage. However, this comes at the expense of an increase in the reset noise, which rises to kT/Cph. Meanwhile, noise may be introduced due to the coupling to the supply voltage [5.2].

Page 96: Low-Power Low-Noise CMOS Imager Design

Low-noise approach to the APS+

88

Figure 5.1 Overview of the operation in different modes of the APS+.

As discussed above, reset noise can be a noticeable noise source since the APS+ employs a 3-T APS pixel. Figure 5.1 summarizes the different operations in both sun acquisition and tracking mode. In the sun acquisition mode, only a rough centroid location is detected, hence the reset noise is not a major concern. However, in the tracking mode, after the APS+ reads out the region of interest (ROI), the processing circuit determines the fine centroid coordinates based on the readout results. Therefore, the noise from the image sensor will have an effect on the final centroid accuracy. In the APS+, in order to eliminate the reset noise introduced by the reset transistor, a quadruple sampling method is proposed. Compared with the conventional readout methods for a 3-T active pixel, this method cancels the correlated reset noise. One disadvantage is the noise introduced by the coupling of the supply voltage. A comparison of these two readout methods will be discussed in the following section.

5.2 Overview of the conventional readout method

A schematic of the 3-T active pixel in the APS+ is depicted in Figure 5.2. The conventional readout method for this pixel is known as Delta Double Sampling (DDS). The timing diagram of DDS is illustrated in Figure 5.3 [5.3]. The timing signals in this graph refer to the pixel schematic in Figure 5.2. In DDS, a pixel is sampled twice: at the end of the integration period (S1) and after a reset (S2). The output of the DDS action is the difference between the two samples:

2 - 1Output S S= . (5.1)

Page 97: Low-Power Low-Noise CMOS Imager Design

Low-noise approach to the APS+

89

Figure 5.2 Pixel schematic of the APS+.

Figure 5.3 Timing diagram of DDS.

With DDS, the pixel fixed pattern noise is cancelled by subtracting the two signals, and 1/f noise is greatly reduced if the interval between the two samples is short enough. The major disadvantage of DDS is that it suffers from reset noise (kT/C noise) [5.4][5.5]. In fact, the effect of the reset noise increases since the reset noise components in the two samples are not correlated.

The signals of the two samples (S1 and S2) are:

,1| |1 sig THreset V VS V − += , (5.2)

Page 98: Low-Power Low-Noise CMOS Imager Design

Low-noise approach to the APS+

90

,2| |2 THreset VS V += , (5.3)

where S1 and S2 are the signals at the output of the source follower; Vreset is the reset level of the photodiode; Vsig is the video signal; and |VTH,1| and |VTH,2| are the absolute value of the p-MOS source follower’s threshold voltages when S1 and S2 are active, which are different from each other due to body effect. The signal result of the subtraction is:

,2 ,12 1 (| | | |)sig TH THS S S V V V= − = + − . (5.4)

The noises in the two samples are expressed as following;

2 2 2 2,1 ,1,11 rst ampshot fN n n n n+ + += , (5.5)

2 2 2,2 ,2,22 rst ampfN n n n+ += , (5.6)

where N1 and N2 are the noises in the two samples, nrst,1 and nrst,2 are the reset noise components of the two samples, which are uncorrelated; namp,1 and namp,2 are the thermal noise components of the DDS amplifier during S1 and S2, respectively; nf,1 and nf,2 are the flicker noise component of the source follower; and nshot is the photon shot noise.

If the interval between the two samples is very short, the flicker noise components can be assumed to be correlated: nf,1= nf,2.

After the two samples have been subtracted, the result is digitized by an ADC; thus, noise is introduced by the ADC conversion and by extra noise sources along the readout chain. The noise in the digital output of the subtraction will be:

2 2 2 2 2 2 2,1 ,2 ,1 ,2 exrst rst amp amp ADCshotn n n n n n n+ + + + + + . (5.7)

In (5.7), nADC is the noise due to the ADC conversion and nex is the total thermal noise introduced by other extra noise sources. Equation (5.7) shows that the major noise contributions come from the reset noise, thermal noise of the amplifier and the extra noise sources, and the ADC quantization. Concurrently, the threshold variation also has an effect on the final result.

Page 99: Low-Power Low-Noise CMOS Imager Design

Low-noise approach to the APS+

91

5.3 Overview of the quadruple sampling method

The quadruple sampling method was first proposed for CCD noise cancellation [5.6]. It is based on a multiple-sampling principle: two samples of the reference level and two samples of the signal level. By subtracting the sum of the reference samples from the sum of the signal samples, the video signal voltage doubles while the uncorrelated noise increases by the square root of 2 [5.7]. In this way, the Signal-to-Noise Ratio (SNR) increases.

However, the specific quadruple sampling method employed in the APS+ mainly focuses on reset noise reduction. The proposed quadruple sampling reduces the reset noise, while the readout noise is increased due to multiple samplings and subtractions. Therefore, this method improves the noise performance only when reset noise is the dominant noise source.

Figure 5.4 Timing diagram of the quadruple sampling method.

A timing diagram of the quadruple sampling in APS+ is shown in Figure 5.4. The signals refer to the pixel schematic in Figure 5.2. In quadruple sampling, four samples are taken in one readout cycle. Samples S1 and S4 are taken when RST is active; S2 and S3 are taken at the beginning and the end of integration time, respectively. At the end, the reset noise components in S2 and S3 can be cancelled by subtraction because they are correlated in this case.

5.3.1 Qualitative analysis

A complete quadruple sampling cycle involves three subtractions; two in the analog domain and one in the digital domain (by the digital processing circuit on the

Page 100: Low-Power Low-Noise CMOS Imager Design

Low-noise approach to the APS+

92

APS+). During and after the pixel reset, S1 and S2 are taken, respectively, and the subtraction of S1-S2 is processed in the analog domain; at the end of integration and during the next reset, S3 and S4 are taken, respectively, and S4-S3 is again processed in the analog domain. As in DDS, the subtractions of S1-S2 and S4-S3 reduce the pixel fixed pattern noise and 1/f noise components. These subtraction results are digitally stored on-chip. Next, the digital outputs of the previous results are subtracted in order to cancel the reset noise. In the final result, the pixel fixed pattern noise, 1/f noise as well as reset noise, are all cancelled.

5.3.2 Quantitative analysis

The signals of the four samples are expressed as:

,11 | |THresetS VV += , (5.8)

,22 | |THresetS VV += , (5.9)

,33 | |sig THresetS V VV − += , (5.10)

,44 | |THresetS VV += . (5.11)

In these expressions, S1 to S4 are the signals at the output of the source follower; Vreset is the photodiode voltage while being reset; Vsig is the video signal; and |VTH,1| to | VTH,4 | are the absolute values of the source follower’s threshold voltages in the four samples. The reset levels of the photodiode in S1 and S4 are the same, which leads to the same body effect in the two samplings, thus | VTH,1 | = |VTH,4|. The final signal result of the quadruple sampling will be:

,2 ,3( 4 3) ( 1 2) 2 3 (| | | |)sig TH THS S S S S S S V V V= − − − = − = + − (5.12)

Compared with (5.4), (5.12) shows the same effect from the threshold variation.

The noises in the four samples (N1 to N4) are expressed as following:

2 2,1,11 ampfN n n+= , (5.13)

2 2 2,2 ,2,22 rst ampfN n n n+ += , (5.14)

Page 101: Low-Power Low-Noise CMOS Imager Design

Low-noise approach to the APS+

93

2 2 2 2,3 ,3,33 rst ampshot fN n n n n+ + += , (5.15)

2 2,4,44 ampfN n n+= . (5.16)

In these expressions, nrst,2 and nrst,3 are the reset noise at the corresponding samples, which are correlated; namp,1 to namp,4 are the thermal noise of the quadruple sampling amplifier during the four samples; nf,1 to nf,4 are the flicker noise components of the source follower; and nshot is the photon shot noise. There are a few facts to mention about these signals:

nrst,2 and nrst,3 are reset noises in the same frame: nrst,2 = nrst,3;

S1 and S2 have correlated flicker noise components: nf,1 = nf,2;

S3 and S4 also have correlated flicker noise components: nf,3= nf 4.

The subtractions of S1-S2 and S4-S3 are processed in the analog domain and converted digitally by the ADC. If the noise introduced by ADC conversion and other sources on the readout chain are considered, the noises of the two subtractions will be:

,12 2 2

,2 ,1 ,2 ,11 22 2

ADCrst amp amp exsubS SN n n n n n− = + ++ + , (5.17)

2,2

2 2 2 2,3 ,3 ,4 ,24 3

2ADCrst amp amp exsubS S shotN n n n n n n− = + + ++ + , (5.18)

where NsubS1-S2 and NsubS4-S3 are the noises of the subtractions of S1-S2 and S4-S3 respectively, nADC,1 and nADC,2 are the total noise introduced by the ADC during the two conversions, and nex,1 and nex,2 are noise from all the other sources on the readout chain. The noise in the final digital result will be:

2 2 2 2 2 2 2 2 2,1 ,2 ,3 ,4 ,1 ,2 ,1 ,2amp amp amp amp ADC ADC ex exshot n n n n n n n nn + + ++ + + + + (5.19)

If the result of quadruple sampling in (5.19) is compared with the result of DDS in (5.7), the reset noise component is removed, while the effect from the threshold variation remains the same. However, the other thermal noise components are increased due to the multiple samplings and subtractions. As a result, the total noise

Page 102: Low-Power Low-Noise CMOS Imager Design

Low-noise approach to the APS+

94

is reduced by quadruple sampling when the reset noise is higher than the readout noise. The measurement results will be presented in the next section.

5.3.3 Measurement results

In the measurements which are shown in Figure 5.5, the APS+ dark random noise is measured by both quadruple sampling and DDS. In this measurement, the threshold variation due to the body effect can be neglected because the reset and video signals are approximately equal in a dark measurement. The measured total thermal noise is 1650μV with the DDS method and 1250μV with the quadruple sampling method. The relatively high noise from the ADC conversion and the external environment hampers the noise improvement with quadruple sampling. The thermal noise measured with quadruple sampling is 24% better than with DDS. Thus, the quadruple sampling method could achieve more noise improvement with a redesign optimized in readout noise.

Figure 5.5 Histogram of the dark random noise with Quadruple Sampling (QS) and Delta Double Sampling (DDS).

5.3.4 The noise floor effect on algorithm accuracy

The measurement results in Figure 5.5 show that the noise floor with the quadruple sampling method is 1200µV. In Section 3.3.2, the effect of ADC noise on

Page 103: Low-Power Low-Noise CMOS Imager Design

Low-noise approach to the APS+

95

the centroiding accuracy was discussed. The total noise floor effect on the centroiding accuracy can be achieved with the same method.

The single-ended full input range of the on-chip 12-bit ADC is 700mV. Therefore, the digital output of the noise floor is: 1200µV/700mV × 4096 = 7.0DN. Since only 10 bits of the digital output are used by the algorithm, the equivalent noise floor in the 10-bit ADC will be: NPIX = 7.0/4 = 1.75DN.

With the 10-bit ADC, since the pixels in the centroid region will be over-saturated, the ADC output level for these pixels will be NSAT = 1023DN. The ADC output of the pixels in the non-illuminated measurement is: NDARK = 37DN.

Figure 5.6 Illustration of the centroiding algorithm.

In the APS+, the centroiding is determined by:

XD XBPOS

XC XA

S S1X' =2 S S

−−

i , (5.20)

where X'POS is defined as the sunspot centroid location referring to the center of the ROI on the x-axis. SXA to SXD are the sums of pixels in areas A to D, which is illustrated in Figure 5.6. This figure has appeared in Figure 3.7, it is recalled here for convenience.

Page 104: Low-Power Low-Noise CMOS Imager Design

Low-noise approach to the APS+

96

The numerator of (5.20) consists of the subtraction of SXD-SXB. SXD and SXB are both the sum of 189 (9×21) pixels. As a consequence, the noise floor in the

numerator should be: NNUM= PIX2 189 N 2 189 1.75 34.0DN× × = × × = .

The denominator of (5.20) is SXC-SXA. Similar to the numerator, the noise floor in

the denominator is: DEN PIXN 2 21 N 2 21 1.75 11.3DN= × × = × × = .

If the effect from the noise floor is considered, (5.20) can be modified as follows:

XD XB NUMPOS

XC XA DEN

S -S N1X' = 2 S -S N

±×

±. (5.21)

Assume that the sunspot centroid is located exactly in the center of the pixel array. In this case, the result of SXD-SXB will be 0. For a sunspot with a size of 9×9 pixels, the result of SXC-SXA = 9×(NSAT- NDARK) = 9×(1023-37) = 8874DN. The value of NDEN is 11.3DN, which can be ignored compared with SXC-SXA.

Therefore, in this case, the X'POS deviation is achieved from (3.6):

POS1 0 34.0X' = 0.0022 8874

±× = ± pixels. (5.22)

(5.22) shows that the algorithm accuracy affected by the noise floor with the quadruple sampling method is ±0.002 pixels. The resolution of this algorithm is specified to be1/64 pixels = 0.0156 pixels. Therefore, the noise with the quadruple sampling method satisfies the noise specification of the algorithm.

5.4 Consideration of offset due to parasitic capacitors

5.4.1 Motivation behind the parasitic capacitor consideration

Figure 5.7 is a schematic of APS’s column sample-hold array and analog chain. CS<k> and CR<k> are the sample-hold capacitors on the k’th column, which samples the signal and reset voltages, respectively. C1 and C2 are the parasitic capacitors on the Sig-bus and Rst-bus. CcpS<k> and CcpR<k> are the parasitic coupling capacitors between neighboring column buses, which are introduced by the neighboring long metal buses in the layout. Extra offsets at the analog output (“Amp-out” in Figure

Page 105: Low-Power Low-Noise CMOS Imager Design

Low-noise approach to the APS+

97

5.7) will be introduced by the coupling capacitors (CcpS<k> and CcpR<k> ) if they are big enough.

Figure 5.7 Schematic of the sample-hold array and analog chain.

The amplitude of the offset depends on the sequence of the “sig_sample” and “rst_sample” signals in Figure 5.7. These are the two signals that sample the voltages of the photodiode to the sample-hold capacitors. With the conventional DDS method, the sequence between the two timing signals is fixed, as referred to in the timing diagram in Figure 5.3. Thus, the offset has a fixed amplitude at a certain input level. On the other hand, with the quadruple sampling, two subtractions are completed on the analog chain: S1-S2 and S4-S3 (referring to the timing diagram in Figure 5.4). In these subtractions, the sequence between “sig_sample” and “rst_sample” is different. Thus, different offset levels are introduced into S1-S2 and S4-S3, resulting in an even larger offset than with the DDS method.

Since the quadruple sampling method is more vulnerable to the offset problem, the layout of the sample-hold array in the APS+ should be very carefully considered. There are a couple of sample-hold capacitors on each column bus (CS<k>

and CR<k> in Figure 5.7), which are both 1pF capacitors. In the layout, the length of the connecting lines of these capacitors (“SIG” and “RST” in Figure 5.7) is 1100µm. If we take, for instance, the CS<k>, in the layout it is placed next to the capacitor of CR<k-1> on the neighboring column bus. The distance between the “SIG” line of CS<k> and the “RST” line of CR<k-1> is 0.26μm. In the TSMC 0.18 process, these two metal lines introduce a coupling capacitor (CcpS<k> in Figure 5.7) which is approximately 0.1pF. Similarly, the “RST” line of the CR<k> and the “SIG” line of the CS<k+1> introduce another coupling capacitor to CcpR<k>. The value of the coupling capacitors is approximately 1/10 of the sample-hold capacitors, thus the

Page 106: Low-Power Low-Noise CMOS Imager Design

Low-noise approach to the APS+

98

effect by the coupling capacitors is not negligible. The relation between the related lines and coupling capacitors is indicated in Figure 5.8. A quantitative analysis of this effect is given in the Appendix.

Figure 5.8 Simplified layout of the sample-hold capacitors.

5.4.2 Algorithm accuracy affected by the coupling capacitors

Due to the coupling capacitors, the introduced offset is visible in a dark image. Figure 5.9 (a) is an image captured by a sensor with the layout depicted in Figure 5.8. This is an image of a 45×30 pixel array captured in dark, with an integration time of 120µs. The upper part is the pixel readout results of S1-S2; the bottom part is the readout results of S4-S3 (S1 to S4 refer to Figure 5.4). In the dark condition, the outputs of S2 and S3 should be very close. Thus, the results of S1-S2 and S4-S3 are expected to have the same level. However, as the image in Figure 5.9 (a) shows, the average level of the upper part is higher than the bottom part. The main reason for this difference is the different offsets in S1-S2 and S4-S3. In the measurement in Figure 5.9 (a), the average level difference between the two parts is about 50mV (200DN with a 12-bit ADC). According to simulations, the input column bus voltage (C-bus<k> referring to Figure 5.7) in this case is approximately 3.0V.

As shown in (5.20), in the APS+ the centroiding is determined by subtracting the sum of the pixel groups. As a consequence, the introduced offset should be proportional to the subtraction result. According to measurement, the input column bus voltages in the illuminated and non-illuminated pixels maximally differ by 700mV. The size of the sunspot is 10×10, and it is illuminated uniformly in all directions. Thus, the gradient between two pixels is approximately 700mV/5 =

Page 107: Low-Power Low-Noise CMOS Imager Design

Low-noise approach to the APS+

99

140mV. As discussed in the quantitative analysis in the Appendix A.2, the offset is in proportion to the input voltage on the column bus. In the measurement in Figure 5.9 (a), a 3V input results in a 50mV offset, hence a 140mV variation should lead to a 2.3mV offset. Assume each pixel has a 2.3mV offset noise: its effect on the centroiding accuracy can be derived by the same calculation presented in Section 5.3.4. With the expression 2.3 / 700 4096 / 4 3.4PIXN mV mV DN= × = , the result of

(3.7) becomes 0.008 pixels. The expected resolution of this algorithm is 1/64 pixels = 0.0156 pixels. The effect due to offset which is about 1/2 of the resolution, is not negligible compared to the resolution. Thus, the layout in Figure 5.8 needs to be improved.

Figure 5.9 Dark images captured by sensors of (a) layout introduced coupling capacitors; (b) modified layout.

5.4.3 Layout modification for coupling capacitor reduction

In order to reduce the offset, the parasitic coupling capacitors need to be minimized by layout modification. The simplified graph of the modified layout is shown in Figure 5.10. The “SIG” and “RST” lines (as referred to in Figure 5.7) of the sample-hold capacitors on neighboring column buses are isolated by GND lines. Compared with the layout in Figure 5.8, in the modified layout the distance between the two lines becomes much larger (4µm). With the TSMC 0.18 process, the total parasitic capacitor is reduced to 0.01fF/um*1000um = 10fF. In order to further reduce this parasitic capacitor, an additional ground line (GND in Figure 5.10) is

Page 108: Low-Power Low-Noise CMOS Imager Design

Low-noise approach to the APS+

100

added in between to isolate the “SIG” and “RST” lines of the sample-hold capacitors on the same column bus.

Figure 5.10 Simplified layout of the modified layout.

Figure 5.9(b) is a dark image captured by a sensor with the modified layout. The offset difference is reduced to about 5mV (20DN by 12-bit ADC) with a 3V input voltage. As discussed in the previous section, the gradient between two pixels is approximately 700mV/5 = 140mV. Since a 3V input voltage results in 5mV offset, a 140mV variation should lead to a 230µV offset. Similar to the calculation in Section 5.4.2, the algorithm accuracy affected by the offset can be evaluated again. The result of 3.7 becomes 0.0008 pixels. As long as the expecting resolution of this algorithm is 1/64 pixels = 0.0156 pixels, the effect by the offset due to parasitic coupling capacitors can be disregarded.

5.5 Images captured by the APS+

The APS+ is a sun sensor which normally operates in the acquisition/tracking mode. However, it can also work as an ordinary two-dimensional image sensor. The image in Figure 5.11 was captured by the APS+ sensor and read out by the DDS method in a conventional imaging mode. The timing diagram of the DDS method was shown in Figure 5.3.

Page 109: Low-Power Low-Noise CMOS Imager Design

Low-noise approach to the APS+

101

Figure 5.11 An image captured by the APS+ sensor and read out by DDS method.

The image in Figure 5.12 was captured by the APS+ when operating with the quadruple sampling method. In this demonstration, the APS+ uses an optical lens focusing on a halogen lamp to emulate a sunspot. The light dot in the image is not a perfect circle due to the shape of the aperture of the optical lens.

Figure 5.12 Light image captured by the APS+ with the quadruple sampling method.

During the readout with the quadruple sampling method, the two subtractions are read and digitally converted by the on-chip ADC. The digital outputs are transferred to a PC where the digital subtraction is implemented.

The complete timing diagram of all the control signals during the tracking mode is presented in the Appendix Section A.1.

Page 110: Low-Power Low-Noise CMOS Imager Design

Low-noise approach to the APS+

102

5.6 Summary

As discussed in Chapter 3, the APS+ determines the final centroid coordinates by reading out the ROI in the sun tracking mode. Therefore, noise performance should be optimized in this mode. In this chapter, the low noise approach used by the APS+ was discussed.

First, in Section 5.1, the reset noise in a 3-T APS pixel by p-MOS and n-MOS reset transistors was discussed and compared. The p-MOS reset transistor has a higher reset noise level than the n-MOS due to a hard reset. However, as discussed in Chapter 4, p-MOS reset transistor is employed in the APS+ both for the WTA profiling method and for radiation hardness. Therefore, a specific sampling method which reduces reset noise was proposed, which is called the quadruple sampling method.

For comparison, an overview of the conventional DDS readout method was presented in Section 5.2. After that, the implementation of the quadruple sampling method was discussed in Section 5.3. As the name indicates, four samples are taken during a complete quadruple sampling cycle, and three subtractions are involved: two in the analog domain and one in the digital domain. The proposed quadruple sampling reduces the reset noise while the readout noise is increased due to multiple samplings and subtractions. Measurement results show that compared with the DDS method, the quadruple sampling method decreases the total thermal noise by 24%.

Due to the specific timing, the quadruple sampling method is more vulnerable to the parasitic coupling capacitors introduced by the layout. The offset has an effect on the accuracy of the centroiding algorithm. Section 5.4 presented the layout proposed to reduce the offset. Measurements show that the offset in a carefully designed layout can satisfy the resolution specification.

In the last section, the images captured by the APS+ were presented. The APS+ can read out an image both with the conventional DDS method and with the quadruple sampling method.

Page 111: Low-Power Low-Noise CMOS Imager Design

Low-noise approach to the APS+

103

5.7 References

[5.1] H. Tian, B. Fowler and A. El Gamal, “Analysis of temporal noise in CMOS photodiode active pixel sensor”, Journal of Solid-State Circuits, vol. 36, issue 1, pp. 92-101, Jan. 2001.

[5.2] K. Singh, “Noise analysis of a fully integrated CMOS image sensor”, Proceedings of SPIE, vol. 32, pp. 285-288, Jan. 1999.

[5.3] A. El Gamal and H. Eltoukhy, “CMOS image sensors”, IEEE Circuits & Devices Magazine, pp. 6-20, May/June 2005.

[5.4] E. R. Fossum, “Active pixel sensors: are CCD’s dinosaurs?”, Proceeding of Charge-Coupled Devices and Solid-State Optical Sensors III, SPIE, vol. 1900, pp. 2-14, Feb. 1993,

[5.5] E. R. Fossum, “CMOS image sensors: electronic camera-on-a-chip”, IEEE Trans. Electron Devices, vol. 44, no. 10, pp. 1689-1698, Oct. 1997.

[5.6] G. R. Hopkinson and D. H. Lumb, “Noise reduction techniques for CCD image sensors”, Journal of Physics E: Scientific Instruments, vol. 15, issue 11, pp. 1214-1222, Nov. 1982.

[5.7] J. Solhusvik, F. Dosiere and J. A. Farre, “Low-noise CCD signal acquisition techniques”, Proceedings of Infrared Readout Electronics, pp. 227-236, June 1994.

[5.8] N. Kawai and S. Kawahito, “Noise analysis of high-gain, low-noise column readout circuits for CMOS image sensors”, IEEE Transactions on Electron Devices, vol. 51, no. 2, pp. 185-194, Feb. 2004.

[5.9] J. de Meulmeester, Internal document by DALSA Corp “12-Bit Pipeline ADC Design Report”, June 2008.

Page 112: Low-Power Low-Noise CMOS Imager Design

104

Chapter 6

APS+ Measurement Results

Chapter 6 discusses the measurement results from the APS+ tests. Section 6.1 presents the measurement related pixel characteristic evaluations, including conversion gain, full well capacity, quantum efficiency, etc. Section 6.2 shows the APS+ operation measurement results. Section 6.3 and Section 6.4 discuss the accuracy and power consumption of the APS+, respectively. In Section 6.5, the APS+ is compared with the other counterpart sun sensors in terms of resolution, accuracy, field of view, etc. The APS+ shows advantages over the state-of-the-art. In Section 6.6, the µDSS device is implemented with the APS+ chip. A conclusion of the overall performance of the APS+ is given at the end of the chapter in Section 6.7.

Page 113: Low-Power Low-Noise CMOS Imager Design

APS+ measurement results

105

6.1 APS+ pixel characteristic measurements

The pixel characteristic evaluation of the APS+ is extremely important for the µDSS design. In practice, the sunlight intensity arriving at the APS+ surface must be well-adjusted. It has to be attenuated in order to ensure that the illuminated pixels are not constantly saturated. Moreover, the light intensity should be strong enough that the pixels in the center of the sunspot are near saturation or slightly over-saturated. Therefore, the attenuation filter, which is illustrated in Figure 3.6, should be designed according to the dynamic range of the pixel, full well capacity, and quantum efficiency. The measurements that achieve these parameters are introduced in this section.

6.1.1 Pixel output swing

In this measurement, the photodiode’s output swing is investigated. Since there is no direct access to the photodiode, the swing can only be derived from the analog output of the sensor (indicated as VSensor_out in Figure 6.1).

Figure 6.1 Analog chain in the APS+.

Figure 6.1 shows the analog chain from the pixel to the sensor output in the APS+. The analog chain of CMOS image sensors was already introduced in Chapter 3. The complete analog chain consists of a p-MOS source follower in-pixel, an n-MOS source follower in the output stage, an amplifier, and charge sharing between the column sample/hold capacitor (CSk/CSR) and the bus capacitor (C1/C2).

When the photodiode is reset to 1.8V, the in-pixel source follower output voltage is 2.89V, according to simulations.

Page 114: Low-Power Low-Noise CMOS Imager Design

APS+ measurement results

106

The output of the amplifier (indicated as Amplifier in Figure 6.1) is Vref-(Vrst-Vsig). In the dark measurement, the output of the amplifier is approximately 2.35V (Vref). At this moment the Sensor_out is 1.45V , according to measurements.

The ratio between the voltage on the S/H capacitor (CSk/CSR) and the voltage on the bus capacitor (C1/C2) is 1:1.69. Thus, the voltage on the bus capacitor is decreased by a ratio of 0.58 (1/1.69). This number is estimated from the layout.

According to the numbers in the analysis above, the DC level at different stages (as indicated in Figure 6.1) can be derived as shown in Table 6.1

Table 6.1 DC level in the analog chain.

condition VPD (V) VSF (V) VAmp_out (V) VSensor_output (V)

Dark 1.8 2.89 2.35 1.45

Saturation 1.17 2.27 1.99 1.09

6.1.2 Photon Transfer Curve measurement

The Photon Transfer Curve (PTC) illustrated in Figure 6.2 is the response from an image sensor that is uniformly illuminated at different levels of light. This method is presented in [6.1]. In the first part of the curve, its slope is equal to 0, and represents the noise floor in dark. The read out noise floor is ultimately limited by on-chip readout noise from the analog chain. As the illumination is increased, the noise becomes dominated by the shot noise of the signal, which is characterized by a slope of 1/2, as can be found in the second part of the curve.

The PTC can be used to evaluate many parameters of an image sensor, including the conversion gain k (DN/e-), full well capacity (e-/pixel), dynamic range, conversion factor CF (V/e-), etc.

Page 115: Low-Power Low-Noise CMOS Imager Design

APS+ measurement results

107

Figure 6.2 An ideal photon transfer curve.

6.1.2.1 Conversion gain derived from the PTC

When the photon shot noise is the dominant noise source, the relation between a signal (DN) and its temporal noise (DN) is:

Signal = k N i , (6.1)

Noise = k Ni , (6.2)

where k is the conversion gain (DN/e-) and N is the number of photons.

From (6.1) and (6.2), the following is achieved:

log(Noise) = 0.5log(Signal) + 0.5log(k) . (6.3)

From (6.1) and (6.2), the following can also be achieved:

2Noise = k Signali . (6.4)

The conversion gain (k) can be achieved with two methods. If the PTC is depicted in the log scale as in (6.3), the 1/k value (in log scale) can be derived at the intersection of the PTC line and the horizontal axis (drawn through noise level = 1DN), as illustrated in Figure 6.2. If the PTC is depicted on a linear scale as in (6.4),

the conversion gain can also be derived from the slope of 2Noise /Signal . The

Page 116: Low-Power Low-Noise CMOS Imager Design

APS+ measurement results

108

measured PTC in both the log scale and linear scale is presented in Figure 6.3 and Figure 6.4, respectively. The PTC measurement process is described in the next section.

Figure 6.3 PTC in the log scale.

Figure 6.4 PTC in the linear scale.

Page 117: Low-Power Low-Noise CMOS Imager Design

APS+ measurement results

109

6.1.2.2 PTC measurement process

The photon transfer curve in the measurement is generated by a 10×10 pixel sub-array of pixels which is illuminated uniformly with visible light. The signal varies with different exposure times. The measurement process is explained as follows:

1) One dark image is taken SOFF,i;

2) Two images are taken with exactly the same exposure time, S1i and S2i.

3) The pixel values are averaged, yielding S(DN):

100

i OFF,ii=1(S1 -S )

S(DN)=100

∑ . (6.5)

4) Pixel non-uniformity is eliminated by differencing the two identical images, S1i and S2i, pixel-by-pixel, generating the differenced frame SDIFF,i. The noise, or standard deviation, σS(DN) of this differenced frame is given by:

2100DIFF,i DIFF,02 i=1

S

S S=

2 100σ

⎡ ⎤−⎣ ⎦×

∑ (6.6)

where SDIFF,0 is the average level of frame SDIFF,i.

5) The signal and noise level at this exposure time is achieved.

6) Two images are taken with a different exposure time; repeat 2) - 4), until the saturation level is reached.

The PTCs in Figure 6.3 PTC in the log scale and Figure 6.4 are achieved after the data has been processed in the log scale and linear scale, respectively.

6.1.2.3 Parameters derived from the PTC

The PTC in Figure 6.3 PTC in the log scale illustrates the relation between the Signal and Noise in the log scale. A trend line is achieved with a slope of 0.482, the

Page 118: Low-Power Low-Noise CMOS Imager Design

APS+ measurement results

110

intersection point of which is 1.35. The conversion gain is derived as: 1.35

1k = 10

=

0.044DN/e-.

The PTC in Figure 6.4 shows the relation between the Signal and Noise2, the slope is 0.037. From this graph the conversion gain is derived as 0.037DN/e-.

The conversion gains derived from Figure 6.3 PTC in the log scale and Figure 6.4 are in first-order agreement with each other. The conversion gain of 0.04DN/e- is used in the calculations below.

The signal at the saturation point is 2100 DN. The electrical parameters achieved from the PTC are as follows:

1) The full well capacity Q = 2100DN0.04DN/e-

= 52,500e-;

2) The pixel capacity C =3 19Q 52.5 10 1.6 10

12fFV 0.7

−× × ×= , where V is the

output swing of the photodiode. This number is derived from the measurements in 6.1.1.

3) Conversion Factor CF = 19

15

1.6 1013 V/e-

12 10μ

×

×.

6.1.3 Quantum efficiency measurement

The definition of Quantum Efficiency (QE) was introduced in Chapter 3. The expression of QE is given by:

sig phQE(λ)=N (λ)/N (λ) , (6.7)

where Nsig and Nph are the generated charge per pixel and the number of photons per pixel, respectively.

Page 119: Low-Power Low-Noise CMOS Imager Design

APS+ measurement results

111

Figure 6.5 Quantum efficiency measurement result.

The QE measurement result with the APS+ is presented in Figure 6.5. The quantum efficiency is measured as a function of the wavelength of the incoming light. The results show two specific characteristics compared with other commercial consumer or scientific image sensors:

1) The peak of QE is situated below 500 nm,

2) The peak QE is relatively low, only 25 %.

Both characteristics can be explained by the presence of the n-well in the layout, which is used to make the p-type MOS transistors. This additional n-well acts as an extra photodiode because it is biased to 3.3 V and drains a significant amount of the photon-generated electrons. Although the APS+ pixel has a relatively low QE, it is not an issue in the µDSS application. The intensity of the sunlight is so strong that it must be attenuated before it arrives at the APS+ focal plane. In the µDSS, the integration time of the APS+ is fixed at 3mS. Thus, the design of the attenuation filter, which is illustrated in Figure 3.4, must be carefully tuned according to the QE and full well capacity of the APS+ pixel in order to achieve proper incident-sunlight intensity.

Page 120: Low-Power Low-Noise CMOS Imager Design

APS+ measurement results

112

6.2 APS+ function measurement in the acquisition-tracking operation

6.2.1 Working flow

Figure 6.6 Working flow chart of the APS+.

The APS+ works as shown in the flow chart in Figure 6.6. Firstly, once powered on, the APS+ starts working in the sun acquisition mode; the ROI determines if a sunspot is present in the image; afterwards, as long as the sunspot is present in the focal plane, the APS+ will continue to work in the tracking mode for fine coordinates. Once the sunspot moves out of the ROI, the APS+ is switched back to acquisition mode for a new ROI detection.

6.2.2 APS+ output window

The data achieved by the APS+ in the sun acquisition and tracking modes were presented in Figure 4.14. In Figure 6.7, a snapshot of the APS+ output window is shown. The data received from the APS+ is displayed on the right side. The Pos X0 and Pos Y0 are the outputs of the acquisition mode, which indicate the coarse location of the sunspot. The PosXB and PosYB are the outputs of the tracking mode which present the fine position of the center of the sunspot. The latter are sub-pixel coordinates with respect to the center of the pixel, which is indicated by X0 and Y0. The full range of XB and YB is limited to ±1 pixel, which is represented by a range

Page 121: Low-Power Low-Noise CMOS Imager Design

APS+ measurement results

113

of (-64, +63). In other words, the centroid resolution of the APS+ is a 1/64 pixel pitch. If we consider that the sun sensor’s Field of View (FoV) is ±50º, the centroid resolution refers to a resolution of 0.004º in terms of the sunlight incident angle.

Figure 6.7 A snap shot of the APS+ output window.

6.3 Measurement results in the acquisition/tracking modes

The devices tested in these measurements were taped out in April 2010. They were manufactured in a TSMC 0.18 CMOS Image Sensor process. The pixel pitch was 6.5µm. The size of the pixel array was 368×368.

Page 122: Low-Power Low-Noise CMOS Imager Design

APS+ measurement results

114

Figure 6.8 Light spot image captured by the APS+ and output amplitudes of the most illuminated column and row.

Figure 6.8 shows a light spot image captured by the APS+. In this measurement, the light spot was not formed by a membrane pinhole. Instead a light spot with a proper size was achieved with the combination of a light source, a microscope objective and an optical lens. The light source was a halogen lamp (with UV filter). The microscope objective was applied in front of the halogen lamp, and the optical lens was applied above the APS+ chip surface on the test board. With this equipment, the diameter of the light spot was about 65µm, as indicated in Figure 6.8.

Figure 6.8 also shows the amplitudes of the column and row which were at the center of the light spot. The outputs indicate that the spot center was approximately at (255, 203) in this case.

Page 123: Low-Power Low-Noise CMOS Imager Design

APS+ measurement results

115

Figure 6.9 Snap shot of the output window.

Meanwhile, the APS+ output data was also sent to the host PC. Figure 6.9 is a snapshot of the output window. The chip works such that the APS+ autonomously switches from acquisition mode to tracking mode once the sun is present.

Figure 6.9 shows the centroid results when the location of the light spot is as shown in Figure 6.8. When the “SP” button is green, it indicates that a light spot has been detected, thus the APS+ outputs both coarse and fine centroid coordinates. Pos X0 and Pos Y0 show that the spot’s coarse location was: (70, 18); PosXB and PosYB show the spot’s fine location, which was (18, 29). The coarse location result achieved by the program was (70, 18), which is the position with respect to the center of the pixel array. This coordinate correspond to the pixel array index of (255, 203). This is identical to the spot center achieved in the image in Figure 6.8. (The interpretation from the program index to the pixel array index is discussed in the Appendix Section A.3.) The fine coordinate results cannot be verified in this measurement since it requires a more accurate calibration. The calibration work was implemented by TNO; this will be discussed in Section 6.7.

Page 124: Low-Power Low-Noise CMOS Imager Design

APS+ measurement results

116

The results from the measurements above show that the centroid results from the algorithm circuit in the APS+ are in good accordance with reality. The communication between the APS+ sensor, the on-chip ADC and the algorithm circuit were successful. Furthermore, the APS+ chip successfully determined the light spot’s coarse and fine location.

6.4 APS+ accuracy measurements

6.4.1 APS+ centroiding accuracy at room temperature

The centroiding accuracy of the APS+ was measured at room temperature (25ºC). A 100µm (diameter) pinhole was applied prior to the optical lens, resulting in a light spot on the pixel array. The light source was a laser pointer. A 90% attenuation filter was placed between the laser pointer and the pinhole in this measurement. The complete setup is shown in Figure 6.10.

Figure 6.10 Setup of the accuracy measurement.

The accuracy was evaluated by repeating the centroid measurement 100 times. The sigma of the measured displacement results of “Pos XB” (as shown in Figure 6.9) was 0.8DN. The digital output of “Pos XB” represents the fine coordinate of the centroid. In the APS+, the FOV of ±47º refers to ±184 pixels, and the full range of each pixel is 64DN. Thus, 1DN of the “Pos XB” output refers to 47º/184/64=

Page 125: Low-Power Low-Noise CMOS Imager Design

APS+ measurement results

117

0.004º/DN. In this way the 3σ displacement accuracy could be converted into the accuracy of the incident angle: 0.8×3×0.004 = 0.01º.

6.4.2 APS+ noise at high temperatures

The operating temperature specification of the APS+ is -40ºC to +80ºC. As the temperature increases, it is expected that both the noise of the image sensor (especially the dark shot noise) and the thermal noise of the readout circuit will increase. Therefore, the APS+ noise level at high temperature should be investigated by means of measurements.

Figure 6.11 Noise of the APS+ as a function of temperature.

Figure 6.11 shows the noise level at high temperatures normalized to the noise at room temperature (25ºC). The figure shows that the total thermal noise at 80ºC is increased by 1.7 times the level at 25ºC. As discussed in Chapter 5, the reset noise is cancelled by the quadruple sampling method; thus, the sources leading to the noise increase at high temperatures should be the dark shot noise of the image sensor and the thermal noise of the ADC and readout circuit. The dark current has a strong dependency on temperature. An empirical law states that dark current doubles with a temperature increase of 8-10K [6.2]. The measurements show that with the APS+, the increase in noise is 1.7 times over a temperature range of more than 50ºC. It indicates that the dark current is not the dominant noise source.

Page 126: Low-Power Low-Noise CMOS Imager Design

APS+ measurement results

118

Instead, the thermal noise of the ADC and readout circuit should dominate the total noise.

In Chapter 5, the noise effect on the displacement accuracy was discussed. The thermal noise floor by the quadruple sampling method at 25ºC was 1200µV, which resulted in a displacement deviation of ±0.002 pixel pitch. Equations (5.21) and (5.22) show that the relation between the noise and the displacement deviation is linear. Thus at 80ºC, the displacement deviation is ±0.003 pixel pitch. This noise effect is negligible compared with the target resolution of 1/64 (0.015) pixel pitch.

The noise performance at temperature below 25ºC was not tested. Since thermal noise is proportional to temperature, the noise at lower temperatures should be even lower than the level at 25ºC. In conclusion, the thermal noise floor does not limit the target resolution over the temperature range between -40ºC and +80ºC.

6.5 APS+ power consumption measurements

6.5.1 Power consumption of the APS+ at room temperature

One of the highlights of the APS+ is its low power consumption. The approaches to low power were already discussed in Chapter 4. The power consumption is measured in different modes: acquisition mode and tracking mode, but separately, and the autonomous mode when the sensor switches between acquisition and tracking autonomously. This measurement was performed at room temperature (25ºC) and 10fps (frame per second). The results are summarized in Table 6.2. The table shows that the power consumption of the APS+ is approximately 21mW. Of this 21mW, the on-chip ADC consumes 13mW, the digital processing circuit consumes approximately 3.6mW, and the focal pixel array and analog chain consume less than 5mW. Since more than half of the power is consumed by the ADC, the APS+ can further reduce its power consumption in an optimized ADC design, which will be discussed in Chapter 7.

Page 127: Low-Power Low-Noise CMOS Imager Design

APS+ measurement results

119

Table 6.2 APS+ power consumption in different modes at room temperature.

Mode VDD! (1.8V)

mA VDDA (3.3V)

uA

VDDIO (3.3V)

mA

Power mW

Acquisition (mode6)

1.947 282 5.127 21.34

Tracking (mode7)

1.953 295.6 5.123 21.40

Autonomous (mode3)

1.953 281 5.120 21.34

A comparison of the power consumed by the APS+ and the state-of-the-art is listed in Table 6.3. It shows that APS+ consumes 10 times less power than the other sun sensors which adopt a similar detection principle.

Table 6.3 Power consumption compared with the state-of-the-art.

Characteristic APS+

(This work) Galileo (ESA)

[6.3] SS-411 [6.4]

Year 2010 2010 2009

Power Consumption

21.34mW @ Acquisition 21.39mW @ Tracking

327mW @ Acquisition 193mW @ Tracking

75mW

It is shown in Table 6.3 that the APS+ consumes approximately 21mW in both acquisition and tracking modes. The Galileo sun sensor [6.3] consumes twice the power in the acquisition mode than in the tracking mode due to the scanning operation during the acquisition. In comparison, the APS+ achieves profiling by the low-power WTA principle in the acquisition mode; thus, the power consumption during the acquisition is reduced to the same level as in the tracking mode. The relatively high power consumption of the Galileo sun sensor also comes from the pixel design, which is optimized for cosmic radiation. The radiation specification of this specific sun sensor reaches up to 2M rad. On the other hand, the APS+ pixel requires no radiation hardness technology, and its radiation specification is 2-3k rad. The SS-411[6.4] is a mature sun sensor product available on the market. It

Page 128: Low-Power Low-Noise CMOS Imager Design

APS+ measurement results

120

consumes 3 times more power than the APS+. The higher power consumption could be due to both the different size of the pixel array and the update frame rate.

6.5.2 Power consumption of the APS+ at high temperatures

In the µDSS application, the operation temperature range of the APS+ is -40ºC to +80ºC. Thus, in order to evaluate the performance of the APS+, the power consumption should be measured at high temperatures.

Figure 6.12 Power consumption as a function of the temperature.

Figure 6.12 shows the power consumption of the APS+ from room temperature (25ºC) up to 80ºC. The measurement results show that power consumption is increased as a function of the temperature. At 80ºC, the power consumption is 23.2mW, which is approximately 1.8mW higher than the value at 25ºC. Over this temperature range, the power consumption of the ADC increases from 13mW at 25ºC to 14.8mW at 80ºC, the power of the digital processing circuit increases from 3.6mW to 3.8mW, and the power by the pixel array remains approximately the same. Thus, the increase in power consumption mainly stems from the ADC. Despite slight increases, the power consumption of the APS+ is roughly stable in its operation temperature range.

Page 129: Low-Power Low-Noise CMOS Imager Design

APS+ measurement results

121

6.6 Comparison with the state-of-the-art

A summary of the APS+ sensor characteristics is presented in Table 6.4. The conversion gain, full well capacity and dark column FPN are derived from measurements.

Table 6.4 APS+ sensor characteristics.

Process Technology 0.18μm 1P4M

Pixel Pitch 6.5μm × 6.5μm

Fill Factor 30%

Effective Pixels 368 × 368

Conversion Factor 13μV/e-

Full Well Capacity 52,500e-

APS

+

Dark Column FPN 0.6%

A comparison of the APS+ and other recently reported sun sensors are listed in Table 6.5. The Galileo sun sensor was developed for the ESA satellite program [6.3]. The SS-411 is a mature sun sensor product available in the space market nowadays [6.4]. Both the Galileo sun sensor and the APS+ are SoC solutions, while the SS-411 is a combination of multiple chips. The detection principles of the Galileo and APS+ are both single pin-hole methods; the SS-411 adopts a multi-aperture method.

Page 130: Low-Power Low-Noise CMOS Imager Design

APS+ measurement results

122

Table 6.5 The μDSS performance compared with the state-of-the-art.

Characteristic μDSS (This work)

Galileo (ESA) [6.3]

SS-411 [6.4]

Year 2010 2010 2009

Chip Size 5mm ×5mm 11mm ×11mm Not available

Pixel Array 368 × 368 512 × 512 Not available

Integration SoC SoC Multi-chip

Power Consumption

21.34mW @ Acquisition 21.39mW @

Tracking

327mW @ Acquisition 193mW @ Tracking

75mW

Power Supply 3.3V for analog 1.8V for digital

3.3V for analog 1.8V for digital

5V

FOV ±50º ±64º ±70º

Operating Temperature

-40ºC to +80ºC -40ºC to +70ºC -25ºC to +70ºC

Accuracy 0.01º (3σ) 0.024º (3σ) 0.11º (2σ)

Resolution 0.004º <0.005º Not available

μDSS

vs.

coun

terp

arts

Detection Principle

Single pinhole Single pinhole Multiple-aperture

The Galileo implements a two-step acquisition-tracking working mode, the same as the APS+. The advantage is that it is carefully designed for radiation hardness. However, the disadvantage is the relatively high power consumption. Although the APS+ also works in the acquisition-tracking mode, it implements the winner-take-all principle in the acquisition mode in order to lower the power consumption further. The result is that the APS+ consumes 10 times less power than the Galileo sun sensor. Although the APS+ does not use the specific radiation hardness technology, it can withstand the radiation specifications of 20krad to 30krad in this application [6.5].

The APS+ has the smallest pixel array size of the three. The small pixel array leads to a limited Field of View (FoV). However, the FoV can be enlarged simply by incorporating a larger pixel array without any need to change the other chip

Page 131: Low-Power Low-Noise CMOS Imager Design

APS+ measurement results

123

components. To summarize, Table 6.5 shows the APS+ improvements in power consumption, chip size, accuracy, resolution and integration density.

6.7 µDSS in-package

6.7.1 The APS+ layout and chip micrograph

The APS+ chip micrograph is shown in Figure 6.13. It is composed of three major blocks: the APS, which is the CMOS image sensor; the on-chip ADC; and the digital processing circuit, which includes the signal generator, algorithm and I/O circuits.

Figure 6.13 Micrograph of the APS+.

Page 132: Low-Power Low-Noise CMOS Imager Design

APS+ measurement results

124

6.7.2 The µDSS package

At the end of the test stage, the APS+ was packed in its radiation resistant package with the membrane pinhole. The photograph of the device is shown in Figure 6.14. At this moment, a cable interface was integrated into the package for communication. Once the wireless function block is developed and manufactured by TNO, this interface will be replaced with an antenna for wireless communication; thus, the size of the package can be further reduced.

Figure 6.14 (a) Cross section of the µDSS; (b) photograph of the µDSS in package [6.6].

Page 133: Low-Power Low-Noise CMOS Imager Design

APS+ measurement results

125

The measurement results of both the coarse and fine centroid coordinates were verified with this packaged µDSS device. After calibration, the measured accuracy of the µDSS was 0.007º, within a FoV of ±50º.

The work related to the fully integrated µDSS device was done at TNO.

6.8 Conclusion

In summary, the APS+ is a fully autonomous sun sensor chip. It consumes 21mW of power at 10fps, which is 10 times less than any prior state-of-the-art SoC. This is realized by using the two step acquisition-tracking operation mode and the fast and low power profiling method, which are implemented by the WTA principle. The proposed pixel design not only enables the WTA principle but also eliminates the need for an extra row readout circuit. Further in the tracking mode, the quadruple sampling reduces the thermal noise by 24% compared with DDS. The APS+ high performance image sensor and smart algorithm enable the μDSS to achieve an accuracy of 0.007º in its field of view (FoV) of ±50º.

6.9 References

[6.1] J. R. Janesick et al., “Charge-coupled device charge-collection efficiency and the photon-transfer technique”, Optical Engineering, vol. 26, no. 10, pp. 972-980, Oct. 1987.

[6.2] A. Theuwissen, “Image capturing, image sensors, technologies and applications”, CEI-Europe course, Copenhagen, Denmark, pp. 145-160, 2007.

[6.3] F. Boldrini et al., “Attitude sensors on a chip: feasibility study and breadboarding activities”, 32nd Annual AAS Guidance and Control Conference Proceedings, Breckenridge, CO, USA, pp. 1197-1216, Feb. 2009.

[6.4] Data sheet from Sinclair Interplanetary website: {http://www.sinclairinterplanetary. com/digitalsunsensors}, accessed July 2011.

Page 134: Low-Power Low-Noise CMOS Imager Design

APS+ measurement results

126

[6.5] J. Leijtens et al., “The APS+ and why we dare going without DARE”, 3rd International Workshop on Analog and Mixed Signal Integrated Circuits for Space Applications, Noordwijk, the Netherlands, Sept. 5-7, 2010.

[6.6] J. Leijtens, Internal information by TNO, Delft, the Netherlands, Nov. 2011.

Page 135: Low-Power Low-Noise CMOS Imager Design

127

Chapter 7

Summary and Future Work

In this thesis, a new pixel structure is proposed. This pixel design enables a WTA principle for profiling, and further realizes a low power consuming acquisition/tracking operation mode. Besides the pixel design, a quadruple sampling method is proposed for low noise design. Chapter 7 summarizes the work in this thesis and discusses an overview of future work.

Page 136: Low-Power Low-Noise CMOS Imager Design

Summary and future work

128

7.1 Summary

This thesis describes the complete design of the APS+. It is a fully autonomous sun sensor chip. It achieves a resolution of 0.004º over the operation temperature range of -40ºC to +80ºC. It consumes 21mW of power at 10fps, which is 10 times less than prior state-of-the-art SoCs. The µDSS device, which is realized by the APS+, achieves an accuracy of 0.007º (3σ) in its field of view (FoV) of ±50º.

The major achievements are summarized as follows:

An APS+ sun sensor has been designed and manufactured. It tracks the sunlight incident angle by reading out the centroid coordinates of the sunspot. The operation is implemented by a two-step acquisition/tracking mode. The coarse location is first achieved in the acquisition mode by profiling; afterwards, the fine location is determined in the tracking mode by reading out the pixels in the coarse area. The operation principle is discussed in Chapter 3.

A specific 3T active pixel design has been proposed. This pixel enables profiling by means of the WTA principle. With this principle, the profiling of the whole pixel array can be achieved within an equivalent readout time for two lines. The short acquisition time greatly reduces the bandwidth of the readout circuit, thus reducing the power consumption. The pixel design is presented in Chapter 4.

The pixel array has been modified in such a way that the row bus voltage can be readout by the column bus readout circuit. Thus, the readout circuit is simplified by eliminating the row bus readout circuit. This modification is also discussed in Chapter 4.

A quadruple sample method has been proposed for the tracking mode. This method is applied in order to reduce the reset noise and 1/f noise with the 3T pixel structure. In a complete quadruple sampling process, four samplings are taken; two time analog subtractions are completed among the four samplings; one subtraction is digitally completed between the previous two analog results. With this method, the reset noise is cancelled at the expense of an increased readout thermal noise. A dark random noise measurement shows

Page 137: Low-Power Low-Noise CMOS Imager Design

Summary and future work

129

that the thermal noise measured by quadruple sampling achieves 24% less thermal noise than by DDS. This proposed readout method is discussed in Chapter 5.

The APS+ chip achieves a resolution of 1/64 pixel pitch, which refers to 0.004º in terms of the sunlight incident angle. The 3σ accuracy is 0.01º. The related tests are discussed in Chapter 6.

The APS+ chip has been tested at high temperatures. The operation temperature of the μDSS device ranges from -40ºC to +80ºC. Many parameters of the image sensor depend on temperature: e.g. thermal noise is proportional to temperature, and dark current doubles every 6ºC to 8ºC. Thus, low temperature is in fact a favorable condition for image sensors. As a consequence, the APS+ needs to be tested over the high temperature range. In this thesis, the noise performance and power consumption of the APS+ are tested over room temperature to 80ºC. The total thermal noise at 80ºC is 1.7 times of that at 25ºC; the power consumption at 80ºC is increased by 8% from 25ºC to 80ºC. These measurement results are presented in Chapter 6.

7.2 Future work

7.2.1 4T pixel applied to APS+

As discussed in Chapter 3, the APS+ design must employ the 3T active pixel structure due to the WTA principle requirement. The WTA can only be implemented by a p-MOS in-pixel transistor, which was not available in a pinned photodiode 4T pixel process until several years ago.

However, p-MOS in-pixel transistors are now available in a standard 4T CIS process. Thus, today the pixel in the APS+ can be realized by a 4T pixel structure. The profiling timing is adjusted by adding a transfer gate (TG) pulse, as shown in Figure 7.1.

Page 138: Low-Power Low-Noise CMOS Imager Design

Summary and future work

130

Figure 7.1 Timing chart for profiling with a 4T active pixel.

The advantage of 4T pinned photodiode is that the real correlated double sampling (CDS) can be implemented. In the APS+ design presented in this thesis, the quadruple sampling is proposed in order to reduce the major noise source resulting from the 3T active pixel, which is the reset noise or so-called kTC noise. On the contrary, the reset noise can be completely cancelled by real CDS. Thus, the readout in the tracking can be simplified by CDS with a 4T active pixel. In this case, the 1/f noise becomes the major noise source. This type of noise can be reduced with a buried-channel source follower together with CDS.

The disadvantage of the 4T pixel is the reduced fill factor. However, this is acceptable for the µDSS application, since the sunlight intensity is always strong enough in space. The attenuation filter needs to be adjusted according to the quantum efficiency of the new pixel.

Another disadvantage is that an additional control signal-TX is required, thus causing the timing control to be more complex and the system to be possibly less reliable. This should be verified by tests.

7.2.2 Column ADC implementation

The current APS+ design implements both chip-level double sampling and a chip-level ADC. The relatively low conversion speed of the chip-level ADC is not a bottleneck in this low frame rate application.

However, the chip-level ADC has a disadvantage in the aspect of noise. Compared with a column-level ADC, the chip-level ADC requires a much higher bandwidth since it reads out the pixel array row-by-row. On the analog chain of the

Page 139: Low-Power Low-Noise CMOS Imager Design

Summary and future work

131

chip-level ADC approach, the gain of each analog circuit is typically limited to one, thus each sub-circuit introduces significant contribution to the total noise over the wide bandwidth [7.2].

On the other hand, a column level ADC is able to read out the pixels on one row concurrently; thus, the readout bandwidth is much lower than chip-level ADC. The total noise of all sub-circuits over the bandwidth is also significantly reduced.

In recently years, many different structures of column level ADC have been proposed. The most popular ones include the Single-Slope ADC [7.3], SAR ADC [7.4] and cyclic ADC [7.5], etc. For space application, the chip area of the APS+ is very critical. Thus, the APS+ requires an ADC with a simple structure. At the same time, the ADC speed is not critical since the frame rate is relatively low: 10fps.

Among the ADCs mentioned above, the digital-to-analog converter in the SAR ADC occupies a large area and is difficult to fit into the pixel pitch; the capacitors used in the cyclic ADC also require chip area and introduce mismatching problems. Thus, the Single-Slope ADC, which has the simplest structure, could be the best candidate.

Since the column ADC reduces the readout bandwidth, it provides a solution for lower readout noise in a redesign. In addition, since the frame rate of the APS+ is relatively low (10 fps), the multiple-sampling method could be applied to the APS+ with a higher pixel rate. Readout noise could be further reduced with the combination of a column ADC and multiple-sampling.

Besides the better noise performance, the column ADC also makes an improved readout method possible for the APS+. This will be explained in the following section.

7.2.3 Optimized readout method by column ADC

If column ADC design is implemented in the APS+, the readout method could be further optimized in terms of speed and power consumption. The readout methods in the sun acquisition and tracking modes by the column ADC are illustrated in Figure 7.2.

Page 140: Low-Power Low-Noise CMOS Imager Design

Summary and future work

132

Figure 7.2 (a) Profiling read out concurrently by a column ADC; (b) assignment of pixels in ROI read out by column ADC.

In the sun acquisition mode, the current APS+ sequentially reads out the profiling by the chip-level ADC. With the column ADC, the profiling can be read out concurrently. Each column output is assigned to one column ADC.

In the sun tracking mode, the column ADCs can be fully utilized by being assigned to the pixels in the ROI. In this way, all the pixels in the ROI can be read out simultaneously. The column ADCs are divided into different blocks, where each block is assigned to a row in the ROI. Each block consists of the same number of column ADCs as there are pixels per row. This is illustrated in Figure 7.2 (b). In the final design of the APS+, the size of the pixel array is 512×512, and the active pixel array in the ROI is 21×21 (441 pixels). Therefore, the total number of the 512 column ADCs can be assigned to the 441 pixels in the ROI.

With these adapted readout methods, the readout speed in both the acquisition and tracking modes can be increased. Since the operation time of the APS+ is reduced, at the same frame rate, the sensor can stay in the stand-by mode longer, during which the power supply can be turned off to save power. In other words, the APS+ can further reduce the power consumption by increasing the readout speed.

7.2.4 Further component integration

At this moment, in the µDSS the APS+ has not yet been integrated with the RF communication and solar cell blocks. The power is supplied by a power cable and

Page 141: Low-Power Low-Noise CMOS Imager Design

Summary and future work

133

communication is implemented by an RS223 interface. The APS+ in its aluminum housing is shown in Figure 7.3 (membrane and pinhole are not included).

Figure 7.3 APS+ in the aluminum housing (photograph by TNO).

The APS+ needs two power supplies: 1.8V for the digital circuit and 3.3V for the analog circuit. In the µDSS shown in Figure 7.3, the voltage regulators are realized with discrete chips. The size of the complete housing is approximately 5cm×5cm, while the die area of the APS+ is 5mm×5mm. In a future redesign, the net weight of the system could be reduced by integrating the voltage regulators on-chip. Moreover, the size of the complete housing could also be greatly reduced if the solar cell is not mounted on the µDSS surface. Otherwise the housing size is decided by the solar cell area, which provides power to the µDSS system.

7.2.5 Light intensity detection

As described in this thesis, the APS+ detects the sunlight incident angle with high accuracy. In the µDSS application, the light intensity information is not necessary because the intensity is so high that it needs to be attenuated to prevent the pixel from being constantly saturated. However, in some other applications, both attitude and light intensity information are required. For instance, a sun sensor could be suitable for greenhouse application, where the heating system is autonomously adjusted based on the sunlight incident angle and light intensity.

Page 142: Low-Power Low-Noise CMOS Imager Design

Summary and future work

134

Figure 7.4 Profiling of varied intensities and multiple thresholds.

The APS+ can determine the sunlight intensity with a multiple-threshold method, which is shown in Figure 7.4. With this modification, the APS+ still operates in the two-step acquisition-tracking mode. During the acquisition mode, the APS+ achieves the profiling by means of the WTA principle as described in Chapter 4. However, in this application, the profiling results under varied light intensities are different in peak level, as illustrated in Figure 7.4. In order to determine the intensity, multiple threshold levels corresponding to different intensities are pre-defined on-chip. The profiling is first judged by the highest threshold. If an ROI can be determined in this case, the light intensity is at the highest level; if not, the profiling is judged by the second highest threshold and the ROI is determined again. This process is repeated until an ROI is decided by the centroid algorithm and the light intensity is derived from the threshold level. After the ROI is defined, the sun sensor works in the tracking mode as discussed in Chapter 5. The working flow in this application is modified as shown in Figure 7.5. With the multi-threshold method, no modification is necessary for the image sensor circuit. The definition and judgment of the varied threshold can be implemented by the digital circuit.

Page 143: Low-Power Low-Noise CMOS Imager Design

Summary and future work

135

Figure 7.5 Working flow with the light intensity detecting function.

7.2.6 Other potential applications with WTA technology

The WTA principle is characterized by its fast speed and low power consumption. Thus it could be very useful for the applications where speed and power are critical.

One potential application is in the laser-spot position detector in a triangulation-based 3-D vision system. With a scanning laser beam, the height of the target surface is derived from the displacement of the illuminated spot on the sensor. [7.6][7.7]. The WTA circuit can be used to detect the region of interest of the laser-spot for high-speed and low-power readout.

Another possible application could be in an eye tracker for human-computer interface. When illuminated by infrared light, the pupil becomes the largest black region in the image of an eye. The point where the user gazes at the screen can be achieved from the centroid position of the pupil in the eye image. In this application, high speed is required for high-tracking resolution and low power is necessary for the mobile environment [7.8]. Thus the WTA circuit could be an efficient technology option. However, in this application, the centroid of the darkest

Page 144: Low-Power Low-Noise CMOS Imager Design

Summary and future work

136

region is tracked, which is the opposite of the situation in the µDSS. Thus the WTA circuit introduced in Chapter 4 needs to be modified accordingly: in order to detect the darkest pixels with the WTA principle, all the in-pixel transistors need to be implemented with n-MOS transistors.

7.3 References

[7.1] X. Wang et al., “A CMOS image sensor with a buried-channel source follower”, ISSCC, San Francisco, CA, Digest Tech. Papers, pp. 62-63, Feb. 3-7, 2008.

[7.2] M. Snoeij, Analog Signal Processing for CMOS Image Sensors, PhD thesis, Delft Univ. of Technology, Delft, the Netherlands, ISBN: 978-90-9022129-8, pp. 74-111, 2007.

[7.3] M.Snoeij et al., “Multiple-ramp column-parallel ADC architectures for CMOS image sensors”, IEEE Journal of Solid-State Circuits, vol. 42, issue 12, pp. 2968-2977, 2007.

[7.4] S. Matsuo et al., “A very low column FPN and row temporal noise 8.9 m-pixel, 60 fps CMOS image sensor with 14bit column parallel SA-ADC”, IEEE Trans. Electron Devices, vol. 56, no. 11, pp. 2380-2389, Nov. 2009.

[7.5] J. H. Park., “A 0.1e- vertical FPN 4.7e- read noise 71dB DR CMOS image sensor with 13b column-parallel single-ended cyclic ADCs”, IEEE ISSCC Dig. Tech. Papers, pp. 268-269, Feb. 2009.

[7.6] D. Harrison, et al., "High-speed triangulation-based 3-D imaging with orthonormal data projections and error detection", IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 12 , issue 4, pp. 409-416, Apr. 1990.

[7.7] Wei Gao, et al., "A 100-dB-DR predictive-integration CMOS image sensor for laser range finding", IEEE Transactions on Electron Devices, vol. 56, issue 12, pp. 2987-2994, Dec. 2009.

[7.8] Dongsoo Kim, et. al, " A 200 µs processing time smart image sensor for an eye tracker using pixel-level analog image processing", IEEE Journal of Solid-State Circuits, vol. 44, issue 9, pp. 2581-2590, Sept. 2009.

Page 145: Low-Power Low-Noise CMOS Imager Design

Summary

137

Summary

This thesis describes the design method of a low-power, low-noise complementary metal-oxide-semiconductor (CMOS) image sensor. The proposed approaches are implemented on a test vehicle: a micro-digital sun sensor (μDSS). Firstly, power consumption is significantly reduced by a profiling method realizing the Winner-Take-All (WTA) principle; and secondly, thermal noise is reduced by a quadruple sampling method.

Chapter 1 provides an introduction to the background of the μDSS. It starts with a discussion about the significance of low-power and low-noise for many electronic devices including CMOS image sensors. After that, an overview of the attitude sensors is presented. Attitude sensors are divided into relative sensors and absolute sensors. The large size and heavy mass of relative attitude sensors make them unsuitable for applications where mass is critical. The characteristics of different types of absolute attitude sensors, e.g. earth horizon sensors, magnetometers, sun sensors and star trackers, are analyzed and compared. It is concluded that for the specific application of a sun sensor, a digital sun sensor is the most suitable architecture, considering the aspects of accuracy, power and weight.

The design for the µDSS has many challenges in terms of the power consumption and accuracy requirements. In order to reduce the power consumption, the APS+, which is the sensor chip of the μDSS, adopts a low-power acquisition-tracking operation mode, which is enabled by the WTA principle. First in the acquisition mode, a Region of Interest (ROI) is determined based on the profiling result, and the rough centroiding coordinates are determined. Then in the tracking mode, the final coordinates are achieved by reading out the ROI. In order to achieve a higher accuracy, thermal noise of the image sensor is reduced by a quadruple sampling applied to the APS+.

Chapter 2 firstly provides an overview of solid-state image sensors. Charge-coupled devices (CCDs) and CMOS sensors are the two types of technologies used for manufacturing solid-state image sensors. In reference to the μDSS application, a CCD is not preferred due to the difficulty of integrating it with (CMOS) transistors,

Page 146: Low-Power Low-Noise CMOS Imager Design

Summary

138

the incapability of the ROI operation and the radiation-softness of the CCD. Thus a CMOS image sensor is employed by the μDSS. In the rest of this chapter, the performance characteristics and architecture of CMOS image sensors are discussed. Some crucial performance evaluations, e.g. the pixel quantum efficiency and responsivity, full well capacity and dynamic range, signal-to-noise ratio and conversion gain, are explained. After the introduction to the 3-T and 4-T pixel architectures, the noise sources in CMOS image sensors are discussed. The noise performance with Correlated Double Sampling (CDS) is compared to that with the Delta Double Sampling (DDS) method. The advantage of CDS over DDS is the elimination of reset noise, which is one of the major noise sources in a 3-T pixel. In the last section of this chapter, the analog processing chain is briefly introduced.

In Chapter 3, the working principle of the μDSS is explained. The μDSS is a completely autonomous and highly integrated digital sun sensor. It achieves a high resolution, low power consumption and has a light mass. These characteristics make it ideally suitable for micro-satellite applications. The μDSS is composed of a sensor chip APS+, a membrane with a pin hole, and a communication block. When sunlight arrives at the focal plane through the pinhole, different pixels on the array are illuminated depending on the sunlight incident angle. The orientation information can be derived from the projective image. As the critical sensing component, the APS+ is composed of a CMOS Active Pixel Image Sensor (APS), an A-to-D converter (ADC), and a digital processing circuit. In Section 3.2, the relation between the Field of View (FoV) and the size of the pixel array is discussed. It is concluded that with a pixel array of 368×368 and 6.5μm pixel pitch, the APS+ is able to achieve a FoV of ±47º. The size of the ROI, which is 25×25, is also determined in this section with considerations made for the satellite instant angular velocity and the time interval between acquisition and tracking modes. In Section 3.3, the centroiding algorithm is briefly introduced. The sub-pixel resolution is achieved with a double balance method. The centroid inaccuracy due to the system noise can be analyzed based on this centroiding algorithm.

In Sections 3.4 and 3.5, overviews of the low-power and low-noise approaches in the APS+ are provided. The power budget of the μDSS is rigid because the power supplied by the on-satellite solar cell is limited by its size. With the two-step acquisition-tracking operation, the power consumed in the acquisition mode, when

Page 147: Low-Power Low-Noise CMOS Imager Design

Summary

139

the complete pixel array is scanned, is much higher than the tracking mode. The APS+ reduces the power consumption in the acquisition mode by narrowing down the bandwidth of the readout circuit. This reduction is achieved by a profiling method with the WTA principle. With this method, the acquisition is completed within an equivalent readout time of only two lines. A creative pixel design is proposed in order to enable the WTA principle. The pixel structure selected is a 3-T APS because of the WTA requirement, but reset noise becomes a major noise source with this structure. In order to improve the noise performance, the APS+ adopts a quadruple sampling method which reduces thermal noise including the reset noise. Detailed discussions on the low-power and low-noise design are given in Chapter 4 and Chapter 5, respectively. Section 3.6 explains the radiation considerations in the μDSS. On the one hand, the radiation hardness is strengthened by hardware, e.g. the aluminum shielding and the indium tin oxide (ITO) protective layer; on the other hand, the radiation-introduced single event upset (SEU) can be detected and corrected by the algorithm.

In Chapter 4, the low-power approach, which is achieved with the profiling method in the sun acquisition mode, is explained. The profiling is realized by the WTA with the particular pixel structure. The first section briefly introduces the principle of the WTA, which was originally a computational principle used for neural network decision-making. It is concluded that a WTA circuit should satisfy two requirements: (1) the competitive network must be highly parallel so that the comparison can be implemented in one clock cycle; and (2) the WTA process ends up with the “winner” exclusively taking over the tail current. In some CMOS image sensor applications, the task is to select a certain object and to track it. In these cases, the image sensor can achieve power efficiency and high speed by means of the object-selecting capability, which can be realized by a WTA circuit.

In Section 4.2, the profiling achieved with the WTA principle is presented. The pixel structure implemented in the APS+ is similar to a typical 3-T APS, but it has two major differences: firstly, the pixel is composed of only p-MOS transistors in order to implement the WTA; secondly, in each pixel, an extra column select transistor (CS) is added besides the conventional row select transistor (RS) in order to enable row profiling. During the column profiling process, the RS transistors are active, whereas during the row profiling, the CS transistors are active. The column

Page 148: Low-Power Low-Noise CMOS Imager Design

Summary

140

and row profiling processes are explained in this section: at the end of the integration time, every column or row bus holds the amplitude of the most heavily illuminated pixel (the “winner”) on each particular column or row. The measurement results of the profiling and the ROI determined based on the profiling are presented at the end of this section. In Section 4.3, the resolution effect of the WTA is discussed. In the ideal case, the sole “winner” among all the pixels decides the output level. However, if the output deviations of several pixels are smaller than the resolution value, there will not be a sole “winner” in the circuit. In this case the WTA result deviates from the ideal level, and the slope of the profiling curve becomes steeper. In Section 4.4, the profiling result affected by the resolution issue is discussed. It is shown that when several “winner” pixels are active during the WTA, the stabilized bus-voltage is determined by both the pixel intensities and the number of “winners”. The method to improve the resolution is also discussed in this section.

Besides low power consumption, Chapter 5 also discusses the low-noise approach implemented in the APS+ which is realized by a quadruple sampling method in the sun tracking mode. At the beginning of this chapter, the reset noise is discussed as a major noise source in a 3-T pixel. The different reset noise situations in n-MOS and p-MOS reset transistors are analyzed. The p-MOS reset transistor introduces higher reset noise than the n-MOS transistor; at the same time, the p-MOS reset transistor also eliminates image lag, which is a disadvantage of the n-MOS transistor. Since the pixels in the APS+ are constructed by p-MOS transistors for the WTA, the reset noise has to be reduced to achieve a higher accuracy. Since the final centroid coordinates are determined in the sun tracking mode, the quadruple sampling, which reduces the thermal noise, is implemented in this mode.

In Sections 5.2 and 5.3, the noise performances are compared with the conventional DDS and with quadruple sampling. An overview of the DDS shows that the reset noise power is doubled in the final reset action. On the other hand, the proposed quadruple sampling cancels the reset noise while increasing the readout noise due to the multiple samplings and subtractions. As a result, the total noise is reduced by quadruple sampling when the reset noise is higher than the readout noise. This method is discussed in both qualitative and quantitative respects. The

Page 149: Low-Power Low-Noise CMOS Imager Design

Summary

141

measurement results prove that the quadruple sampling effectively reduces the total thermal noise, which contains the reset noise element.

Section 5.4 discusses the offset introduced by parasitic coupling capacitors with the quadruple sampling. A displacement error could be introduced by the offset in the algorithm. Thus the layout needs to be well considered in order to reduce the parasitic capacitors. An optimized layout is proposed. Measurement shows that with this layout, the displacement error introduced by the offset is lower than the expected design resolution; the effect of parasitic coupling capacitors can be disregarded. In the sun tracking mode, the APS+ operates as an ordinary imager. Thus in the last section, images captured by the APS+ are presented.

Chapter 6 discusses the measurement results from the APS+ tests. Section 6.1 presents the measurement-related pixel characteristic evaluations, including conversion gain, full well capacity, quantum efficiency, etc. Sections 6.2 and 6.3 show the completely autonomous sun acquisition-tracking operation measurement results of the APS+. The working flow is: first, once powered on, the APS+ starts working in the sun acquisition mode; the ROI is determined if a sunspot is present in the image; afterwards, as long as the sunspot is present in the focal plane, the APS+ will continue to work in the tracking mode for fine coordinates. Once the sunspot moves out of the ROI, the APS+ is switched back to acquisition mode for a new ROI detection. In the measurement, the APS+ outputs and displays the ROI and the final centroid coordinates with the APS+ output window on the PC. Section 6.3 and Section 6.4 discuss the accuracy and power consumption of the APS+, respectively. In the µDSS application, the operation temperature range of the APS+ is -40ºC to +80ºC. Thus the accuracy and power consumption are both measured as a function of temperature. The results show that even at the highest operation temperature, the APS+ performance is better than the specification. In Section 6.5, the APS+ is compared with the other counterpart sun sensors in terms of resolution, accuracy, field of view, etc. The APS+ shows advantages over the state-of-the-art. In Section 6.6, the µDSS device is implemented with the APS+ chip. A conclusion of the overall performance of the APS+ is given at the end of the chapter in Section 6.7.

Chapter 7 summarizes the work in this thesis and discusses an overview of future work. In this thesis, a new pixel structure is proposed. This pixel design enables a

Page 150: Low-Power Low-Noise CMOS Imager Design

Summary

142

WTA principle for profiling, and further realizes a low power-consuming acquisition-tracking operation mode in the APS+. Besides the pixel design, a quadruple sampling method is proposed for low-noise design. The major achievements are summarized in Section 7.1. In Section 7.2, the potential future works are described. A 4-T pixel structure, which is able to realize real CDS to cancel reset noise, could be realized in a future APS+ design. A column-level ADC could achieve lower readout bandwidth, thus also lower readout noise. An optimized readout method with a column ADC is proposed to even further reduce the APS+ power consumption by increasing the readout speed. The integration of the µDSS device is not yet completely optimized. Section 7.3 discusses the approaches to further minimize the size of the µDSS device. In the µDSS application, the APS+ only reads out the sun spot centroid information. Section 7.4 proposes a simple modification, with which the APS+ will be able to read out the light intensity information as well. Thus the APS+ could be applied for applications where both attitude and light intensity information are required. For instance, it could be suitable for greenhouse application, where the heating system is autonomously adjusted based on the sunlight incident angle and light intensity.

Page 151: Low-Power Low-Noise CMOS Imager Design

Samenvatting

143

Samenvatting

Dit proefschrift beschrijft de ontwerp methode van een laag-vermogen, lage-ruis complementaire metaal oxide halfgeleider (CMOS) image sensor. De voorgestelde benaderingen worden uitgevoerd op een prototype: een micro-digitale zonnesensor (μDSS). Als eerst wordt het energieverbruik aanzienlijk verminderd door een methode die de Winner-Take-All (WTA) principe realiseert; en als tweede, wordt thermische ruis verminderd met een viervoudige bemonsteringsmethode.

Hoofdstuk 1 geeft een inleiding op de achtergrond van de μDSS. Het begint met een discussie over het belang van het laag-vermogen en de lage-ruis voor veel elektronische apparatuur, zoals CMOS-image sensoren. Daarna wordt een overzicht van de altitude sensoren gepresenteerd. Attitude sensoren zijn verdeeld in relatieve en absolute sensoren. De grote omvang en grote massa van de relatieve attitude sensoren maken ze ongeschikt voor toepassingen waar de massa van cruciaal belang is. De eigenschappen van verschillende absolute attitude sensoren, bv. aarde-horizon sensoren, magnetometers, zonnesensoren en sterren trackers, worden geanalyseerd en vergeleken. Geconcludeerd wordt dat voor de specifieke toepassing van een zonnesensor, een digitale zonnesensor de meest geschikte architectuur is, gezien de aspecten nauwkeurigheid, vermogen en gewicht.

Het ontwerp voor de μDSS heeft vele uitdagingen met betrekking tot de eisen van energieverbruik en nauwkeurigheid. Om het energieverbruik te verminderen, neemt de APS+, dat de sensor chip is van de μDSS, een laag-vermogen dataverzameling-tracking operatie modus over, die ingeschakeld wordt door het WTA-principe. Eerst wordt in de dataverzameling-modus een venster (ROI, Region of Interest) bepaald op basis van het beoordelingsresultaat, en worden de ruwe zwaartepunt coördinaten bepaald. Daarna worden in de tracking-modus de exacte coördinaten bepaald door het uitlezen van de ROI. Om een grotere nauwkeurigheid te bereiken, wordt thermische ruis van de image sensor verlaagd door viervoudige bemonstering die toegepast wordt op de APS+.

Hoofdstuk 2 geeft als eerst een overzicht van de solid-state image sensor. Ladingsgekoppelde inrichtingen (CCD’s) en CMOS sensoren zijn de twee type

Page 152: Low-Power Low-Noise CMOS Imager Design

Samenvatting

144

technieken die gebruikt worden voor het vervaardigen van solid-state image sensoren. Met betrekking tot de μDSS toepassing heeft een CCD niet de voorkeur vanwege de lastige integratie met (CMOS) transistors, het onvermogen van de ROI werking en het stralingsgevoeligheid van de CCD. Dus een CMOS-image sensor wordt gebruikt door de μDSS. In de rest van dit hoofdstuk worden de prestatie-eigenschappen en de architectuur van CMOS image sensors besproken. Een aantal cruciale prestatie-evaluaties, bv. de pixel quantum efficiëntie en responsiviteit (lichtgevoeligheid), full-well capaciteit (maximale opslagcapaciteit) en dynamische bereik, signaalruilverhouding en conversiefactor worden toegelicht. Na de introductie van de 3-T en 4-T pixel architecturen, worden de ruisbronnen in de CMOS-image sensoren besproken. De ruisprestatie met gecorreleerde dubbele bemonstering (CDS) wordt vergeleken met die van de delta dubbele bemonstering (DDS) methode. Het voordeel van CDS t.o.v. DDS is de verwijdering van reset-ruis, die één van de hoofdbronnen van ruis is in een 3-T pixel. In het laatste deel van het hoofdstuk wordt de analoge verwerkingsketen kort geïntroduceerd.

In hoofdstuk 3 wordt het werkingsprincipe van de μDSS uitgelegd. De μDSS is een volledig autonome en sterk geïntegreerde digitale zonnesensor. De sensor bereikt een hoge resolutie, een laag vermogenverbruik en heeft een kleine massa. Deze kenmerken maken hem uitermate geschikt voor micro-satelliet toepassingen. De μDSS bestaat uit een sensor chip APS+, een membraan met een speldengaatje en een communicatieblok. Als zonlicht aankomt door het speldengaatje op het oppervlak van de sensor, worden verschillende pixels op het array belicht afhankelijk van de invalshoek van het zonlicht. De oriëntatie-informatie kan worden afgeleid uit het geprojecteerde beeld. Als kritische meetcomponent bestaat de APS+ uit een CMOS actieve pixel image sensor (APS), een analoog-digitaal omzetter (ADC) en een digitaal verwerkingscircuit. In paragraaf 3.2 wordt de relatie tussen de beeldhoek (Field-of-View FOV) en de grootte van de pixel-array besproken. Geconcludeerd wordt dat met een pixel array van 368 × 368 en 6,5μm pixel pitch, de APS+ in staat is om een FoV van ±47º te bereiken. De grootte van de ROI, van 25x25, wordt mede bepaald door overwegingen met betrekking tot de hoeksnelheid van de satelliet en het tijdsinterval tussen de dataverzameling en tracking modi. In paragraaf 3.3 wordt het zwaartepunt algoritme kort geïntroduceerd. De sub-pixelresolutie wordt bereikt met een dubbelebalansmethode. De zwaartepunt

Page 153: Low-Power Low-Noise CMOS Imager Design

Samenvatting

145

onnauwkeurigheid veroorzaakt door de systeemruis kan worden geanalyseerd op basis van dit zwaartepunt algoritme.

In de paragrafen 3.4 en 3.5 worden verschillende overzichten gegeven van de laag-vermogen en de lage-ruis benaderingen in de APS+. Het beschikbare vermogen van de μDSS is beperkt omdat het vermogen van de on-satelliet zonnecel beperkt wordt door zijn grootte. Met de twee-staps dataverzameling-tracking operatie is het energieverbruik in de dataverzameling-modus, als de gehele pixel-array wordt gescand, veel hoger dan de tracking-modus. De APS+ vermindert het energieverbruik in de dataverzameling modus door het versmallen van de bandbreedte van de uitleescircuit. Deze reductie wordt bereikt door een beoordelingsmethode met het WTA principe. Met deze methode wordt de dataverzameling voltooid binnen een equivalent uitleestijd van slechts twee lijnen. Daarom wordt een creatief pixel ontwerp voorgesteld om het WTA principe mogelijk te maken. De geselecteerde pixel structuur is een 3-T APS vanwege de WTA eis, maar met deze structuur wordt de reset-ruis een grote ruisbron. Ter verbetering van het geluidsniveau, gebruikt de APS+ een viervoudige bemonstering methode die zowel thermische ruis als reset-ruis vermindert. Gedetailleerde discussies over het laag-vermogen en lage-ruis ontwerp worden respectievelijk weergegeven in hoofdstuk 4 en hoofdstuk 5. Paragraaf 3.6 licht de straling overwegingen in de μDSS toe. Aan de ene kant wordt de stralingshardheid versterkt door de hardware, bv. de aluminium afscherming en indium tin oxide (ITO) beschermlaag op het membraan; aan de andere kant kan de stralinggeïntroduceerde single event upset (SEU) worden gedetecteerd en gecorrigeerd door het algoritme.

In hoofdstuk 4 wordt de laag-vermogen benadering uitgelegd die wordt bereikt met de beoordelingsmethode in de zon-dataverzameling modus. De beoordeling wordt gerealiseerd door de WTA met een specifieke pixel structuur. Het eerste deel introduceert in het kort het principe van de WTA, die oorspronkelijk een computationeel beginsel dat gebruikt werd voor neurale netwerk besluitvorming. De conclusie is dat een WTA-circuit aan twee eisen moet voldoen: (1) het netwerk moet in hoge mate parallel zijn zodat de vergelijking kan worden geïmplementeerd in één klokcyclus; en (2) het WTA-proces eindigt als de “winner” uitsluitend de stroom in de kolom overneemt. In sommige CMOS-image sensor toepassingen is het de taak om een bepaald object te selecteren en te traceren. In deze gevallen kan

Page 154: Low-Power Low-Noise CMOS Imager Design

Samenvatting

146

de sensor energie-efficiëntie en hoge snelheid bereiken door de mogelijkheid tot object selectie, die kan worden gerealiseerd door een WTA circuit.

In paragraaf 4.2 wordt de beoordeling door middel van het WTA principe gepresenteerd. De pixelstructuur die uitgevoerd wordt in APS+ is vergelijkbaar met een typische 3-T APS, maar heeft twee belangrijke verschillen: ten eerste is de pixel samengesteld uit slechts p-MOS transistoren om de WTA uit te voeren; ten tweede wordt er in elke pixel een extra column select transistor (CS) toegevoegd naast de conventionele row select transistor (RS) om row beoordeling mogelijk te maken. Tijdens het column beoordeling proces zijn de RS transistors actief, terwijl tijdens de rij beoordeling, de CS transistors actief zijn. De column en row beoordelingsprocessen worden in deze paragraaf uitgelegd: aan het eind van de integratie tijd houdt elke column of row bus de amplitude van de zwaarst belichte pixel (de “winner”) op elke afzonderlijke/specifieke column of row. De meetresultaten van de beoordeling en de ROI die bepaald werden op basis van de beoordeling worden aan het eind van dit onderdeel gepresenteerd. In paragraaf 4.3 wordt het resolutie effect van de WTA besproken. In het ideale geval bepaalt de enige “winner” onder alle pixels het uitgangsniveau. Indien de uitgangafwijkingen van meerdere pixels echter kleiner zijn dan de resolutie waarde, zal er niet slechts één “winner” zijn in het circuit. In dit geval wijkt het WTA resultaat af van het ideale niveau en wordt de helling van de beoordelingskromme steiler. In paragraaf 4.4 wordt het beoordelingsresultaat besproken dat negatief beïnvloed wordt door de resolutie kwestie. Er wordt aangetoond dat wanneer meerdere “winner”-pixels actief zijn tijdens de WTA de gestabiliseerde bus spanning bepaald wordt door zowel de pixel intensiteiten als het aantal “winners”. De methode om de resolutie te verbeteren wordt ook besproken in dit gedeelte.

Naast het lage energieverbruik, wordt in hoofdstuk 5 tevens de in de APS+ geïmplementeerde lage-ruis benadering besproken, die gerealiseerd wordt door een viervoudige bemonsteringsmethode in de zon tracking modus. Aan het begin van dit hoofdstuk wordt de reset-ruis besproken als een hoofdbron van ruis in een 3-T pixel. De verschillende reset-ruis situaties in de n-MOS en p-MOS reset-transistoren worden geanalyseerd. De p-MOS transistor reset introduceert hogere reset-ruis dan de n-MOS transistor; tegelijkertijd verwijdert de p-MOS reset transistor ook beeldvertraging, wat een nadeel is van de n-MOS transistor. Aangezien de pixels in de APS+ vervaardigd worden door p-MOS transistoren voor de WTA, moet de

Page 155: Low-Power Low-Noise CMOS Imager Design

Samenvatting

147

reset-ruis worden gereduceerd om een grotere nauwkeurigheid te bereiken. Aangezien de laatste zwaartepunt coördinaten worden bepaald in de zon tracking modus, is de viervoudige bemonstering, die de thermische ruis vermindert, in deze modus geïmplementeerd.

In paragrafen 5.2 en 5.3 worden de ruis prestaties vergeleken met de conventionele DDS en met viervoudige bemonstering. Een overzicht van de DDS toont dat het reset-ruisvermogen verdubbeld wordt in de laatste reset actie. Anderzijds elimineert de voorgestelde viervoudige bemonstering de reset-ruis en terwijl de uitleesruis toeneemt door de veelvoudige bemonsteringen en subtracties. Hierdoor wordt de totale ruis verminderd door viervoudige bemonstering wanneer de reset-ruis hoger is dan de uitleesruis. Zowel de kwalitatieve als kwantitatieve aspecten van deze methode worden besproken. De meetresultaten bewijzen dat de viervoudige bemonstering de totale thermische ruis, die het reset-ruis element bevat, daadwerkelijk vermindert.

In paragraaf 5.4 wordt ingegaan op de fout of onnauwkeurigheid die geïntroduceerd is door parasitaire koppelingscondensatoren met de viervoudige bemonstering.. Dus er moet ook rekening worden gehouden met de lay-out om de parasitaire condensatoren te verminderen. Een geoptimaliseerde lay-out wordt voorgesteld. Metingen tonen aan dat met deze lay-out de verplaatsingsfout die geïntroduceerd is door de offset lager is dan de verwachte ontwerp-resolutie; het effect van parasitaire koppeling condensatoren kan vervolgens worden genegeerd. In de zon tracking modus werkt de APS+ als een gewone imager. Dus in de laatste paragraaf worden beelden die vastgelegd zijn door de APS+ gepresenteerd.

Hoofdstuk 6 behandelt de meetresultaten van de APS+ tests. Paragraaf 6.1 presenteert de meting in verband met pixel karakteristieke evaluaties, waaronder conversiefactor, full-well capaciteit, kwantum efficiëntie, etc. Paragrafen 6.2 en 6.3 tonen de volledig autonome meetresultaten van de APS+ in bedrijf. Het proces is als volgt: ten eerste, zodra ingeschakeld gaat de APS+ werken in de zon dataverzameling modus; de ROI wordt bepaald als een zonnevlek aanwezig is in het beeld; vervolgens, zolang de zonnevlek aanwezig is in het brandvlak, zal de APS+ blijven werken in de tracking modus voor het bepalen van de nauwkeurige coördinaten. Zodra de zonnevlek verhuist uit de ROI wordt de APS+ teruggeschakeld op de dataverzameling-modus voor een nieuwe ROI-detectie. In de

Page 156: Low-Power Low-Noise CMOS Imager Design

Samenvatting

148

meting toont de APS+ de ROI en de uiteindelijke zwaartepuntcoördinaten met de APS+-uitgang venster op de PC. Paragraaf 6.3 en paragraaf 6.4 bespreken respectievelijk de nauwkeurigheid en het stroomverbruik van de APS+. In de μDSS toepassing bedraagt de operatie temperatuurbereik van de APS+ -40ºC tot +80ºC. Dus de nauwkeurigheid en energieverbruik worden allebei gemeten als functie van temperatuur. De resultaten tonen dat zelfs bij de hoogste bedrijfstemperatuur, de APS+ prestatie beter is dan de specificatie. In paragraaf 6.5, wordt de APS+ vergeleken met de andere equivalente zonnesensoren met betrekking tot resolutie, nauwkeurigheid, field of view, etc. De APS+ toont voordelen ten opzichte van de state-of-the-art. In paragraaf 6.6 wordt een μDSS apparaat uitgevoerd met de APS+ chip. Een conclusie van de algemene prestatie van de APS+ wordt gegeven aan het eind van het hoofdstuk in paragraaf 6.7.

Hoofdstuk 7 vat het werk in dit proefschrift samen en bespreekt een overzicht van de toekomstige werkzaamheden. In dit proefschrift wordt een nieuwe pixel-structuur voorgesteld. Dit pixel ontwerp maakt een WTA-principe voor beoordeling, en realiseert een energiezuinige dataverzameling-tracking operatiemodus in de APS+. Naast het pixel ontwerp wordt er een viervoudige bemonstering methode voorgesteld voor een lage-ruis ontwerp. De belangrijkste resultaten worden samengevat in paragraaf 7.1. In paragraaf 7.2 worden de potentiële toekomstige werkzaamheden beschreven. Een 4-T pixel structuur, die reële CDS kan realiseren om reset-ruis te annuleren, zou kunnen worden gerealiseerd in een volgend APS+ ontwerp. Een column-niveau ADC zou lagere uitlees bandbreedte kunnen bereiken, dus ook lagere uitlees ruis. Een optimaal uitleesmethode met een column ADC wordt voorgesteld om de APS+ vermogen zelfs verder te verminderen door het toenemen van de uitlees snelheid. De integratie van de μDSS apparaat is nog niet volledig geoptimaliseerd. Paragraaf 7.3 bespreekt de benaderingen om de grootte van het μDSS toestel verder te minimaliseren. In de μDSS toepassing leest de APS+ alleen de zonnevlek zwaartepunt informatie uit. Paragraaf 7.4 stelt een eenvoudige modificatie voor, waarbij de APS+ zal ook de lichtintensiteit informatie kunnen uitlezen. Dus de APS+ zou kunnen worden toegepast voor toepassingen waarbij zowel de attitude als de lichtintensiteit informatie nodig zijn. Zo zou de APS+ bij voorbeeld geschikt kunnen zijn voor toepassing in ruimtes, waar het verwarmingssysteem zelfstandig wordt aangepast op basis van de zonlicht invalshoek en lichtintensiteit.

Page 157: Low-Power Low-Noise CMOS Imager Design

Appendix

149

Appendix

A.1 The APS+ timing diagram in the acquisition and tracking mode

In this section, the complete timing charts of all control signals used by the APS+ during the acquisition and tracking mode are depicted. These control signals can either be supplied by off-chip FPGA for test purposes or be autonomously generated by the digital processing circuit, which was designed by TNO. The control signal description is presented in Table A.1. Figure A.1 and Figure A.2 show the complete timing chart during the acquisition and tracking modes, respectively.

Table A.1 Control signal description.

Signal Name Type Sensitivity Description

Clock input rising edgeGlobal clock input to the digital

processing circuit. The frequency is 3.6864MHz.

Address Bus input level The address bus is common for both the column decoder and row decoder. The

address bus is a 9-bit address.

Row Address Latch

input rising edgeA pulse that latches the address on

Address Bus onto the row addressing circuit.

Row Number Selected

n.a. n.a. This is simply an indication of the row

that is selected.

All Row Reset input rising edgeThis is a pulse that allows all rows to be

selected at once to be reset. This one overrules any other row reset definition.

Row Reset input active high The reset pulse that resets the pixels on

Page 158: Low-Power Low-Noise CMOS Imager Design

Appendix

150

Pulse the rows that are selected for reset.

Column Profile

input active highThis pulse enables column profiling. It is

active at high level.

Row Read Pulse

input active highA read out pulse that connects the pixels on a particular row to the column buses.

Sig Sample input active highPulse to sample the voltage which

contains the video level.

Rst Sample input active high Pulse to sample the reset voltage level.

Row Profile input active low This pulse enables row profiling. It is

active at low levels.

Column Address Latch

input rising edgeA pulse that latches the address on the

Address Bus onto the column addressing circuit.

Column Number Selected

n.a. n.a.

This is simply an indication of the column number that is being addressed for read out; this pulse is only used for

clarification.

Bus Reset input active highThe pulse that resets the signal bus and

reset bus before the column readout starts.

CDS Signal (Col Select

/Signal Sample Loop)

input active highThree inputs which have the same

timing. All for column readout.

CDS Reset input active high A pulse used for column readout.

ADC Clock input rising edge

A pulse needed by the on-chip ADC to indicate when the ADC conversion

starts. This pulse needs to be generated by the digital processing circuit. The frequency is a quarter of the global

Page 159: Low-Power Low-Noise CMOS Imager Design

Appendix

151

frequency (3.6864 MHz).

Data Number Available

n.a n.a

This is simply an indication of the data number that is being generated by the

ADC; this pulse is only used for clarification.

Page 160: Low-Power Low-Noise CMOS Imager Design

Appendix

152

Figure A.1 T

he APS+ tim

ing chart in the acquisition mode

Page 161: Low-Power Low-Noise CMOS Imager Design

Appendix

153

Figure A.2 T

he APS+ tim

ing chart in the tracking mode.

Page 162: Low-Power Low-Noise CMOS Imager Design

Appendix

154

A.2 The calculation of offset due to parasitic bus capacitors

Figure A.3 Schematic of the APS+ sample-hold array and analog chain.

Figure A.3 is the schematic of the APS column sample-hold array and analog chain. CS<K> and CR<K> are the sample-hold capacitors on the k’th column, which samples the signal and reset voltages, respectively. C1 and C2 are the parasitic capacitors on the Sig-bus and Rst-bus. CcpS<k> and CcpR<k> are the parasitic coupling capacitors between neighboring column buses; they are introduced by the neighboring long metal buses in the layout.

During a Quadruple Sampling process, two subtractions are done on the analog chain: S1-S2 and S4-S3 (referring to the timing diagram in Figure 5.4). In these subtractions, the sequence between “sig_sample” and “rst_sample” are different. Thus different offset levels are introduced into S1-S2 and S4-S3, resulting in an offset at the node of “Amp_out” in Figure A.3.

Figure A.4 is the schematic of three column buses with coupling capacitors. In this figure, there are three column buses: C-bus<0:2>, when “sig_sample” is active, each column simultaneously samples voltage to the signal-sample capacitors; CS<0:2>, when “rst_sample” is active, voltages are sampled to reset-sample capacitors; and CR<0:2>, the value of all sample-hold capacitors (CS<0:2> and CR<0:2>) is 1pF. Every column’s signal buses (sig<0:2>) are connected to the common signal bus (Sig-bus) with a bus capacitor of 1.2pF, every column’s reset buses (rst<0:2>) are connected to the common reset bus (Rst-bus), and the bus capacitor is also 1.2pF. In this schematic, coupling capacitors are considered. CCP<1> is the coupling

Page 163: Low-Power Low-Noise CMOS Imager Design

Appendix

155

capacitor between the buses of rst<0> and sig<1>, while CCP<2> is the one between rst<1> and sig<2>. The following analysis refers to this simplified schematic.

Figure A.4 Schematic of three column buses with coupling capacitors.

Since every column has the same structure, in the discussion only the part of the circuits which are related to Ccp<1> are analyzed as an example for simplification. The voltages on the reset bus of the C-bus<0> (rst<0>) and the signal bus of the C-bus<1> (sig<1>) are influenced by the coupling capacitor Ccp<1>. The voltage changes due to the Ccp<1> are discussed below; the results can be applied to all other

Page 164: Low-Power Low-Noise CMOS Imager Design

Appendix

156

column buses. In the design, both sample-hold capacitors on each column are 1pF; the capacitors on the Sig_bus and Rst_bus, C1 and C2, are 1.2pF.

The discussion is divided into two cases. In Case1 the “rst_sample” pulse comes before that of “sig_sample”; while in Case2 the “sig_sample” pulse comes before “rst_sample”.

A.2.1 Case 1: “rst_sample” pulse comes first

Figure A.5 Timing diagram in case 1:“rst_sample” comes before “sig_sample”.

The first case analyzed is when the “rst_sample” pulse comes before the “sig_sample”. The timing diagram in this case is illustrated in Figure A.5. During different time intervals (T1 to T4 as indicated in Figure A.5), the schematic in Figure A.4 is in different situations with the coupling capacitors. Assume the voltage level on every column bus (C-bus<0:2>) is constantly Vi, which is a DC voltage, and the initial voltages of all the capacitors are 0. The voltages on the nodes of C+

cp<1>/ C+R<0> and C-

cp<1>/ C+S<1> (as indicated in Figure A.4) in this process can

be summarized as in Table A.2. Although only the part of the circuit related to Ccp<1> is discussed, the results can be applied to all other column circuits.

Page 165: Low-Power Low-Noise CMOS Imager Design

Appendix

157

Table A.2 The voltages on different nodes during T1 to T4.

C+cp<1>/ C+

R<0> C-cp<1>/ C+

S<1>

Initial 0 0

T1 Vi 1

11 1

cpi

cp S

CV V

C C< >

< > < >

=+

i

T2 1 0 1 12

1 0

(2 )cp R i cp

cp R

C C V C VV

C C< > < > < >

< > < >

+ −=

+

i i Vi

T3 0 12

0 1 1

22

R cpR

R cp

C CV V

C C C< > < >

< > < >

+

+ +i 1 1

3 21 1 0 1 12

cpi

S cp R cp

C CV V VC C C C C

< >

< > < > < > < >

−+ + +

i i

T4 1 24 3

0 1 1 2

cpR

R cp S

C CV V VC C C C

< >

< > < > < >

= −+ +

i i 13

1 2

SS

S

CV VC C

< >

< >

=+

i

Based on the expressions in Table A.2, the node voltages in each interval with different coupling capacitors values can be derived. The coupling capacitor is 0pF ideally. The layout shown in Figure 5.8 introduces a coupling capacitor of 0.1pF approximately. The node voltages of these two cases are listed in the tables below.

Table A.3 The voltages on different nodes: Vi=2V, Ccp<1>=1fF, CR<0> =CS<1>=1pF, and C1=C2=1.2pF.

C+cp<1>/ C+

R<0> C-cp<1>/ C+

S<1>

Initial 0 0

T1 Vi=2V V1=0

T2 V2=2V Vi=2V

T3 VR=0.91V V3=2V

T4 V4=0.91V VS=0.91V

Page 166: Low-Power Low-Noise CMOS Imager Design

Appendix

158

Table A.4 The voltages on different nodes: Vi=2V, Ccp<1>=0.1pF, CR<0> =CS<1>=1pF, and C1=C2=1.2pF.

C+cp<1>/ C+

R<0> C-cp<1>/ C+

S<1>

Initial 0 0

T1 Vi=2V V1=0.18V

T2 V2=2.16V Vi=2V

T3 VR=1.03V V3=1.90V

T4 V4=0.93V VS=0.90V

It is necessary to point out that although the VR calculated in the above analysis is the Rst_bus voltage when the col<0> is active, the result of VR also works when the col<1> is active. This is because of the assumption that all coupling capacitors are the same size, and that every column has exactly the same structure. Since two coupling capacitors are involved in the sub-circuit of the C-bus<1>, the voltages on Rst_bus and Sig_bus when col<1> is active emulate the situation in reality.

The simulation with the circuits in Figure A.4 was done with coupling capacitors of 1fF and 0.1pF, respectively. The timing in this simulation refers to Figure A.5. The results are shown in Figure A.6, under the same conditions as listed in Table A.3 and Table A.4. The simulation results are in accordance with the results in the tables, which were derived from the circuit analysis in this section. It shows that when the coupling capacitor is relatively large (0.1pF), the outputs at “Rst_bus” and “Sig_bus” have an offset even with the same inputs.

Page 167: Low-Power Low-Noise CMOS Imager Design

Appendix

159

Figure A.6 Simulation results with different coupling capacitor values when “rst_sample” comes first.

Page 168: Low-Power Low-Noise CMOS Imager Design

Appendix

160

A.2.2 Case 2: “sig_sample” pulse comes first

Figure A.7 Timing diagram in case 2:“sig_sample” comes before “rst_sample”.

The second case analyzed is when the “rst_sample” pulse comes before the “sig_sample”. The timing diagram in this case is illustrated in Figure A.7. Similar to the analysis in the first case, the schematic in Figure A.4 was analyzed in different situations during T5 to T8. Assume the voltage level on every column bus (C-bus<0:2>) is constantly a DC voltage Vi and the initial voltages of all the capacitors are 0. The voltages on nodes of C+

cp<1>/ C+R<0> and C-

cp<1>/ C+S<1> (as indicated in

Figure A.4) in this process can be summarized as in Table A.5. Although only the part of the circuit related to Ccp<1> is discussed, the results can be applied to all other column circuits.

Page 169: Low-Power Low-Noise CMOS Imager Design

Appendix

161

Table A.5 The voltages on different nodes during T5 to T8.

C+cp<1>/ C+

R<0> C-cp<1>/ C+

S<1>

Initial 0 0

T5 15

1 0

cpi

cp R

CV V

C C< >

< > < >

=+

i Vi

T6 Vi 1

6 51 1

( - )cpi i

cp S

CV V V V

C C< >

< > < >

= ++

i

T7 0 1

0 1 1

R cpR i

R cp

C CV V

C C C< > < >

< > < >

+

+ +i 1 1

7 61 1 0 1 1( )( )

cpi

S cp R cp

C CV V V

C C C C C< >

< > < > < > < >

−+ + +

ii

T8 2 18 7

0 1 1 2

-( ) ( )

cpR

R cp S

C CV V V

C C C C< >

< > < > < >

=+ +

ii

i1 11

1 2 1 1

2S cpSS i

S S cp

C CCV VC C C C

< > < >< >

< > < > < >

+

+ +i i

Based on the analysis summarized in Table A.5, the node voltages with different coupling capacitors values can be derived. The coupling capacitor is 0pF ideally. The layout shown in Figure 5.8 introduces a coupling capacitor of 0.1pF approximately. The node voltages of these two cases are listed in the tables below.

Table A.6 The voltages on different nodes: Vi=2V, Ccp<1>=1fF, CR<0> =CS<1>=1pF, and C1=C2=1.2pF.

Initial T5 T6 T7 T8

C+cp<1>/ C+

R<0> 0 0 Vi=2V VR=0.91V V8=0.91V

C-cp<1>/ C+

S<1> 0 Vi=2V V6=2V V7=2V VS=0.91V

Page 170: Low-Power Low-Noise CMOS Imager Design

Appendix

162

Table A.7 The voltages on different nodes: Vi=2V, Ccp<1>=0.1pF, CR<0> =CS<1>=1pF, and C1=C2=1.2pF.

Initial T5 T6 T7 T8

C+cp<1>/

C+R<0>

0 V5=0.18V Vi=2V VR=0.95V V8=0.85V

C-cp<1>/

C+S<1>

0 Vi=2V V6=2.16V V7=2.07V VS=0.98V

It is also helpful to point out that although the VR calculated in the above analysis is the Rst_bus voltage when the col<0> is active, the result of VR works the same when the col<1> is active. This is because of the assumption that all coupling capacitors are the same size, and that every column has exactly the same structure.

Although the VR calculated in the above analysis is the Rst_bus voltage when the col<0> is active, the result of VR also works when the col<1> is active. Since two coupling capacitors are involved in the sub-circuit of the C-bus<1>, the voltages on Rst_bus and Sig_bus when col<1> is active emulate the situation in reality.

The simulations with the circuits in Figure A.4 were done with coupling capacitors of 1fF and 0.1pF, respectively. The timing in this simulation refers to Figure A.7. The results are shown in Figure A.8, under the same conditions listed in Table A.6 and Table A.7. The simulation results are in accordance with the expressions in Table A.5. It shows that due to the relatively large coupling capacitors (0.1pF), the outputs at “Rst_bus” and “Sig_bus” have an offset. Compared to the results in Figure A.6, when “sig_sample” comes first, the introduced offset has the opposite polarity of the offset if “rst_sample” come first.

Page 171: Low-Power Low-Noise CMOS Imager Design

Appendix

163

Figure A.8 Simulation results with different coupling capacitor values when “sig_sample” comes first.

The offset introduced by the parasitic coupling capacitors is discussed in this section. In order to reduce the offset effect, the layout needs to be optimized for the coupling capacitor. This improvement is presented in the thesis in Section 5.4. After modification, the accuracy effect by the offset due to parasitic coupling capacitors can be ignored in the APS+.

Page 172: Low-Power Low-Noise CMOS Imager Design

Appendix

164

A.3 The APS+ application program

Figure A.9 A snapshot of the interface program.

A snapshot of the APS+ application program is shown in Figure A.9. The transmit commands in the left part can be sent to the APS+. The programmable commands include MODE, IT-ACQ and IT-TRACK. The APS+ work mode is programmable depending on different “MODE” parameters. It can work in the acquisition or tracking mode separately or autonomously in the continuous acquisition-tracking mode. The integration time in the acquisition and tracking mode can be adjusted by the “IT-ACQ” and “IT-TRACK” parameters, respectively. A value of 70 as the parameter of “IT-ACQ” or “IT-TRACK” refers to an integration time of 3ms, which is the design specification. The spectral filter (as shown in Figure 3.4) is adjusted based on the saturation level with an integration time of 3ms.

The received data from the APS+ is displayed in the right part. The Pos X0 and Pos Y0 are the outputs of the acquisition mode, which indicate the coarse location of the sun spot. The PosXB and PosYB are the outputs of the tracking mode. X0 and Y0 are the pixel coordinates referring to the coarse location. XB and YB

Page 173: Low-Power Low-Noise CMOS Imager Design

Appendix

165

present the sun spot’s fine position. They are sub-pixel coordinates with respect to the center of the pixel, which is indicated by X0 and Y0. The full range of XB and YB is limited to ±1 pixel, which is represented by the range of (-64, +63). In other words, the centroid resolution of the APS+ is 1/64 pixel pitch. Considering the sun sensor’s Field of View (FoV) is over the range of ±50º, the centroid resolution refers to a resolution of 0.004º in terms of the satellite’s attitude angle. The relation between X0 Y0 and XB YB is illustrated in Figure A.10.

Figure A.10 Illustration of X0, Y0 and XB, YB.

Page 174: Low-Power Low-Noise CMOS Imager Design

Abbreviations

166

Abbreviations

ADC: Analog-to-Digital converter

APS: active pixel sensor

ADC: A-to-D converter:

CDS: correlated double sampling

CMOS: complementary metal–oxide–semiconductor

COX: gate oxide capacitance per unit area

DR: Dynamic range

DDS: delta double sampling

FoV: Field of View

FPN: fixed pattern noise

ITO: indium tin oxide

JPL: Jet Propulsion Laboratory

PTC: Photon Transfer Curve

PPS: passive pixel sensor

ROI: Region of Interest

SEU: Single Event Upset

SoC : System on Chip

SNR: signal-to-noise ratio

S-H array: sample-hold array

VTH: threshold voltage of a MOS transistor

WTA: Winner-Take-All

μ: mobility coefficient

µDSS: micro-Digital Sun Sensor

Page 175: Low-Power Low-Noise CMOS Imager Design

List of publications

167

List of Publications

Peer-reviewed articles

Ning Xie, Albert Theuwissen, “A Low-Power High-Accuracy Micro-Digital Sun Sensor by Means of a CMOS Image Sensor”, submitted for publication in Journal of Electronic Imaging.

Ning Xie, Albert Theuwissen, “A Miniaturized Micro-Digital Sun Sensor by Means of Low-Power Low-Noise CMOS Imager”, submitted for publication in Sensors & Actuators: A. Physical.

Conference proceedings

Ning Xie, Albert Theuwissen, Bernhard Buettgen, “An Autonomous micro-Digital Sun Sensor Implemented with a CMOS Image Sensor Achieving 0.004º Resolution @ 21 mW”, 2011 International Image Sensor Workshop, Hakodate-Hokkaido (Japan), pp. 208-211.

Ning Xie, Albert Theuwissen, “An autonomous low power high resolution micro-digital sun sensor”, International Symposium on Photoelectric Detection and Imaging”, Beijing, May 24-26, 2011.

Ning Xie, Albert Theuwissen, Bernard Buettgen, Henk Hakkesteegt, Henk Jansen, Johan Leijtens, “The APS+: an intelligent active pixel sensor centered on low power”, International Conference on Space Optics, Oct. 4-8, 2010, Rhodes (Greece).

Ning Xie, Albert Theuwissen, Bernard Buettgen, Henk Hakkesteegt, Henk Jansen, Johan Leijtens, “Micro-Digital Sun Sensor: An imaging sensor for space

Page 176: Low-Power Low-Noise CMOS Imager Design

List of publications

168

applications”, Proceeding of IEEE International Industrial Electronics (ISIE) 2010, pp. 3362-3365.

Ning Xie, Albert J.P. Theuwissen, Xinyang Wang, “A CMOS image sensor with row and column profiling means”, IEEE Sensors 2008 Conference Proceedings, pp. 1356-1359, Oct. 2008.

Bart de Boer, Murat Durkut, Johan Leijtens, Erik Laan, Albert Theuwissen, Ning Xie, Henk Hakkesteegt, Enrique Urquijo, Peter Bruins, “MiniDSS: A low-power and high-precision miniaturized digital sun sensor”, poster at International Conference on Space Optics, Oct. 9-12 2012, Ajaccio, Corse, France.

Johan Leijtens, Ning Xie, Albert Theuwissen, “The APS+ and why we dare going without DARE”, 3rd International Workshop on Analog and Mixed Signal Integrated Circuits for Space Applications, Sept. 5-7, 2010, Noordwijk (Netherlands).

Johan Leijtens, Albert Theuwissen, Padmakumar Rao, Xinyang Wang, Ning Xie, “Active pixel sensors: the sensor of choice for future space applications”, SPIE Europe Remote Sensing Conf., Florence (Italy), Sept. 17-20, 2007.

Workshop contributions

Ning Xie, “An autonomous micro-digital sun sensor achieving 0.004º resolution @21mW”, presentation in the Student Research Review at International Solid-State Circuits Conference, Feb. 2011.

Page 177: Low-Power Low-Noise CMOS Imager Design

Acknowledgements

169

Acknowledgements

When I started writing this part of my thesis, I realized I am reaching the end of my PhD work, which has been a very long but exciting exploration. I would like to take this opportunity to express my appreciation to everyone who accompanied me in this journey. Without anyone of you, I could have never finished this dissertation.

This thesis has been supported by the Dutch Technology Foundation (STW) under project number 05869. Their support is gratefully acknowledged.

I would like to deeply thank my promoter Prof. Albert Theuwissen, who opened the gate of the image sensor world to me. During these years, he has not only given me patient supervising and insightful instruction, but also set an example as a dedicated and open-minded scientist and researcher. It is his encouragement and support that helped to make this thesis a reality.

I heartily thank the committee members, Dr. B. Bernhard, Prof. P. Magnan, Prof. G. Meijer, Prof. P. French, Dr. M. Graef, Prof. Ronald Dekker and Prof. H. Huijsing, for their valuable comments, which enabled me to make the necessary improvements.

I must offer my thanks to Martijn Snoeij and Xinyang Wang for their great help at the beginning of my project. I also want to thank Bongki, Bernhard and Mukul, who were the post-doctorates of our imaging group. I really appreciate all your patience and discussions even when you were extremely busy with your own projects. My sincere thanks go to my group members, Yue, Gayathri, Rao, Jiaming and Yang. It was a pleasure to work together with you and I enjoyed every discussion and talk-academic and non-academic- with you. I would like to thank Adri Mierop and Jacobus de Meulmeester, who helped me with chip measurements and chip design when they were working at DALSA, and also our technician Marc Horemans.

I want to thank my colleagues at TNO for their cooperation, important discussions and feedback in this project: Johan Leijtens, Henk Hakkesteegt, and Henk Jansen.

Page 178: Low-Power Low-Noise CMOS Imager Design

Acknowledgements

170

Thanks to Prof. Paddy French and Prof. Kofi Makinwa, who made the Electronic Instrumentation Laboratory a warm and friendly family. Thanks to all my colleagues especially to Joyce Siemers, Adri Roos-Rouffaer, Jawad Jodeh, Willem van der Sluys, Ilse van der Kraaij and Karen van Busschbach for all their administrative and financial support. I would like to thank Zu-yao Chang, Piet Trimp, Jeroen Bastemeijer, Jeff Mollinger, Antoon Frehe, and Maureen Meekel for their help with technical, instrumental and IT problems, and especially my profound thanks to Zu-yao, who gave me indispensable help with my chip measurement and made my life in the Netherlands much easier than it could have been. Many thanks go to my present and former roommates: Sha, Rong, Darko, Mohammadamir, and Vijayekumar, for providing a nice research environment.

Many thanks are given to my beloved friends who made my life warm and pleasant: Zhichao, Huaiwen, Yifan Lai, Ruimin, Chi, Zili, Qi, Kerong, Lei, Youngcheol, Qinwen, Saleh, Caspar, Eduardo, Karfee, Wanghua, Rui, Wei, Fa, Jiansong, Jie (good luck to your baby), Yudy, Mario, Dada, Meike, Yifan He, Songyue and Shuang. I am also grateful to Dr. Li and Dr. Wang for their care in the past years. I would like to thank all my friends in the Netherlands, China, on MSN and Weibo, all of whom I cannot name here.

I am grateful to Sarah for her revisions of the English text of this thesis.

Last but not the least, I would like to thank my parents Hailong Xie and Jiqing Yang for their unconditional love and encourage. It is what you have taught me that makes me who I am. Thanks to my husband Yu Chen, for his love, affection and understanding.

Ning Xie

Delft, June 2012

Page 179: Low-Power Low-Noise CMOS Imager Design

About the author

171

About the Author

Ning Xie was born in Jilin City, Jilin Provence, China, in 1982. She received her B.Sc. degree in Electronic and Information Engineering from Zhejing University, China in June 2004. She completed the M.Sc. degree of Microelectronics at Delft University of Technology, the Netherlands in 2007 and is continuing her Ph.D. study in

the Electronic Instrumentation Laboratory. The subject of her research is low-power low-noise CMOS image sensor design. Her project is the design of the Micro-Digital Sun Sensor applied for micro- and nano-satellites.

Page 180: Low-Power Low-Noise CMOS Imager Design