LEAKAGE POWER REDUCTION TECHNIQUES

FOR CMOS CIRCUIT DESIGN

Submitted by: Submitted to:Anamika Pancholi Ms. Vandana Niranjan

02702072014 Asst. Professor, ECE Dept.M.Tech(VLSI Design) IGDTUW, Delhi

2014‐2016

CONTENTSIntroduction

Previous Work

Sleep Mode Approach

Stack Mode Approach

Leakage Feedback Approach

Sleepy Stack Approach

Sleepy Keeper Approach

Proposed Lector Technique

Conclusion

Introduction

In order to achieve high density and high

performance, CMOS technology feature size and

threshold voltage have been scaling down for decades.

As the feature size becomes smaller, shorter channel

lengths result in increased subthreshold leakage

current through a transistor when it is off. Low

threshold voltage also results in increased

subthreshold leakage current because transistors

cannot be turned off completely.

Leakage power consumption is an important issue inDSM CMOS VLSI circuit. The main Contribution ofPower dissipation in CMOS circuit increases with thereduction of channel length, Threshold voltage and gateoxide thickness.

The power dissipation of a logic gate is given by

Pavg /gate = Pswitching + Pshort circuit +Pleakage

Subthreshold leakage current (Isub) in MOStransistors, which occurs when the gate voltage isbelow the threshold voltage and mainly, consists ofdiffusion current.

•Diode reverse bias

current–I1

•Sub threshold current – I2

•Gate induced drain

leakage – I3

•Gate oxide tunneling – I4

Fig.1. Leakage Mechanism in Short-Channel NMOS Transistor

Leakage Power Reduction Techniques

Sleep Mode Approach

• An additional "sleep" PMOStransistor is placed betweenVDD and the pull-up networkof a circuit and

• An additional "sleep" NMOStransistor is placed betweenthe pull-down network andGND. These sleep transistorsturn off the circuit by cuttingoff the power rails.

• By cutting off the powersource, this technique canreduce leakage powereffectively

Fig.2. Sleep Approach NAND gate

Stack ApproachIn the stack approach, whichforces a stack affect bybreaking down an existingtransistor into two half sizetransistors. Subthresholdleakage is exponentiallyrelated to the thresholdvoltage of the device, andthe threshold voltagechanges due to body effect.From these two facts, onecan reduce the subthresholdleakage in the device bystacking two or moretransistors serially .

Fig.3. Stack Approach based 2 input NAND gate

Leakage Feedback ApproachIn this approach we use two

parallel PMOS transistor above

pull up network and Vdd . To

provide the inverting output of

the circuit we connect inverter

at the output, an inverter

provides the proper logic

feedback to both pull down

NMOS(S') and pull up

PMOS(S) sleep transistor as

shown in Fig.4. This two

transistor enhance the circuit

performance and maintain the

proper logic of the circuit

during standby mode.Fig.4. Leakage Feedback Approach

SLEEPY STACK APPROACH

Fig. 5. Sleepy Stack Approach based 2 input NAND gate

The main idea behind the sleepy stack technique is tocombine the sleep transistor approach during activemode with the stack approach during sleep mode.

The stacked transistors in the sleepy stack approachsuppress leakage current. Although the sleeptransistors are turned off, the sleepy stack structuremaintains exact logic state.

The leakage reduction of the sleepy stack structureoccurs in two ways. First, leakage power issuppressed by high- transistors, which are applied tothe sleep transistors and the transistors parallel to thesleep transistors.

Second, stacked and turned off transistors induce the

stack effect which also suppresses leakage power

consumption. By combining these two effects, the

sleepy stack structure achieves ultra-low leakage power

consumption during sleep mode while retaining exact

logic state

The price for this, however, is increased area

Sleepy Keeper ApproachIn this approach combination

of PMOS and NMOS transistor

which is connected paralleled

inserted between pull up

network and Vdd and pull

down and GND, NMOS

transistor of pull up sleep

transistor connected PMOS

pull down sleep transistor.

This approach reduces the

leakage power efficiently and

maintains the proper logic of

the circuit with lesser area.

Fig.6. Sleepy keeper Approach based 2 input NAND gate

PROPOSED LECTOR TECHNIQUE

Fig. 6. Proposed technique Sleepy Lector with high Vth transistors

In LECTOR technique two leakage control transistors (one p-

type and one n-type) are introduced between pull-up and pull-

down circuit within the logic gate for which the gate terminal

of each leakage control transistor (LCT) is controlled by the

source of the other. This arrangement ensures that one of the

LCTs always operates in its near cut off region.

The basic idea behind LECTOR approach is that “a state with

more than one transistor OFF in a path from supply voltage to

ground is far less leaky than a state with only one transistor

OFF in any supply to ground path.

In case of near cut off operation of transistors the resistance of

transistor is as high as an OFF transistor’s resistance but the

available resistance is sufficient to increase the supply voltage

to ground path resistance and so to reduce the leakage power

dissipation.

CONCLUSION

Leakage reduction technique plays a key role in VLSI

circuit design. Scaling down the appropriate

parameter can reduce the leakage power. it can be

concluded that there is a strong correlation between

three performance parameters: leakage power, delay,

power delay product.

LECTOR method found more effective in both

standby and active mode of operation. If propagation

delay is taken as the performance metrics, then sleep

transistor method is proved effective method in the

standby mode. In active mode, sleepy stack based

approach is suitable for faster circuit operation.